mirror of https://github.com/ARMmbed/mbed-os.git
MPU - use higher-level calls, fix ARMv8-M error
Switch to higher-level calls and macros, and fix an error in the ARMv8-M version - "inner" attributes were not being set correctly due to a copy/paste error - "outer" was being set twice. This means RAM would have been marked WTRA rather than WBWA for the inner cache. Slightly reduces ARMv7-M init code size by feeding region number into RBAR instead of using RNR.pull/9208/head
Kevin Bracey
Cruz Monrreal II
parent
60451368a8
commit
263129a300
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@ -74,13 +74,12 @@ void mbed_mpu_init()
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* 0xE0000000 - 0xFFFFFFFF System No
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*/
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// Select region 1 and used it for the WT rom region
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// - RAM 0x00000000 to MBED_MPU_ROM_END
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MPU->RNR = 0;
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// Set address to 0
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MPU->RBAR = 0;
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// Configure and enable region
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MPU->RASR =
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// Select region 0 and use it for the WT read-only rom region
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// - Code 0x00000000 to MBED_MPU_ROM_END
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ARM_MPU_SetRegion(
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ARM_MPU_RBAR(
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0, // Region
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0x00000000), // Base
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ARM_MPU_RASR(
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0, // DisableExec
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ARM_MPU_AP_RO, // AccessPermission
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@ -97,16 +96,15 @@ void mbed_mpu_init()
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((MBED_MPU_ROM_END >= 0x14000000) ? 0 : (1 << 5)) |
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((MBED_MPU_ROM_END >= 0x18000000) ? 0 : (1 << 6)) |
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((MBED_MPU_ROM_END >= 0x1C000000) ? 0 : (1 << 7)),
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ARM_MPU_REGION_SIZE_512MB // Size
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);
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ARM_MPU_REGION_SIZE_512MB) // Size
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);
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// Select region 1 and used it for the WT rom region
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// - RAM MBED_MPU_ROM_END + 1 to 0x1FFFFFFF
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MPU->RNR = 1;
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// Set address to 0
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MPU->RBAR = 0;
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// Configure and enable region
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MPU->RASR =
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// Select region 1 and use it for a WT ram region in the Code area
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// - Code MBED_MPU_ROM_END + 1 to 0x1FFFFFFF
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ARM_MPU_SetRegion(
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ARM_MPU_RBAR(
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1, // Region
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0x00000000), // Base
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ARM_MPU_RASR(
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1, // DisableExec
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ARM_MPU_AP_FULL, // AccessPermission
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@ -123,17 +121,16 @@ void mbed_mpu_init()
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((MBED_MPU_RAM_START <= 0x18000000) ? 0 : (1 << 5)) |
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((MBED_MPU_RAM_START <= 0x1C000000) ? 0 : (1 << 6)) |
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((MBED_MPU_RAM_START <= 0x20000000) ? 0 : (1 << 7)),
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ARM_MPU_REGION_SIZE_512MB // Size
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);
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ARM_MPU_REGION_SIZE_512MB) // Size
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);
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// Select region 2 and used it for WBWA ram regions
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// Select region 2 and use it for WBWA ram regions
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// - SRAM 0x20000000 to 0x3FFFFFFF
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// - RAM 0x60000000 to 0x7FFFFFFF
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MPU->RNR = 2;
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// Set address to 0
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MPU->RBAR = 0;
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// Configure and enable region
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MPU->RASR =
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ARM_MPU_SetRegion(
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ARM_MPU_RBAR(
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2, // Region
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0x00000000), // Base
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ARM_MPU_RASR(
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1, // DisableExec
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ARM_MPU_AP_FULL, // AccessPermission
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@ -150,16 +147,15 @@ void mbed_mpu_init()
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(1 << 5) | // Disable Sub-region
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(1 << 6) | // Disable Sub-region
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(1 << 7), // Disable Sub-region
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ARM_MPU_REGION_SIZE_4GB // Size
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);
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ARM_MPU_REGION_SIZE_4GB) // Size
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);
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// Select region 3 and used it for the WT ram region
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// - RAM RAM 0x80000000 to 0x9FFFFFFF
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MPU->RNR = 3;
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// Set address
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MPU->RBAR = 0x80000000;
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// Configure and enable region
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MPU->RASR =
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// Select region 3 and use it for the WT ram region
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// - RAM 0x80000000 to 0x9FFFFFFF
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ARM_MPU_SetRegion(
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ARM_MPU_RBAR(
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3, // Region
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0x80000000), // Base
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ARM_MPU_RASR(
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1, // DisableExec
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ARM_MPU_AP_FULL, // AccessPermission
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@ -168,8 +164,8 @@ void mbed_mpu_init()
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1, // IsCacheable
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0, // IsBufferable
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~0U, // SubRegionDisable
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ARM_MPU_REGION_SIZE_512MB // Size
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);
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ARM_MPU_REGION_SIZE_512MB) // Size
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);
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// Enable the MPU
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MPU->CTRL =
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@ -47,7 +47,7 @@ void mbed_mpu_init()
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// Reset all mapping
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for (uint32_t i = 0; i < regions; i++) {
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ARM_MPU_ClrRegionEx(MPU, i);
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ARM_MPU_ClrRegion(i);
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}
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/*
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@ -64,61 +64,67 @@ void mbed_mpu_init()
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* 0xE0000000 - 0xFFFFFFFF System No
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*/
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uint32_t region;
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uint8_t outer;
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uint8_t inner;
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const uint8_t WTRA = ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0); // Non-transient, Write-Through, Read-allocate, Not Write-allocate
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const uint8_t WBWARA = ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1); // Non-transient, Write-Back, Read-allocate, Write-allocate
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enum {
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AttrIndex_WTRA,
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AttrIndex_WBWARA,
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};
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region = 0;
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MPU->RNR = region;
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outer = 0xA; // Write-Through, Non-transient, Read-allocate
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inner = 0xA; // Write-Through, Non-transient, Read-allocate
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ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
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MPU->RBAR = (0x00000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x00000000
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(0 << MPU_RBAR_SH_Pos) | // Not shareable
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(3 << MPU_RBAR_AP_Pos) | // RO allowed by all privilege levels
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(0 << MPU_RBAR_XN_Pos); // Execute Never disabled
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MPU->RLAR = (0x1FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x1FFFFFFF
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(region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number
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(1 << MPU_RLAR_EN_Pos); // Region enabled
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ARM_MPU_SetMemAttr(AttrIndex_WTRA, ARM_MPU_ATTR(WTRA, WTRA));
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ARM_MPU_SetMemAttr(AttrIndex_WBWARA, ARM_MPU_ATTR(WBWARA, WBWARA));
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region = 1;
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MPU->RNR = region;
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outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
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outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
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ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
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MPU->RBAR = (0x20000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x20000000
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(0 << MPU_RBAR_SH_Pos) | // Not shareable
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(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
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(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
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MPU->RLAR = (0x3FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x3FFFFFFF
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(region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number
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(1 << MPU_RLAR_EN_Pos); // Region enabled
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ARM_MPU_SetRegion(
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0, // Region
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ARM_MPU_RBAR(
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0x00000000, // Base
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ARM_MPU_SH_NON, // Non-shareable
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1, // Read-Only
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1, // Non-Privileged
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0), // Execute Never disabled
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ARM_MPU_RLAR(
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0x1FFFFFFF, // Limit
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AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate
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);
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region = 2;
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MPU->RNR = region;
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outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
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outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
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ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
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MPU->RBAR = (0x60000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x60000000
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(0 << MPU_RBAR_SH_Pos) | // Not shareable
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(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
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(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
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MPU->RLAR = (0x7FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x7FFFFFFF
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(region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number
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(1 << MPU_RLAR_EN_Pos); // Region enabled
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ARM_MPU_SetRegion(
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1, // Region
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ARM_MPU_RBAR(
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0x20000000, // Base
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ARM_MPU_SH_NON, // Non-shareable
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0, // Read-Write
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1, // Non-Privileged
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1), // Execute Never enabled
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ARM_MPU_RLAR(
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0x3FFFFFFF, // Limit
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AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate
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);
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region = 3;
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MPU->RNR = region;
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outer = 0xA; // Write-Through, Non-transient, Read-allocate
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inner = 0xA; // Write-Through, Non-transient, Read-allocate
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ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
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MPU->RBAR = (0x80000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x80000000
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(0 << MPU_RBAR_SH_Pos) | // Not shareable
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(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
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(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
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MPU->RLAR = (0x9FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x9FFFFFFF
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(region << MPU_RLAR_AttrIndx_Pos) | // Attribute index - configured to be the same as the region number
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(1 << MPU_RLAR_EN_Pos); // Region enabled
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ARM_MPU_SetRegion(
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2, // Region
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ARM_MPU_RBAR(
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0x60000000, // Base
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ARM_MPU_SH_NON, // Non-shareable
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0, // Read-Write
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1, // Non-Privileged
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1), // Execute Never enabled
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ARM_MPU_RLAR(
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0x7FFFFFFF, // Limit
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AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate
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);
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ARM_MPU_SetRegion(
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3, // Region
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ARM_MPU_RBAR(
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0x80000000, // Base
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ARM_MPU_SH_NON, // Non-shareable
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0, // Read-Write
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1, // Non-Privileged
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1), // Execute Never enabled
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ARM_MPU_RLAR(
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0x9FFFFFFF, // Limit
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AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate
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);
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// Enable the MPU
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MPU->CTRL =
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