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306 Commits (16a40c9f9c3883ba1cbdb775d22c1884911dfc63)

Author SHA1 Message Date
Martin Kojtal 6111b8dfcc
Merge pull request #12828 from dustin-crossman/pr/update-cysbsyskit_01 
Update CYSBSYSKIT_01
 2020-04-21 10:13:38 +02:00
Martin Kojtal aec6303437
Merge pull request #12787 from kyle-cypress/pr/cyeskit-064b0s2-4343w 
Cypress: Add CYESKIT-064B0S2-4343W
 2020-04-21 10:08:40 +02:00
Dustin Crossman d9655da2e8 Update COMPONENT_SCL 2020-04-17 13:13:18 -07:00
Dustin Crossman 2148fa5ab9 Update CYSBSYSKIT_01 BSP 2020-04-17 13:13:18 -07:00
Martin Kojtal a79d3ce18d
Merge pull request #12271 from jainvikas8/jae-feature-twincpu-6-mbed-os-integration 
Make cypress psoc64 TFM ready and also add TF-M initialization
 2020-04-17 15:48:58 +02:00
Kyle Kearney 76a14f2ff4 Cypress: Fix unitialized memory in spi_master_write 
'received' was declared as an int but populated by cyhal_spi_transfer
after being cast to to (uint8_t *), which left the upper 3 bytes
uninitialized. Instead, declare as uint8_t and let the compiler upcast
the value when it is returned.
 2020-04-16 16:54:12 -07:00
Jaeden Amero 07a84ec10a psa: Remove MBED_SPM code 
All MBED_SPM targets have been removed previously, via commits
5cc66282dd ("PSOC6: remove PSA targets") and 115b09aba43b ("psoc6:
Remove FUTURE_SEQUANA and FUTURE_SEQUANA_M0"). Remove all the dead
MBED_SPM code, as no targets use it.

Signed-off-by: Jaeden Amero <jaeden.amero@arm.com>
 2020-04-16 14:10:54 +01:00
Sree Harsha Angara b77a5b331c Removed NVRAM references to CY8CKTI_064B0S2_4343W Kit 2020-04-08 11:32:27 -07:00
Sree Harsha Angara 63b93ff696 Removing ES100 references and CY8CKIT_064B0S2_4343W 2020-04-08 11:28:58 -07:00
Sree Harsha Angara 118b4b3df1 Fixing clock for greentea cordio test 2020-04-07 14:43:29 -07:00
Sree Harsha Angara 3b6020c1be Updating BSP files for CYESKIT_064B0S2_4343W 2020-04-06 17:12:23 -07:00
Roman Okhrimenko 70c9142647 Add wifi_nvram_image for TARGET_CYESKIT_064B0S2_4343W 2020-04-05 13:52:27 +03:00
Roman Okhrimenko 69d0721e30 Add BSP for CYESKIT_064B0S2_4343W 2020-04-05 13:52:27 +03:00
Roman Okhrimenko d3813a318a Add latest prebuild hex file 2020-04-05 13:52:27 +03:00
Roman Okhrimenko c4e8f8d816 Comment out init_cycfg_system() to avoid HardFault before Secure Driver arrive 2020-04-05 13:52:27 +03:00
Roman Okhrimenko 89531b9163 Add essential file for peripheral pins definition 2020-04-05 13:52:27 +03:00
Roman Okhrimenko f2a3954d6e Update slot start address in linker scripts according to default multi image policy 2020-04-05 13:52:27 +03:00
Roman Okhrimenko 57d141d005 Update pre build hex with Release version, generated by CI 2020-04-05 13:52:27 +03:00
Roman Okhrimenko 5267ec3375 Add prebuilded hex file for secure cm0p application 2020-04-05 13:52:26 +03:00
Roman Okhrimenko a17bed366a Change policy to multi image, as one supported for es100 2020-04-05 13:52:26 +03:00
Dustin Crossman e873669b04 Added policy file and removed old secure tools config file. 2020-04-05 13:52:26 +03:00
Dustin Crossman f8c1c446f1 Add nvram image for CY8CKIT_064B0S2_4343W 2020-04-05 13:52:26 +03:00
Dustin Crossman b6c4fc6d23 Add CY8CKIT_064B0S2_4343W board. 2020-04-05 13:52:26 +03:00
Jaeden Amero c447278727 cypress: psoc64: Add TF-M compatibility 
Make the CY8CKIT_064S2_4343W target TF-M compatible by addding flash and
region definitions from TF-M (at c4f37c18c4a0) and by updating the
CY8CKIT_064S2_4343W linker script to create a flash image compatible
with TF-M.

Signed-off-by: Jaeden Amero <jaeden.amero@arm.com>
 2020-04-03 15:48:58 +01:00
Devaraj Ranganna cc8cc5903a cypress: psoc64: Reserve timer channels used by TF-M 
There are two timers, Timer0 and Timer1, available on the PSoC64. Timer0
has 8 channels and Timer1 has 24 channels. TF-M regression tests make
use of Timer0 Channel 0 and Timer0 Channel 1. Therefore, reserve the
timer channels used by TF-M. This approach can be replaced once we have
a way to allocate dedicated timers for TF-M and Mbed OS.

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Vikas Katariya <vikas.katariya@arm.com>
 2020-04-03 15:48:58 +01:00
Dustin Crossman 56099951b5 Ran astyle on COMPONENT_SCL. 2020-03-26 11:50:58 -07:00
Dustin Crossman 89c70fbd9a Fix licenses in COMPONENT_SCL. 2020-03-16 09:40:34 -07:00
Dustin Crossman 539b78fae0 CYSBSYSKIT_01 targets.json and bsp update. 2020-03-10 09:52:52 -07:00
Dustin Crossman 05776d6f88 Update COMPONENT_SCL. 2020-03-09 10:07:12 -07:00
Dustin Crossman 6b6db89434 Improve documentation. 2020-03-09 10:07:12 -07:00
Dustin Crossman 0fe5efc4a4 Added checks for configuration parameters 2020-03-09 10:07:12 -07:00
Dustin Crossman e754510cce Add COMPONENT_SCL. 2020-03-09 10:07:11 -07:00
Dustin Crossman 684d6dab4c Add CYSBSYSKIT_01 bsp. 2020-03-09 10:07:11 -07:00
Martin Kojtal 98db25537a
Merge pull request #12440 from dustin-crossman/pr/reset_reason 
Implement reset_reason api for cypress targets
 2020-02-25 15:24:54 +00:00
Martin Kojtal 1629103fb1
Merge pull request #12421 from dustin-crossman/pr/cy_targets_reorganization 
Cypress Targets Reorganization
 2020-02-24 16:25:08 +00:00
midd 6baafdaf81 Update psoc6cm0p asset to version 1.1.1. This version is built with PSoC 6 Peripheral Driver Library (PDL) 1.4.1 2020-02-21 10:52:33 -08:00
Dustin Crossman 404dacc9ea Implemented reset reason api. 2020-02-21 09:48:26 -08:00
Martin Kojtal 3662759a0e
Merge pull request #12438 from hugueskamba/hk-fix-baremetal-cy9cproto 
Fix CY8CPROTO_062_4343W baremetal build
 2020-02-20 12:50:29 +00:00
Hugues Kamba 18193abdb5 Fix CY8CPROTO_062_4343W baremetal build 
Make a Mbed library with Cypress WHD files so it is automatically excluded
when building with the bare metal profile. Create another Mbed library to
group network files that use WHD so they can also be excluded fro the bare
metal profile.
 2020-02-16 13:02:36 +00:00
Dustin Crossman 563edb294d Store RTC century and RTC state information in persistent BREG register. 2020-02-12 15:05:26 -08:00
Dustin Crossman 3fdb820b26 Update psoc6hal to 1.1.1.11145. 2020-02-12 15:05:16 -08:00
Dustin Crossman a8331c28ce Update psoc6 core_lib to version 1.1.1.11109. 2020-02-12 15:05:05 -08:00
Dustin Crossman 5bd02f866e Update psoc6pdl to version 1.4.1.2240 2020-02-12 15:04:46 -08:00
Dustin Crossman 84c9303ea0 Remove CY8CMOD_062S3_4343W and merge into CY8CPROTO_062S3_4343W. 2020-02-10 12:04:59 -08:00
Dustin Crossman 0f0c79d2ed Remove CY8CMOD_062S2_43012 and merge into CY8CKIT_062S2_43012. 2020-02-10 12:03:13 -08:00
Dustin Crossman f4731715df Remove CY8CMOD_062_4343W and merge into CY8CPROTO_062_4343W. 2020-02-10 12:01:51 -08:00
midd df5ac6483b Added a multiplied by 2 in the SDIO clock divider calculation to account for internal UDB divider. 
Note: Fixes issues with intermittent WiFi firmware load failures on CY8CKIT_062_WIFI_BT, CYW943012P6EVB_01, CYW9P62S1_43012EVB_01, CYW9P62S1_43438EVB_01.
 2020-02-07 10:25:24 -08:00
midd 3dbfed058e Update psoc6cm0p asset to 1.1.0 2020-02-05 12:40:17 -08:00
Dustin Crossman b204dfd943 Fix inconsistency between mbed crc and psoc6 crc implementations. 2020-01-24 18:23:25 +00:00
YARB(Cypress) c53d2f1198 Addressed comments 2020-01-13 14:46:32 +02:00