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Update CYSBSYSKIT_01 BSP

pull/12828/head
Dustin Crossman 2020-04-13 10:49:11 -07:00
parent a79d3ce18d
commit 2148fa5ab9
16 changed files with 1319 additions and 291 deletions
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6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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@ -28,6 +28,8 @@
void init_cycfg_all(void)
{
init_cycfg_routing();
init_cycfg_pins();
init_cycfg_system();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
}

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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@ -34,6 +34,7 @@ extern "C" {
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
void init_cycfg_all(void);

49
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c Normal file
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@ -0,0 +1,49 @@
/*******************************************************************************
* File Name: cycfg_peripherals.c
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_peripherals.h"
const cy_stc_smif_config_t CYBSP_QSPI_config = {
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj = {
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
}

72
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h Normal file
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@ -0,0 +1,72 @@
/*******************************************************************************
* File Name: cycfg_peripherals.h
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PERIPHERALS_H */

355
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
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@ -26,152 +26,277 @@
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_SW1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_SW1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
const cy_stc_gpio_pin_config_t CYBSP_SW1_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_SW1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SW1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SW1_PORT_NUM,
.channel_num = CYBSP_SW1_PIN,
};
const cyhal_resource_inst_t CYBSP_SW1_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SW1_PORT_NUM,
.channel_num = CYBSP_SW1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_LED1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
const cy_stc_gpio_pin_config_t CYBSP_LED1_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_LED1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_LED1_PORT_NUM,
.channel_num = CYBSP_LED1_PIN,
};
const cyhal_resource_inst_t CYBSP_LED1_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_LED1_PORT_NUM,
.channel_num = CYBSP_LED1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_QSPI_SS0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SS0_PORT_NUM,
.channel_num = CYBSP_QSPI_SS0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_QSPI_DATA0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_QSPI_SPI_CLOCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = {
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj = {
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config);
Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SW1_obj);
cyhal_hwmgr_reserve(&CYBSP_SW1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config);
Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_LED1_obj);
cyhal_hwmgr_reserve(&CYBSP_LED1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
#endif //defined (CY_USING_HAL)
}

224
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -30,7 +30,7 @@
#include "cycfg_notices.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
@ -46,21 +46,21 @@ extern "C" {
#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_SW1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SW1_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_SW1_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_PORT_PIN P0_4
#define CYBSP_SW1_HAL_PORT_PIN P0_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_LED1_ENABLED 1U
#define CYBSP_LED1_PORT GPIO_PRT11
@ -70,45 +70,165 @@ extern "C" {
#define CYBSP_LED1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED1_HSIOM ioss_0_port_11_pin_1_HSIOM
#define CYBSP_LED1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_PORT_PIN P11_1
#define CYBSP_LED1_HAL_PORT_PIN P11_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#define CYBSP_QSPI_SS0_ENABLED 1U
#define CYBSP_QSPI_SS0_PORT GPIO_PRT11
#define CYBSP_QSPI_SS0_PORT_NUM 11U
#define CYBSP_QSPI_SS0_PIN 2U
#define CYBSP_QSPI_SS0_NUM 2U
#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_ENABLED 1U
#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA3_PORT_NUM 11U
#define CYBSP_QSPI_DATA3_PIN 3U
#define CYBSP_QSPI_DATA3_NUM 3U
#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_ENABLED 1U
#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA2_PORT_NUM 11U
#define CYBSP_QSPI_DATA2_PIN 4U
#define CYBSP_QSPI_DATA2_NUM 4U
#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_ENABLED 1U
#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA1_PORT_NUM 11U
#define CYBSP_QSPI_DATA1_PIN 5U
#define CYBSP_QSPI_DATA1_NUM 5U
#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_ENABLED 1U
#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA0_PORT_NUM 11U
#define CYBSP_QSPI_DATA0_PIN 6U
#define CYBSP_QSPI_DATA0_NUM 6U
#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U
#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U
#define CYBSP_QSPI_SPI_CLOCK_PIN 7U
#define CYBSP_QSPI_SPI_CLOCK_NUM 7U
#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
@ -118,21 +238,21 @@ extern "C" {
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
@ -142,42 +262,62 @@ extern "C" {
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SW1_obj;
extern const cyhal_resource_inst_t CYBSP_SW1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_LED1_obj;
extern const cyhal_resource_inst_t CYBSP_LED1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);

62
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -25,8 +25,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
/* The width of the command transfer. */
@ -43,8 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
@ -61,8 +59,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
@ -79,8 +76,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
/* The width of the command transfer. */
@ -97,8 +93,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
@ -115,8 +110,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
/* The width of the command transfer. */
@ -133,8 +127,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
@ -151,8 +144,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
@ -169,8 +161,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = {
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
@ -187,34 +178,33 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = {
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t *) &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -227,8 +217,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = {
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
@ -245,19 +234,18 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t *) &deviceCfg_S25FL512S_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
const cy_stc_smif_mem_config_t *const smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
const cy_stc_smif_block_config_t smifBlockConfig = {
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
.memConfig = (cy_stc_smif_mem_config_t **)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -42,7 +42,7 @@ extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_mem_config_t *const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -34,7 +34,12 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK

420
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -26,3 +26,423 @@
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = {
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = {
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = {
.feedbackDiv = 25,
.referenceDiv = 1,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while (1);
}
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
{
Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
}
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
}
__STATIC_INLINE void Cy_SysClk_ClkFastInit()
{
Cy_SysClk_ClkFastSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
{
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloEnable();
Cy_SysClk_IloHibernateOn(true);
}
__STATIC_INLINE void Cy_SysClk_ClkLfInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
}
__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
{
Cy_SysClk_ClkTimerDisable();
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
Cy_SysClk_ClkTimerSetDivider(0U);
Cy_SysClk_ClkTimerEnable();
}
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#ifdef CY_CFG_PWR_ENABLED
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) { /* PLL 1 is the first PLL. 0 is invalid. */
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) {
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
#else
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
Cy_SysClk_ClkPath2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
Cy_SysClk_ClkPath3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
Cy_SysClk_ClkPath4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
Cy_SysClk_ClkPath5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
Cy_SysClk_ClkPath6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
Cy_SysClk_ClkPath7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
Cy_SysClk_ClkPath8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
Cy_SysClk_ClkPath9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
Cy_SysClk_ClkPath10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
Cy_SysClk_ClkPath11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
Cy_SysClk_ClkPath12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
Cy_SysClk_ClkPath13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
Cy_SysClk_ClkPath14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
Cy_SysClk_Pll1Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
Cy_SysClk_Pll2Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
Cy_SysClk_Pll3Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
Cy_SysClk_Pll4Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
Cy_SysClk_Pll5Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
Cy_SysClk_Pll6Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
Cy_SysClk_Pll7Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
Cy_SysClk_Pll8Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
Cy_SysClk_Pll9Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
Cy_SysClk_Pll10Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
Cy_SysClk_Pll11Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
Cy_SysClk_Pll12Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
Cy_SysClk_Pll13Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
Cy_SysClk_ClkHf2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
Cy_SysClk_ClkHf3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
Cy_SysClk_ClkHf4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
Cy_SysClk_ClkHf5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
Cy_SysClk_ClkHf6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
Cy_SysClk_ClkHf7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
Cy_SysClk_ClkHf8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
Cy_SysClk_ClkHf9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
Cy_SysClk_ClkHf10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
Cy_SysClk_ClkHf11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
Cy_SysClk_ClkHf12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
Cy_SysClk_ClkHf13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
Cy_SysClk_ClkHf14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
}

34
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -28,12 +28,46 @@
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)
}

38
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -50,45 +50,17 @@ scb[10]
ioss[0].port[5].pin[4]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[5]
# CYBSP_DEBUG_UART_RTS
ioss[0].port[5].pin[6]
# CYBSP_DEBUG_UART_CTS
ioss[0].port[5].pin[7]
# CYBSP_DEBUG_UART_CLK_DIV
peri[0].div_16[0]
# POWER
srss[0].power[0]
# SYSTEM CLOCK
srss[0].clock[0]
# CLK_ALT_SYS_TICK
srss[0].clock[0].altsystickclk[0]
# CLK_BAK
srss[0].clock[0].bakclk[0]
# CLK_FAST
srss[0].clock[0].fastclk[0]
# CLK_HF0
srss[0].clock[0].hfclk[0]
# CLK_HF2
srss[0].clock[0].hfclk[2]
# CLK_HF4
srss[0].clock[0].hfclk[4]
# CLK_ILO
srss[0].clock[0].ilo[0]
# CLK_IMO
srss[0].clock[0].imo[0]
# CLK_LF
srss[0].clock[0].lfclk[0]
# PATH_MUX0
srss[0].clock[0].pathmux[0]
# PATH_MUX1
srss[0].clock[0].pathmux[1]
# CLK_PERI
srss[0].clock[0].periclk[0]
# CLK_PLL0
srss[0].clock[0].pll[0]
# CLK_SLOW
srss[0].clock[0].slowclk[0]
# CLK_TIMER
srss[0].clock[0].timerclk[0]
# RTC
srss[0].rtc[0]

200
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -36,8 +36,8 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Block location="ioss[0].port[11].pin[2]">
<Alias value="CYBSP_QSPI_SS0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -49,6 +49,72 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[3]">
<Alias value="CYBSP_QSPI_DATA3"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[4]">
<Alias value="CYBSP_QSPI_DATA2"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[5]">
<Alias value="CYBSP_QSPI_DATA1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[6]">
<Alias value="CYBSP_QSPI_DATA0"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[7]">
<Alias value="CYBSP_QSPI_SPI_CLOCK"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[4]"/>
<Block location="ioss[0].port[6].pin[6]">
<Alias value="CYBSP_SWDIO"/>
<Personality template="mxs40pin" version="1.1">
@ -84,6 +150,104 @@
<Block location="ioss[0].port[8].pin[7]">
<Alias value="CYBSP_CSD_SLD4"/>
</Block>
<Block location="smif[0]">
<Alias value="CYBSP_QSPI"/>
<Personality template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
<Param id="isrUnderflow" value="false"/>
<Param id="isrCmdOverflow" value="false"/>
<Param id="isrDataOverflow" value="false"/>
<Param id="rxTriggerLevel" value="0"/>
<Param id="txTriggerLevel" value="0"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
<Block location="srss[0].clock[0].altsystickclk[0]">
<Personality template="mxs40altsystick" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].bakclk[0]">
<Personality template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].fastclk[0]">
<Personality template="mxs40fastclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[0]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[2]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="2"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].hfclk[4]">
<Personality template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].ilo[0]">
<Personality template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].imo[0]">
<Personality template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].lfclk[0]">
<Personality template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="ilo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[0]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pathmux[1]">
<Personality template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[0]">
<Personality template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
<Param id="optimization" value="MinPower"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].slowclk[0]">
<Personality template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].timerclk[0]">
<Personality template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/>
</Personality>
</Block>
</BlockConfig>
<Netlist>
<Net>
@ -95,8 +259,36 @@
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
<Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
<Port name="smif[0].spi_select0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
<Port name="smif[0].spi_data3[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
<Port name="smif[0].spi_data2[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
<Port name="smif[0].spi_data1[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
<Port name="smif[0].spi_data0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
</Netlist>
</Device>

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c
View File

@ -2,7 +2,7 @@
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
@ -40,18 +40,18 @@ extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
@ -73,8 +73,7 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) {
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
@ -93,8 +92,7 @@ cy_rslt_t cybsp_init(void)
init_cycfg_all();
#endif
if (CY_RSLT_SUCCESS == result)
{
if (CY_RSLT_SUCCESS == result) {
result = cybsp_register_sysclk_pm_callback();
}

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h
View File

@ -62,11 +62,11 @@ cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */

122
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h
View File

@ -33,10 +33,6 @@
extern "C" {
#endif
#ifndef CY_CFG_SYSCLK_CLKLF_FREQ_HZ
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ (32000U)
#endif
/**
* \addtogroup group_bsp_settings BSP Settings
* \{
@ -113,50 +109,15 @@ extern "C" {
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P1_4)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P13_4)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P13_5)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P13_6)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P13_7)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P12_0)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P12_3)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P12_2)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_4)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_5)
/** Pin: UART_RTS */
#define CYBSP_DEBUG_UART_RTS (P5_6)
/** Pin: UART_CTS */
#define CYBSP_DEBUG_UART_CTS (P5_7)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
@ -180,13 +141,82 @@ extern "C" {
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SPI MOSI */
#define CYBSP_SPI_MOSI (P5_0)
/** Pin: SPI MISO */
#define CYBSP_SPI_MISO (P5_1)
/** Pin: SPI CLK */
#define CYBSP_SPI_CLK (P5_2)
/** Pin: SPI CS */
#define CYBSP_SPI_CS (P5_3)
/** Pin: FEATHER UART RX */
#define CYBSP_FEATHER_UART_RX (P6_4)
/** Pin: FEATHER UART TX */
#define CYBSP_FEATHER_UART_TX (P6_5)
/** \} group_bsp_pins_comm */
/**
* \addtogroup group_bsp_pins_therm Thermister Pins
* \{
*/
/** Pin: Thermister VDD */
#define CYBSP_THERM_VDD (P10_6)
/** Pin: Thermister output */
#define CYBSP_THERM_OUT (P10_7)
/** \} group_bsp_pins_therm */
/**
* \addtogroup group_bsp_pins_eco ECO Pins
* \{
*/
/** Pin: ECO IN */
#define CYBSP_ECO_IN (P12_6)
/** Pin: ECO IN */
#define CYBSP_ECO_OUT (P12_7)
/** \} group_bsp_pins_eco */
/**
* \addtogroup group_bsp_pins_feather Feather Header Pins
* \{
*/
/** GPIOA0 */
#define CYBSP_GPIOA0 (P10_0)
/** GPIOA1 */
#define CYBSP_GPIOA1 (P10_1)
/** GPIOA2 */
#define CYBSP_GPIOA2 (P10_2)
/** GPIOA3 */
#define CYBSP_GPIOA3 (P10_3)
/** GPIOA4 */
#define CYBSP_GPIOA4 (P10_4)
/** GPIOA5 */
#define CYBSP_GPIOA5 (P10_5)
/** GPIO5 */
#define CYBSP_GPIO5 (P8_4)
/** GPIO6 */
#define CYBSP_GPIO6 (P9_7)
/** GPIO9 */
#define CYBSP_GPIO9 (P9_4)
/** GPIO10 */
#define CYBSP_GPIO10 (P9_3)
/** GPIO11 */
#define CYBSP_GPIO11 (P9_2)
/** GPIO12 */
#define CYBSP_GPIO12 (P9_1)
/** GPIO13 */
#define CYBSP_GPIO13 (P9_0)
/** \} group_bsp_pins_feather */
/** \} group_bsp_pins */
#endif /* defined(CY_USING_HAL) */
#if defined(__cplusplus)