This is a minor optimisation to the mcr20a-rf-driver code:
Note that function parameter is pointer. The code is more readable when 'NULL' instead of using '0'.
When dealing with EEPROMs without a 16 bit adressing, the current
implementation does not work, as it writes a 16 bit address to the chip.
This may cause undefined behaviour.
This change adds a new constructor argument to enable this new eight-bit
mode. It defaults to false to not break existing code.
This constructor argument should actually never be necessary to manually
set, except when dealing with cheap devices.
This is a minor optimisation to the mcr20a-rf-driver code:
1. The function parameter is 'uint8_t *byteArray', (byteArray == NULL) instead of using (byteArray == 0). The code is more readable.
When reading a data block, the returned error codes from the I2C subsystem
are different from normal single byte operations. We have to verify that
the read-function for multiple bytes does return zero, because it
returns "readBytes != expectedLength".
Additionally, sync before trying to read from the eeprom as slow devices
may not yet be ready to return data, especially with low-priced ones
used with fast controllers.
At these locations, psa_key_attribute variables are used without
initialisation. The function getting it (psa_get_key_attributes),
is freeing attributes->domain_parameters, which can contain random
address from the stack.
Signed-off-by: Gabor Abonyi <gabor.abonyi@arm.com>
This is a special case since targets do not provide by default GPIO pin-maps.
This extension is required for FPGA GPIO tests - if some pins have limitations (e.g. fixed pull-up) we need to skip these pins while testing.
To do that we were adding a dummy pin-map with commented out pins that can't be tested because of the limitations.
This solution is redundant and the proposition is to provide a list of restricted gpio pins if required (by default weak implementation is provided with an empty list).
This mechanism will be backward compatible, so the old method with dummy gpio pinmap will also work. The switch from dummy pin-maps to pinmap_gpio_restricted_pins() will be performed in separate commits/PRs.
Substantiation for this is that the STDIO UART peripheral is used by Mbed, so it should never be tested.
Also solve the potential problem with accidenty skipped peripherals in FPGA testing. Currently, we have a one `pinmap_restricted_peripherals()` function for all interfaces (UART, I2C, SPI, etc.).
The problem can be encountered if different interfaces have the same peripheral ids (e.g. `UART_0` = 0, `SPI_0` = 0). In this case, if `UART_0` is on the restricted list, then SPI tests will be also skipped for `SPI_0`.
The good news is that usually, the peripheral ids are the base addresses of the peripheral's register set, but we can't rely on this. It is also good that `pinmap_restricted_peripherals()` at this moment is only required for STDIO UART (Nuvoton and STM).
To solve this issue we will change name of `pinmap_restricted_peripherals()` to `pinmap_uart_restricted_peripherals()`, make STDIO UART restricted by default for all targets and update FPGA test utilily functions to use `pinmap_uart_restricted_peripherals()` to skip only uart peripherals.
In the future if needed we can consider to add support to restrict peripherals of other interfaces(SPI, I2C, etc).
This far all SFDP Sector Map Table related data has been found in small
pieces inside SPIFBlockDevice. Purpose was to consolidate the data
under one SFDP structure where all the information gathered from
SFDP tables is stored.
More generic version of a function used for parsing a Sector Map Table
was taken into use to avoid duplicate code. The implementation taken
into use is the one which got split from QSPIFBlockDevice and resides
now under the SFDP module.
This far all SFDP Sector Map Table related data has been found in small
pieces inside QSPIFBlockDevice. Purpose was to consolidate the data
under one SFDP structure where all the information gathered from
SFDP tables is stored.
Parsing a Sector Map Table was made more generic so that later it can be
moved under SFDP module. Once that is done it can be shared with
SPIFBlockDevice to avoid code duplication.
Add a "used" attribute to SVCHandler_main/tfm_pendsv_do_schedule to fix ARMC6 build with
the "-flto" flag.
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Major changes:
- Dependency to FileHandle removed from base classes
- AT_CellularDevice owns the default FileHandle and shares it with AT -classes
- Hang-up -detection moved as CellularContext::configure_hup(). Cannot be configured via CellularDevice any more.
Result on NRF52840_DK + BG96:
GCC:
Total Static RAM memory (data + bss): 29360(+296) bytes
Total Flash memory (text + data): 130660(-832) bytes
ARM:
Total Static RAM memory (data + bss): 261554(+8) bytes
Total Flash memory (text + data): 127573(-1193) bytes
IAR:
Total Static RAM memory (data + bss): 25479(+296) bytes
Total Flash memory (text + data): 102418(-527) bytes
RAM increase is because now ATHandler is no longer created with new -operator but is now member of AT_CellularDevice,
so image tool is able to count it. Actually total RAM consumption has decreased due to removed variables.
Separates SFDP header retrieval and moves it as a part of the earlier
introduced SFDP file.
Purpose is to abstract away differences between SPIF and QSPIF devices
when it comes to fetching the SFDP headers from a device.
1. Fix 'spurious close' by adding close() in open(). 'spurious close' gets frequent and cannot ignore when send() changes to asynchronous. User can retry open() until 'spurious close' gets true.
2. Allow only one actively sending socket because:
(1) ESP8266 AT packets 'SEND OK'/'SEND FAIL' are not associated with socket ID. No way to tell them.
(2) In original implementation, ESP8266::send() is synchronous, which implies only one actively sending socket.
3. Register 'SEND OK'/'SEND FAIL' oobs, like others in ESP8266::ESP8266 constructor. Don't get involved in oob management with send status because ESP8266 modem possibly doesn't reply these packets on error case.
4. Now that ESP8266::send() changes to asynchronous, drop the code with _parser.recv("SEND OK")/_parser.recv("SEND FAIL"). _parser.recv("SEND OK")/_parser.recv("SEND FAIL") and 'SEND OK'/'SEND FAIL' oobs both consume 'SEND OK'/'SEND FAIL' packets and complicate flow control.
Default NS lock functions use mutex to guarantee serialization into secure world.
But this mechanism doesn't support pre-rtos and interrupt-disabled.
This commit changes these functions to weak so that platform can override them to provide another mechanism.
This approach is just what TF-M repository is adopting.
https://review.trustedfirmware.org/c/trusted-firmware-m/+/1460
SPIFReducedBlockDevice parameters come from mbed_lib.json if not provided
explicitly.
Introduced an app config file for running filesystem tests with RSPIF
block device
SPIFBlockDevice parameters come from mbed_lib.json if not provided
explicitly.
Introduced an app config file for running filesystem tests with SPIF
modules
QSPIFBlockDevice parameters come from mbed_lib.json if not provided
explicitly.
Introduced an app config file for running filesystem tests with QSPIF
modules
We are now checking if ESP8266 has confirmed receiving data over serial
port with an undocumented (but existing) "Recv x bytes" message. Next we
are explicitly waiting for an official "SEND OK".
The size stated in the struct header was 0xB0, however
the actual size(including the header) is 0xAC. Changed the
len value in the header, to avoid memory corruption.
Raised in #12171
Update Mbed OS's PSA Crypto service to work with Mbed Crypto 3.x.
- psa_asymmetric_verify() is now called psa_verify_hash().
- psa_asymmetric_sign() is now called psa_sign_hash().
Compatibilty wrappers are provided via crypto_compat.h for source-level
backwards compatibility.
* Make mbed_error use bitwise MbedCRC call rather than local
implementation.
* Remove use of POLY_32BIT_REV_ANSI from LittleFS.
* Move some MbedCRC instances closer to use - construction cost is
trivial, and visibility aids compiler optimisation.
As the `psa` library is not included in the baremetal profile, perform
a TFM system reset only if the `psa` library is included in
the build otherwise perform a normal CMSIS system reset.
* Make mbed_error use bitwise MbedCRC call rather than local
implementation.
* Remove use of POLY_32BIT_REV_ANSI from LittleFS.
* Move some MbedCRC instances closer to use - construction cost is
trivial, and visibility aids compiler optimisation.
4-byte addressing has been seen to cause failures on NORDIC
boards and with Macronix memories. Suppress the attempt to enable it
on that hardware (via vendor quirks and a target check) until either
the failure cause can be fixed or a more robust suppression mechanism
is implemented.
Use a vendor id check to only perform this enable on devices which define the
second configuration register where the fast mode enable bit lives.
Change _enable_fast_mode to use the standard status register reading and writing functions
Default to 2 status registers, but update this value if necessary
during vendor quirk handling for parts (currently only Macronix)
which have one status register and two control registers. For the
purposes of QSPIFBlockDevice, these are all considered status
(or at least "status-like") registers because they are all written
via the Write Status Register instruction.
Set the custom RDCR instruction for Macronix during quirk handling.
Update reading and writing of status registers to handle a variable
number of status registers.
Introduce a separate function for handling alterations to device interaction
which are not covered by the SFDP tables and therefore require checking against
the vendor id.
QSPIFBlockDevice::_clear_block_protection() has logic to retain the
WIP and WEL bits in status register 1, but it failed to account for
the situation where the QE bit is also in status register 1.
In _sfdp_set_quad_enabled, note the status register and bit therein
for the quad enable, so that _clear_block_protection can retain it.
This function writes a "config" register to ensure that the flash part
is in high performance mode, not low-power mode. This is required at
by at least MX25R6435F in order to operate at frequencies > 33MHz
(for reference, DISCO_L475VG_IOT01A runs the QSPI interface at 80 MHz).
The config register that this writes does not appear to be covered by
the SFDP spec (JESD216D.01) so this remains the status quo of
unconditional execution, as has been done on master since #8352.
To support online compiler build for PSA targets, some files are
auto-generated (LPC55S69_NS and ARM_MUSCA_A1_NS) by the script
from offline build system. Since these files are identical for these
V8-M targets it would be good to check them in to support online
compiler as they are COMPONENT_SPE and services related.
In folder: components/TARGET_PSA/
--TARGET_MBED_SPM
--COMPONENT_SPE
psa_setup.c
--TARGET_TFM
--COMPONENT_SPE
--inc
tfm_partition_defs.inc
tfm_partition_list.inc
tfm_service_list.inc
tfm_spm_signal_defs.h
--services
--inc
autogen_sid.h
mbed_spm_partitions.h
Signed-off-by: Vikas Katariya <Vikas.Katariya@arm.com>
* Refactor some headers to use relative path from Mbed OS root.
* Refactor some data types to compile on 64bit machines.
* Refactor some debug traces to use mbed_trace.
Arto Kinnunen
Veijo Pesonen
Stephan Brunner
Martin Kojtal
David Lin
jeromecoutant
Przemyslaw Stekiel
Gabor Abonyi
Michal Paszta
Maciej Bocianski
Mahesh Mahadevan
Pawel Zarembski
Kevin Bracey
Marcin Tomczyk
Rajkumar Kanagaraj
Kimmo Vaisanen
Andrew Chong
Anna Bridge
Hugues Kamba
Chun-Chieh Li
Tymoteusz Bloch
Ron Eldor
Jaeden Amero
Antti Kauppila
Antti Yli-Tokola
Jarkko Paso
Kyle Kearney
Matthew Macovsky
Vikas Katariya
Seppo Takalo