mirror of https://github.com/ARMmbed/mbed-os.git
				
				
				
			Merge pull request #12331 from jeromecoutant/PR_OSPI
STM32: enable QSPI test with MX25LM51245G octo SPIpull/12336/head
						commit
						44add981ff
					
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			@ -54,7 +54,7 @@
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#define QSPI_PAGE_SIZE                          256     // 256B
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#define QSPI_SECTOR_SIZE                        4096    // 4kB
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#define QSPI_SECTOR_COUNT                       2048
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#define QSPI_SECTOR_COUNT                       131072  // 512MB / QSPI_SECTOR_SIZE
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// Commands for reading
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// Only single/octal mode supported with this memory
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			@ -67,7 +67,7 @@
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// Commands for erasing
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#define QSPI_CMD_ERASE_SECTOR                   0x20    // 4kB
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//#define QSPI_CMD_ERASE_BLOCK_32   // not supported, only ersae block 64
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//#define QSPI_CMD_ERASE_BLOCK_32                       // not supported
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#define QSPI_CMD_ERASE_BLOCK_64                 0xD8    // 64kB
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#define QSPI_CMD_ERASE_CHIP                     0x60    // or 0xC7
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			@ -76,13 +76,13 @@
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#define QSPI_ERASE_BLOCK_64_MAX_TIME            2400000     // 2s
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// max frequency for basic rw operation (for fast mode)
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#define QSPI_COMMON_MAX_FREQUENCY               1000000
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#define QSPI_COMMON_MAX_FREQUENCY               66000000
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#define QSPI_STATUS_REG_SIZE                    1 //2 ??
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#define QSPI_STATUS_REG_SIZE                    1
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#define QSPI_CONFIG_REG_0_SIZE                  1
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#define QSPI_CONFIG_REG_1_SIZE                  1
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#define QSPI_CONFIG_REG_1_SIZE                  12
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#define QSPI_SECURITY_REG_SIZE                  1
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#define QSPI_MAX_REG_SIZE                       2
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#define QSPI_MAX_REG_SIZE                       12
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// status register
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#define STATUS_BIT_WIP   (1 << 0)   // write in progress bit
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			@ -91,11 +91,5 @@
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#define STATUS_BIT_BP1   (1 << 3)   //
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#define STATUS_BIT_BP2   (1 << 4)   //
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#define STATUS_BIT_BP3   (1 << 5)   //
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//#define STATUS_BIT_QE    (1 << 6)   // Not supported
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//#define STATUS_BIT_SRWD  (1 << 7)   // Not supported
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// configuration register 0
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// bit 0, 1, 2, 4, 5, 7 reserved
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#define CONFIG0_BIT_TB   (1 << 3)   // Top/Bottom area protect
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#endif // MBED_QSPI_FLASH_MX25LM51245G_H
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			@ -19,6 +19,9 @@
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        "MX25L51245G": {
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            "QSPI_FREQ": "8000000"
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        },
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        "MX25LM51245G": {
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            "QSPI_FREQ": "66000000"
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        },
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        "N25Q128A": {
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            "QSPI_FREQ": "80000000"
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        },
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			@ -12014,7 +12014,8 @@
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        "core": "Cortex-M4F",
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        "extra_labels_add": [
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            "STM32L4",
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            "STM32L4R9xI"
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            "STM32L4R9xI",
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            "MX25LM51245G"
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        ],
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        "config": {
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            "clock_source": {
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