mirror of https://github.com/ARMmbed/mbed-os.git
Update STM32H7 HAL driver to v1.11.3 (#353)
* Update STM32H5 HAL driver, fix some DMA bugs * Disable LL driver * Add scancode ignore rules * Update STM32H7 HAL driver to v1.11.3 * Fix some license issuespull/15530/head
Jamie Smith
GitHub
parent
f2a128b895
commit
cfee81c7ce
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@ -1,6 +1,8 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018, STMicroelectronics
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* All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -160,4 +162,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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}
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}
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// Blank, non-weak-override function to make sure the linker pulls in this file
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void stm32_eth_init_weak_symbol_helper()
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{}
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#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */
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@ -28,6 +28,7 @@
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#error [NOT_SUPPORTED] No network configuration found for this target.
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#endif
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#if MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI
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/*
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* Read the MBED_GREENTEA_WIFI_SECURE_PROTOCOL define from CMake and get the type of wifi
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* security in use
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@ -58,6 +59,7 @@ inline WiFiInterface *get_wifi_interface()
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return wifi_interface;
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}
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#endif
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/*
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* Get the default network interface for this board.
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@ -44,5 +44,6 @@ elseif("STM32H7_280MHZ" IN_LIST MBED_TARGET_LABELS)
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target_sources(mbed-stm32h7 INTERFACE clock_cfg/TARGET_STM32H7_280MHZ/system_clock.c)
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endif()
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# Add linker scripts
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add_subdirectory(linker_scripts)
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# Add linker scripts & system init files
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add_subdirectory(linker_scripts)
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add_subdirectory(system_init_files)
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@ -12,13 +12,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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@ -50,7 +49,7 @@ typedef enum
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{
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/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
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@ -209,13 +208,13 @@ typedef enum
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/**
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
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#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 1U /*!< FPU present */
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#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
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#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
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#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
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/**
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@ -732,8 +731,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
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* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
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* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
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* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
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* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
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* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
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* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
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* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
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* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
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*/
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@ -2288,7 +2287,6 @@ typedef struct
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#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
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#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
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#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
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#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
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/* GFXMMU virtual buffers base address */
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#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
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@ -2596,6 +2594,15 @@ typedef struct
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* @{
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*/
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/** @addtogroup Hardware_Constant_Definition
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* @{
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*/
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#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
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/**
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* @}
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*/
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/** @addtogroup Peripheral_Registers_Bits_Definition
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* @{
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*/
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@ -2645,6 +2652,9 @@ typedef struct
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#define ADC_ISR_JQOVF_Pos (10U)
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#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
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#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
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#define ADC_ISR_LDORDY_Pos (12U)
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#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
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#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
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/******************** Bit definition for ADC_IER register ********************/
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#define ADC_IER_ADRDYIE_Pos (0U)
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@ -3895,7 +3905,7 @@ typedef struct
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#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
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#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
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#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
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#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
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#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
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#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
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#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
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@ -5852,10 +5862,10 @@ typedef struct
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#define DCMI_CR_VSPOL_Pos (7U)
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#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
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#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
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#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
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#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
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#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
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#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
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#define DCMI_CR_FCRC_0 (0x00000100U)
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#define DCMI_CR_FCRC_1 (0x00000200U)
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#define DCMI_CR_EDM_0 (0x00000400U)
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#define DCMI_CR_EDM_1 (0x00000800U)
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#define DCMI_CR_CRE_Pos (12U)
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#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
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#define DCMI_CR_CRE DCMI_CR_CRE_Msk
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@ -8472,7 +8482,7 @@ typedef struct
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/******************* Bit definition for EXTI_IMR3 register *******************/
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#define EXTI_IMR3_IM_Pos (0U)
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#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
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#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
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#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
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#define EXTI_IMR3_IM64_Pos (0U)
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#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
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@ -8619,7 +8629,7 @@ typedef struct
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/******************* Bits definition for FLASH_ACR register **********************/
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#define FLASH_ACR_LATENCY_Pos (0U)
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#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
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#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
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#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
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#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
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#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
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@ -8629,6 +8639,14 @@ typedef struct
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#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
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#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
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#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
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#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
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#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
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#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
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#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
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#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
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/* Legacy FLASH Latency defines */
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#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
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#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
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#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
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@ -8637,12 +8655,6 @@ typedef struct
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#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
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#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
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#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
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#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
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#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
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#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
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#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
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#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
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/******************* Bits definition for FLASH_CR register ***********************/
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#define FLASH_CR_LOCK_Pos (0U)
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#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
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@ -9411,7 +9423,7 @@ typedef struct
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#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
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#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
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#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
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#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
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#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
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#define FMC_SDCMR_CTB2_Pos (3U)
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#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
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/******************** Bit definition for SR register ********************/
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#define JPEG_SR_IFTF_Pos (1U)
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#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
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#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
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#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
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#define JPEG_SR_IFNFF_Pos (2U)
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#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
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#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
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#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
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#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
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#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
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#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
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#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
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#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
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#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
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#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
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#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
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#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
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#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
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#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
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#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
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#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
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@ -12796,7 +12808,7 @@ typedef struct
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#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
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#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
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#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
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#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
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#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
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#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
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#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
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@ -12831,7 +12843,7 @@ typedef struct
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#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
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#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
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#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
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#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
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#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
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#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
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#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
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@ -12853,7 +12865,7 @@ typedef struct
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#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
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#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
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#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
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#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
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#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
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#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
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#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
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#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
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#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
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|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
|
|
@ -12896,7 +12908,7 @@ typedef struct
|
|||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
|
|
@ -16565,10 +16577,10 @@ typedef struct
|
|||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -17048,61 +17060,61 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
|
|
@ -17120,60 +17132,60 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
|
|
@ -17192,62 +17204,62 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
|
|
@ -17265,59 +17277,59 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
|
|
@ -17597,8 +17609,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -17875,8 +17887,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -17900,12 +17912,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18111,6 +18123,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18145,8 +18169,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18164,12 +18188,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18655,9 +18679,6 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
|
||||
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
|
||||
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
#define OCTOSPI_DCR1_CSHT_Pos (8U)
|
||||
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
|
||||
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
|
||||
|
|
@ -18671,6 +18692,11 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
|
||||
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
|
||||
|
||||
/* Legacy define */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
|
||||
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
|
||||
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
|
||||
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
|
||||
|
|
@ -19770,7 +19796,7 @@ typedef struct
|
|||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
|
@ -20168,6 +20194,9 @@ typedef struct
|
|||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
|
|
@ -20193,7 +20222,7 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20204,13 +20233,21 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
|
|
@ -20280,6 +20317,12 @@ typedef struct
|
|||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
|
|
@ -20397,7 +20440,7 @@ typedef struct
|
|||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
|
@ -22019,7 +22062,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22216,6 +22260,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22226,6 +22271,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -22529,4 +22575,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7A3xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -210,13 +209,13 @@ typedef enum
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -733,8 +732,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2289,7 +2288,6 @@ typedef struct
|
|||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
|
|
@ -2597,6 +2595,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2646,6 +2653,9 @@ typedef struct
|
|||
#define ADC_ISR_JQOVF_Pos (10U)
|
||||
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
|
||||
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
|
||||
#define ADC_ISR_LDORDY_Pos (12U)
|
||||
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
|
||||
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
|
||||
|
||||
/******************** Bit definition for ADC_IER register ********************/
|
||||
#define ADC_IER_ADRDYIE_Pos (0U)
|
||||
|
|
@ -3896,7 +3906,7 @@ typedef struct
|
|||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
|
|
@ -5853,10 +5863,10 @@ typedef struct
|
|||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
|
|
@ -8473,7 +8483,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8620,7 +8630,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8630,6 +8640,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8638,12 +8656,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9412,7 +9424,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -11302,7 +11314,7 @@ typedef struct
|
|||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
|
@ -12752,7 +12764,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
|
|
@ -12786,7 +12798,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
|
|
@ -12808,7 +12820,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
|
|
@ -12843,7 +12855,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
|
|
@ -12865,7 +12877,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
|
|
@ -12888,7 +12900,7 @@ typedef struct
|
|||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
|
|
@ -12908,7 +12920,7 @@ typedef struct
|
|||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
|
|
@ -16577,10 +16589,10 @@ typedef struct
|
|||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -17060,61 +17072,61 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
|
|
@ -17132,60 +17144,60 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
|
|
@ -17204,62 +17216,62 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
|
|
@ -17277,59 +17289,59 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
|
|
@ -17609,8 +17621,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -17887,8 +17899,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -17912,12 +17924,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18123,6 +18135,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18157,8 +18181,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18176,12 +18200,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18667,9 +18691,6 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
|
||||
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
|
||||
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
#define OCTOSPI_DCR1_CSHT_Pos (8U)
|
||||
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
|
||||
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
|
||||
|
|
@ -18683,6 +18704,11 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
|
||||
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
|
||||
|
||||
/* Legacy define */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
|
||||
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
|
||||
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
|
||||
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
|
||||
|
|
@ -19782,7 +19808,7 @@ typedef struct
|
|||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
|
@ -20180,6 +20206,9 @@ typedef struct
|
|||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
|
|
@ -20205,7 +20234,7 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20216,13 +20245,21 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
|
|
@ -20292,6 +20329,12 @@ typedef struct
|
|||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
|
|
@ -20409,7 +20452,7 @@ typedef struct
|
|||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
|
@ -22031,7 +22074,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22228,6 +22272,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22238,6 +22283,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -22541,4 +22587,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7A3xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -212,13 +211,13 @@ typedef enum
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -735,8 +734,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2408,7 +2407,6 @@ typedef struct
|
|||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
|
|
@ -2731,6 +2729,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2780,6 +2787,9 @@ typedef struct
|
|||
#define ADC_ISR_JQOVF_Pos (10U)
|
||||
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
|
||||
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
|
||||
#define ADC_ISR_LDORDY_Pos (12U)
|
||||
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
|
||||
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
|
||||
|
||||
/******************** Bit definition for ADC_IER register ********************/
|
||||
#define ADC_IER_ADRDYIE_Pos (0U)
|
||||
|
|
@ -4030,7 +4040,7 @@ typedef struct
|
|||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
|
|
@ -5747,7 +5757,7 @@ typedef struct
|
|||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
|
|
@ -5798,7 +5808,7 @@ typedef struct
|
|||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
|
|
@ -6106,10 +6116,10 @@ typedef struct
|
|||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
|
|
@ -8726,7 +8736,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8872,7 +8882,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8882,6 +8892,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8890,12 +8908,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9658,7 +9670,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -11624,7 +11636,7 @@ typedef struct
|
|||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
|
@ -13184,7 +13196,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
|
|
@ -13218,7 +13230,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
|
|
@ -13240,7 +13252,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
|
|
@ -13275,7 +13287,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
|
|
@ -13297,7 +13309,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
|
|
@ -13320,7 +13332,7 @@ typedef struct
|
|||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
|
|
@ -13340,7 +13352,7 @@ typedef struct
|
|||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
|
|
@ -17045,10 +17057,10 @@ typedef struct
|
|||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -17528,61 +17540,61 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
|
|
@ -17600,60 +17612,60 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
|
|
@ -17672,62 +17684,62 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
|
|
@ -17745,59 +17757,59 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
|
|
@ -18077,8 +18089,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18355,8 +18367,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18380,12 +18392,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18591,6 +18603,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18625,8 +18649,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18644,12 +18668,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19135,9 +19159,6 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
|
||||
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
|
||||
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
#define OCTOSPI_DCR1_CSHT_Pos (8U)
|
||||
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
|
||||
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
|
||||
|
|
@ -19151,6 +19172,11 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
|
||||
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
|
||||
|
||||
/* Legacy define */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
|
||||
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
|
||||
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
|
||||
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
|
||||
|
|
@ -20250,7 +20276,7 @@ typedef struct
|
|||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
|
@ -20648,6 +20674,9 @@ typedef struct
|
|||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
|
|
@ -20673,7 +20702,7 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20684,13 +20713,21 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
|
|
@ -20760,6 +20797,12 @@ typedef struct
|
|||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
|
|
@ -20877,7 +20920,7 @@ typedef struct
|
|||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
|
@ -22503,7 +22546,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22700,6 +22744,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22710,6 +22755,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23013,4 +23059,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B0xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -213,13 +212,13 @@ typedef enum
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -736,8 +735,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2409,7 +2408,6 @@ typedef struct
|
|||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
|
|
@ -2732,6 +2730,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2781,6 +2788,9 @@ typedef struct
|
|||
#define ADC_ISR_JQOVF_Pos (10U)
|
||||
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
|
||||
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
|
||||
#define ADC_ISR_LDORDY_Pos (12U)
|
||||
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
|
||||
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
|
||||
|
||||
/******************** Bit definition for ADC_IER register ********************/
|
||||
#define ADC_IER_ADRDYIE_Pos (0U)
|
||||
|
|
@ -4031,7 +4041,7 @@ typedef struct
|
|||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
|
|
@ -5748,7 +5758,7 @@ typedef struct
|
|||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
|
|
@ -5799,7 +5809,7 @@ typedef struct
|
|||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
|
|
@ -6107,10 +6117,10 @@ typedef struct
|
|||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
|
|
@ -8727,7 +8737,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8873,7 +8883,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8883,6 +8893,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8891,12 +8909,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9659,7 +9671,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -11625,7 +11637,7 @@ typedef struct
|
|||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
|
@ -13196,7 +13208,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
|
|
@ -13230,7 +13242,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
|
|
@ -13252,7 +13264,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
|
|
@ -13287,7 +13299,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
|
|
@ -13309,7 +13321,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
|
|
@ -13332,7 +13344,7 @@ typedef struct
|
|||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
|
|
@ -13352,7 +13364,7 @@ typedef struct
|
|||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
|
|
@ -17057,10 +17069,10 @@ typedef struct
|
|||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -17540,61 +17552,61 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
|
|
@ -17612,60 +17624,60 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
|
|
@ -17684,62 +17696,62 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
|
|
@ -17757,59 +17769,59 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
|
|
@ -18089,8 +18101,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18367,8 +18379,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18392,12 +18404,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18603,6 +18615,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18637,8 +18661,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18656,12 +18680,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19147,9 +19171,6 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
|
||||
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
|
||||
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
#define OCTOSPI_DCR1_CSHT_Pos (8U)
|
||||
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
|
||||
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
|
||||
|
|
@ -19163,6 +19184,11 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
|
||||
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
|
||||
|
||||
/* Legacy define */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
|
||||
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
|
||||
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
|
||||
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
|
||||
|
|
@ -20262,7 +20288,7 @@ typedef struct
|
|||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
|
@ -20660,6 +20686,9 @@ typedef struct
|
|||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
|
|
@ -20685,7 +20714,7 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20696,13 +20725,21 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
|
|
@ -20772,6 +20809,12 @@ typedef struct
|
|||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
|
|
@ -20889,7 +20932,7 @@ typedef struct
|
|||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
|
@ -22515,7 +22558,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22712,6 +22756,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22722,6 +22767,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23025,4 +23071,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B0xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -212,13 +211,13 @@ typedef enum
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -735,8 +734,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2408,7 +2407,6 @@ typedef struct
|
|||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
|
|
@ -2731,6 +2729,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2780,6 +2787,9 @@ typedef struct
|
|||
#define ADC_ISR_JQOVF_Pos (10U)
|
||||
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
|
||||
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
|
||||
#define ADC_ISR_LDORDY_Pos (12U)
|
||||
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
|
||||
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
|
||||
|
||||
/******************** Bit definition for ADC_IER register ********************/
|
||||
#define ADC_IER_ADRDYIE_Pos (0U)
|
||||
|
|
@ -4030,7 +4040,7 @@ typedef struct
|
|||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
|
|
@ -5747,7 +5757,7 @@ typedef struct
|
|||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
|
|
@ -5798,7 +5808,7 @@ typedef struct
|
|||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
|
|
@ -6106,10 +6116,10 @@ typedef struct
|
|||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
|
|
@ -8726,7 +8736,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8873,7 +8883,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8883,6 +8893,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8891,12 +8909,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9665,7 +9677,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -11631,7 +11643,7 @@ typedef struct
|
|||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
|
@ -13191,7 +13203,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
|
|
@ -13225,7 +13237,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
|
|
@ -13247,7 +13259,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
|
|
@ -13282,7 +13294,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
|
|
@ -13304,7 +13316,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
|
|
@ -13327,7 +13339,7 @@ typedef struct
|
|||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
|
|
@ -13347,7 +13359,7 @@ typedef struct
|
|||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
|
|
@ -17052,10 +17064,10 @@ typedef struct
|
|||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -17535,61 +17547,61 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
|
|
@ -17607,60 +17619,60 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
|
|
@ -17679,62 +17691,62 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
|
|
@ -17752,59 +17764,59 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
|
|
@ -18084,8 +18096,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18362,8 +18374,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18387,12 +18399,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18598,6 +18610,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18632,8 +18656,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18651,12 +18675,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19142,9 +19166,6 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
|
||||
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
|
||||
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
#define OCTOSPI_DCR1_CSHT_Pos (8U)
|
||||
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
|
||||
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
|
||||
|
|
@ -19158,6 +19179,11 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
|
||||
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
|
||||
|
||||
/* Legacy define */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
|
||||
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
|
||||
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
|
||||
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
|
||||
|
|
@ -20257,7 +20283,7 @@ typedef struct
|
|||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
|
@ -20655,6 +20681,9 @@ typedef struct
|
|||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
|
|
@ -20680,7 +20709,7 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20691,13 +20720,21 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
|
|
@ -20767,6 +20804,12 @@ typedef struct
|
|||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
|
|
@ -20884,7 +20927,7 @@ typedef struct
|
|||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
|
@ -22510,7 +22553,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22707,6 +22751,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22717,6 +22762,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23020,4 +23066,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B3xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -12,13 +12,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -50,7 +49,7 @@ typedef enum
|
|||
{
|
||||
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
|
||||
|
|
@ -213,13 +212,13 @@ typedef enum
|
|||
/**
|
||||
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
|
||||
*/
|
||||
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
|
||||
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
|
||||
#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
|
||||
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1U /*!< FPU present */
|
||||
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
|
||||
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
|
||||
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
|
||||
|
||||
/**
|
||||
|
|
@ -736,8 +735,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
|
|||
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
|
||||
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
|
||||
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
|
||||
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
|
||||
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
|
||||
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
|
||||
*/
|
||||
|
||||
|
|
@ -2409,7 +2408,6 @@ typedef struct
|
|||
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
|
||||
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
|
||||
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
|
||||
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
|
||||
|
||||
/* GFXMMU virtual buffers base address */
|
||||
#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
|
||||
|
|
@ -2732,6 +2730,15 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2781,6 +2788,9 @@ typedef struct
|
|||
#define ADC_ISR_JQOVF_Pos (10U)
|
||||
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
|
||||
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
|
||||
#define ADC_ISR_LDORDY_Pos (12U)
|
||||
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
|
||||
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
|
||||
|
||||
/******************** Bit definition for ADC_IER register ********************/
|
||||
#define ADC_IER_ADRDYIE_Pos (0U)
|
||||
|
|
@ -4031,7 +4041,7 @@ typedef struct
|
|||
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
|
||||
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
|
||||
|
||||
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */
|
||||
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
|
||||
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
|
||||
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
|
||||
|
|
@ -5748,7 +5758,7 @@ typedef struct
|
|||
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
|
||||
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
|
||||
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
|
||||
|
|
@ -5799,7 +5809,7 @@ typedef struct
|
|||
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
|
||||
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
|
||||
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
|
||||
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
|
||||
#define CRYP_CR_ALGOMODE_3 (0x00080000U)
|
||||
#define CRYP_CR_NPBLB_Pos (20U)
|
||||
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
|
||||
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
|
||||
|
|
@ -6107,10 +6117,10 @@ typedef struct
|
|||
#define DCMI_CR_VSPOL_Pos (7U)
|
||||
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
|
||||
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
|
||||
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
|
||||
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
|
||||
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
|
||||
#define DCMI_CR_FCRC_0 (0x00000100U)
|
||||
#define DCMI_CR_FCRC_1 (0x00000200U)
|
||||
#define DCMI_CR_EDM_0 (0x00000400U)
|
||||
#define DCMI_CR_EDM_1 (0x00000800U)
|
||||
#define DCMI_CR_CRE_Pos (12U)
|
||||
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
|
||||
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
|
||||
|
|
@ -8727,7 +8737,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for EXTI_IMR3 register *******************/
|
||||
#define EXTI_IMR3_IM_Pos (0U)
|
||||
#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
|
||||
#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */
|
||||
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
|
||||
#define EXTI_IMR3_IM64_Pos (0U)
|
||||
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -8874,7 +8884,7 @@ typedef struct
|
|||
|
||||
/******************* Bits definition for FLASH_ACR register **********************/
|
||||
#define FLASH_ACR_LATENCY_Pos (0U)
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
|
||||
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
|
||||
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
|
||||
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
|
||||
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
|
||||
|
|
@ -8884,6 +8894,14 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
|
||||
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
|
||||
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
|
||||
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/* Legacy FLASH Latency defines */
|
||||
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
|
||||
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
|
||||
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
|
||||
|
|
@ -8892,12 +8910,6 @@ typedef struct
|
|||
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
|
||||
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
|
||||
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
|
||||
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
|
||||
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
|
||||
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
|
||||
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
|
||||
|
||||
/******************* Bits definition for FLASH_CR register ***********************/
|
||||
#define FLASH_CR_LOCK_Pos (0U)
|
||||
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9666,7 +9678,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -11632,7 +11644,7 @@ typedef struct
|
|||
/******************** Bit definition for SR register ********************/
|
||||
#define JPEG_SR_IFTF_Pos (1U)
|
||||
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
|
||||
#define JPEG_SR_IFNFF_Pos (2U)
|
||||
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
|
||||
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
|
||||
|
|
@ -13203,7 +13215,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
|
||||
#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
|
||||
#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
|
||||
#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
|
||||
|
|
@ -13237,7 +13249,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
|
||||
|
|
@ -13259,7 +13271,7 @@ typedef struct
|
|||
#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
|
||||
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
|
||||
#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
|
||||
|
|
@ -13294,7 +13306,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
|
||||
|
|
@ -13316,7 +13328,7 @@ typedef struct
|
|||
#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
|
||||
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
|
||||
#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
|
||||
|
|
@ -13339,7 +13351,7 @@ typedef struct
|
|||
#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
|
||||
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
|
||||
#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
|
||||
|
|
@ -13359,7 +13371,7 @@ typedef struct
|
|||
#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
|
||||
#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
|
||||
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
|
||||
#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
|
||||
|
|
@ -17064,10 +17076,10 @@ typedef struct
|
|||
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
|
||||
#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */
|
||||
|
||||
/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
|
||||
#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -17547,61 +17559,61 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI0 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI1 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */
|
||||
/**
|
||||
* @brief EXTI2 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI3 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */
|
||||
#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
||||
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
|
||||
|
|
@ -17619,60 +17631,60 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI4 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */
|
||||
/**
|
||||
* @brief EXTI5 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */
|
||||
/**
|
||||
* @brief EXTI6 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI7 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */
|
||||
#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
||||
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
|
||||
|
|
@ -17691,62 +17703,62 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI8 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI9 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI10 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */
|
||||
|
||||
/**
|
||||
* @brief EXTI11 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */
|
||||
#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */
|
||||
|
||||
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
||||
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
|
||||
|
|
@ -17764,59 +17776,59 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI12 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */
|
||||
/**
|
||||
* @brief EXTI13 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */
|
||||
/**
|
||||
* @brief EXTI14 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */
|
||||
/**
|
||||
* @brief EXTI15 configuration
|
||||
*/
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */
|
||||
#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFGR register ******************/
|
||||
#define SYSCFG_CFGR_PVDL_Pos (2U)
|
||||
|
|
@ -18096,8 +18108,8 @@ typedef struct
|
|||
#define TIM_CR2_OIS5_Pos (16U)
|
||||
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
|
||||
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
#define TIM_CR2_OIS6_Pos (17U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
|
||||
#define TIM_CR2_OIS6_Pos (18U)
|
||||
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
|
||||
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
|
||||
|
||||
#define TIM_CR2_MMS2_Pos (20U)
|
||||
|
|
@ -18374,8 +18386,8 @@ typedef struct
|
|||
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC3M_Pos (4U)
|
||||
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
|
||||
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18399,12 +18411,12 @@ typedef struct
|
|||
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR2_OC4M_Pos (12U)
|
||||
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR2_OC4CE_Pos (15U)
|
||||
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -18610,6 +18622,18 @@ typedef struct
|
|||
#define TIM_BDTR_BK2P_Pos (25U)
|
||||
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
|
||||
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
|
||||
#define TIM_BDTR_BKDSRM_Pos (26U)
|
||||
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
|
||||
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
|
||||
#define TIM_BDTR_BK2DSRM_Pos (27U)
|
||||
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
|
||||
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
|
||||
#define TIM_BDTR_BKBID_Pos (28U)
|
||||
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
|
||||
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
|
||||
#define TIM_BDTR_BK2BID_Pos (29U)
|
||||
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
|
||||
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
|
||||
|
||||
/******************* Bit definition for TIM_DCR register ********************/
|
||||
#define TIM_DCR_DBA_Pos (0U)
|
||||
|
|
@ -18644,8 +18668,8 @@ typedef struct
|
|||
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC5M_Pos (4U)
|
||||
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
|
||||
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
|
||||
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
|
||||
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
|
||||
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -18663,12 +18687,12 @@ typedef struct
|
|||
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
|
||||
|
||||
#define TIM_CCMR3_OC6M_Pos (12U)
|
||||
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
|
||||
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
|
||||
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
|
||||
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
|
||||
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
|
||||
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
|
||||
|
||||
#define TIM_CCMR3_OC6CE_Pos (15U)
|
||||
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -19154,9 +19178,6 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
|
||||
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
|
||||
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
#define OCTOSPI_DCR1_CSHT_Pos (8U)
|
||||
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
|
||||
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
|
||||
|
|
@ -19170,6 +19191,11 @@ typedef struct
|
|||
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
|
||||
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
|
||||
|
||||
/* Legacy define */
|
||||
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
|
||||
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
|
||||
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
|
||||
|
||||
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
|
||||
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
|
||||
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
|
||||
|
|
@ -20269,7 +20295,7 @@ typedef struct
|
|||
#define SWPMI_RFL_RFL_Pos (0U)
|
||||
#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
|
||||
#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
|
||||
#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
|
||||
|
||||
/******************* Bit definition for SWPMI_TDR register ********************/
|
||||
#define SWPMI_TDR_TD_Pos (0U)
|
||||
|
|
@ -20667,6 +20693,9 @@ typedef struct
|
|||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
|
||||
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
|
|
@ -20692,7 +20721,7 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_DAD_Pos (4U)
|
||||
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
|
||||
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -20703,13 +20732,21 @@ typedef struct
|
|||
|
||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
|
||||
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
|
||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
|
||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
|
||||
#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
|
||||
|
||||
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
|
|
@ -20779,6 +20816,12 @@ typedef struct
|
|||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
|
|
@ -20896,7 +20939,7 @@ typedef struct
|
|||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
|
@ -22522,7 +22565,8 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12))
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
||||
|
|
@ -22719,6 +22763,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
|
|
@ -22729,6 +22774,7 @@ typedef struct
|
|||
((INSTANCE) == TIM4) || \
|
||||
((INSTANCE) == TIM5) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****************** TIM Instances : supporting OCxREF clear *******************/
|
||||
|
|
@ -23032,4 +23078,3 @@ typedef struct
|
|||
|
||||
#endif /* STM32H7B3xxQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -16,13 +16,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -59,7 +58,7 @@
|
|||
*/
|
||||
|
||||
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
|
||||
!defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
|
||||
!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \
|
||||
!defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx)
|
||||
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
|
||||
|
|
@ -67,10 +66,13 @@
|
|||
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
|
||||
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
|
||||
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
|
||||
/* #define STM32H747xG */ /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */
|
||||
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
|
||||
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
|
||||
/* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */
|
||||
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
|
||||
/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
|
||||
/* #define STM32H7B0xx */ /*!< STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx Devices */
|
||||
/* #define STM32H7B0xxQ */ /*!< STM32H7B0ABIxQ, STM32H7B0IBKxQ Devices */
|
||||
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
|
||||
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
|
||||
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
|
||||
|
|
@ -101,11 +103,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.10.0
|
||||
* @brief CMSIS Device version number V1.10.4
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
@ -116,6 +118,12 @@
|
|||
* @}
|
||||
*/
|
||||
|
||||
// MBED: The CMake scripts always define __FPU_PRESENT, but the MCU CMSIS headers below also define it.
|
||||
// So, undef it here to prevent multiple definition warning.
|
||||
#ifdef __FPU_PRESENT
|
||||
#undef __FPU_PRESENT
|
||||
#endif
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -130,10 +138,14 @@
|
|||
#include "stm32h742xx.h"
|
||||
#elif defined(STM32H745xx)
|
||||
#include "stm32h745xx.h"
|
||||
#elif defined(STM32H745xG)
|
||||
#include "stm32h745xg.h"
|
||||
#elif defined(STM32H755xx)
|
||||
#include "stm32h755xx.h"
|
||||
#elif defined(STM32H747xx)
|
||||
#include "stm32h747xx.h"
|
||||
#elif defined(STM32H747xG)
|
||||
#include "stm32h747xg.h"
|
||||
#elif defined(STM32H757xx)
|
||||
#include "stm32h757xx.h"
|
||||
#elif defined(STM32H7B0xx)
|
||||
|
|
@ -214,6 +226,60 @@ typedef enum
|
|||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
/* Use of CMSIS compiler intrinsics for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -240,4 +306,3 @@ typedef enum
|
|||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -102,4 +101,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -26,8 +26,11 @@ target_sources(mbed-stm32h7cube-fw
|
|||
STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c
|
||||
|
||||
# Temporary: using legacy Ethernet driver for now
|
||||
STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth.c
|
||||
STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex.c
|
||||
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c
|
||||
|
|
@ -124,8 +127,6 @@ target_sources(mbed-stm32h7cube-fw
|
|||
STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c
|
||||
STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c
|
||||
system_stm32h7xx_dualcore_boot_cm4_cm7.c
|
||||
system_stm32h7xx_singlecore.c
|
||||
)
|
||||
|
||||
target_include_directories(mbed-stm32h7cube-fw
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
Copyright 2017 STMicroelectronics.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,556 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_eth_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief ETH HAL Extended module driver.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
|
||||
|
||||
#if defined(ETH)
|
||||
|
||||
/** @defgroup ETHEx ETHEx
|
||||
* @brief ETH HAL Extended module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define ETH_MACL4CR_MASK (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
|
||||
ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
|
||||
ETH_MACL3L4CR_L4DPIM)
|
||||
|
||||
#define ETH_MACL3CR_MASK (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
|
||||
ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
|
||||
ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
|
||||
ETH_MACL3L4CR_L3HDBM)
|
||||
|
||||
#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
|
||||
ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
|
||||
ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
|
||||
ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
|
||||
ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
|
||||
ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
|
||||
|
||||
#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
|
||||
ETH_MACVIR_VLP | ETH_MACVIR_VLC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure ARP offload module
|
||||
(+) Configure L3 and L4 filters
|
||||
(+) Configure Extended VLAN features
|
||||
(+) Configure Energy Efficient Ethernet module
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables ARP Offload.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables ARP Offload.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the ARP Match IP address
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param IpAddress: IP Address to be matched for incoming ARP requests
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
|
||||
{
|
||||
WRITE_REG(heth->Instance->MACARPAR, IpAddress);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the L4 Filter, this function allow to:
|
||||
* set the layer 4 protocol to be matched (TCP or UDP)
|
||||
* enable/disable L4 source/destination port perfect/inverse match.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param Filter: L4 filter to configured, this parameter must be one of the following
|
||||
* ETH_L4_FILTER_0
|
||||
* ETH_L4_FILTER_1
|
||||
* @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
|
||||
* that contains L4 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef const *pL4FilterConfig)
|
||||
{
|
||||
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
|
||||
|
||||
if(pL4FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write configuration to (MACL3L4C0R + filter )register */
|
||||
MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
|
||||
configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
|
||||
|
||||
/* Write configuration to (MACL4A0R + filter )register */
|
||||
MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
|
||||
(pL4FilterConfig->DestinationPort << 16)));
|
||||
|
||||
/* Enable L4 filter */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the L4 Filter, this function allow to:
|
||||
* set the layer 4 protocol to be matched (TCP or UDP)
|
||||
* enable/disable L4 source/destination port perfect/inverse match.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param Filter: L4 filter to configured, this parameter must be one of the following
|
||||
* ETH_L4_FILTER_0
|
||||
* ETH_L4_FILTER_1
|
||||
* @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
|
||||
* that contains L4 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef const *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
{
|
||||
if(pL4FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get configuration to (MACL3L4C0R + filter )register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
|
||||
/* Get configuration to (MACL3L4C0R + filter )register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the L3 Filter, this function allow to:
|
||||
* set the layer 3 protocol to be matched (IPv4 or IPv6)
|
||||
* enable/disable L3 source/destination port perfect/inverse match.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param Filter: L3 filter to configured, this parameter must be one of the following
|
||||
* ETH_L3_FILTER_0
|
||||
* ETH_L3_FILTER_1
|
||||
* @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
|
||||
* that contains L3 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef const *pL3FilterConfig)
|
||||
{
|
||||
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
|
||||
|
||||
if(pL3FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write configuration to (MACL3L4C0R + filter )register */
|
||||
MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
|
||||
/* Set the IPv4 destination address match */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the L3 Filter, this function allow to:
|
||||
* set the layer 3 protocol to be matched (IPv4 or IPv6)
|
||||
* enable/disable L3 source/destination port perfect/inverse match.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param Filter: L3 filter to configured, this parameter must be one of the following
|
||||
* ETH_L3_FILTER_0
|
||||
* ETH_L3_FILTER_1
|
||||
* @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
|
||||
* that will contain the L3 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef const *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
{
|
||||
if(pL3FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
|
||||
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
|
||||
pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
|
||||
pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
|
||||
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
|
||||
|
||||
if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
|
||||
}
|
||||
else
|
||||
{
|
||||
pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
|
||||
pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables L3 and L4 filtering process.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
/* Enable L3/L4 filter */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables L3 and L4 filtering process.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
/* Disable L3/L4 filter */
|
||||
CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the VLAN Configuration for Receive Packets.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
|
||||
* that will contain the VLAN filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef const *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if(pVlanConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
|
||||
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
|
||||
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
|
||||
pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the VLAN Configuration for Receive Packets.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
|
||||
* that contains VLAN filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if(pVlanConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write config to MACVTR */
|
||||
MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
|
||||
pVlanConfig->StripInnerVLANTag |
|
||||
((uint32_t)pVlanConfig->InnerVLANTag << 27) |
|
||||
((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
|
||||
((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
|
||||
((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
|
||||
pVlanConfig->StripVLANTag |
|
||||
pVlanConfig->VLANTypeCheck |
|
||||
((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the VLAN Hash Table
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param VLANHashTable: VLAN hash table 16 bit value
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the VLAN Configuration for Transmit Packets.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param VLANTag: Selects the vlan tag, this parameter must be one of the following
|
||||
* ETH_OUTER_TX_VLANTAG
|
||||
* ETH_INNER_TX_VLANTAG
|
||||
* @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
|
||||
* that will contain the Tx VLAN filter configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef const *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if (pVlanConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
|
||||
}
|
||||
else
|
||||
{
|
||||
pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
|
||||
}
|
||||
|
||||
return HAL_OK;;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the VLAN Configuration for Transmit Packets.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param VLANTag: Selects the vlan tag, this parameter must be one of the following
|
||||
* ETH_OUTER_TX_VLANTAG
|
||||
* ETH_INNER_TX_VLANTAG
|
||||
* @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
|
||||
* that contains Tx VLAN filter configuration.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef const *pVlanConfig)
|
||||
{
|
||||
if(VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
|
||||
((uint32_t)pVlanConfig->SVLANType << 19) |
|
||||
pVlanConfig->VLANTagControl));
|
||||
/* Enable Double VLAN processing */
|
||||
SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
|
||||
((uint32_t)pVlanConfig->SVLANType << 19) |
|
||||
pVlanConfig->VLANTagControl));
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the VLAN Tag Identifier for Transmit Packets.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param VLANTag: Selects the vlan tag, this parameter must be one of the following
|
||||
* ETH_OUTER_TX_VLANTAG
|
||||
* ETH_INNER_TX_VLANTAG
|
||||
* @param VLANIdentifier: VLAN Identifier 16 bit value
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
|
||||
{
|
||||
if(VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the VLAN Tag Filtering process.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
/* Enable VLAN processing */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the VLAN Tag Filtering process.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
/* Disable VLAN processing */
|
||||
CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters the Low Power Idle (LPI) mode
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param TxAutomate: Enable/Disable automate enter/exit LPI mode.
|
||||
* @param TxClockStop: Enable/Disable Tx clock stop in LPI mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
|
||||
{
|
||||
/* Enable LPI Interrupts */
|
||||
__HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
|
||||
|
||||
/* Write to LPI Control register: Enter low power mode */
|
||||
MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
|
||||
((uint32_t)TxClockStop << 21) |
|
||||
ETH_MACLCSR_LPIEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits the Low Power Idle (LPI) mode.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
/* Clear the LPI Config and exit low power mode */
|
||||
CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
|
||||
|
||||
/* Enable LPI Interrupts */
|
||||
__HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the ETH MAC LPI event
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval ETH MAC WakeUp event
|
||||
*/
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef const *heth)
|
||||
{
|
||||
return heth->MACLPIEvent;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* ETH */
|
||||
|
||||
#endif /* HAL_ETH_LEGACY_MODULE_ENABLED*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_eth_ex_legacy.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ETH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_ETH_EX_LEGACY_H
|
||||
#define STM32H7xx_HAL_ETH_EX_LEGACY_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(ETH)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ETHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH RX VLAN structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
|
||||
|
||||
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
|
||||
|
||||
FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
|
||||
|
||||
FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
|
||||
|
||||
FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
|
||||
|
||||
FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
|
||||
|
||||
uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
|
||||
|
||||
uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
|
||||
|
||||
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
|
||||
}ETH_RxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH TX VLAN structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
|
||||
|
||||
FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
|
||||
|
||||
uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
|
||||
}ETH_TxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH L3 filter structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
|
||||
This parameter can be a value of @ref ETHEx_L3_Protocol */
|
||||
|
||||
uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Source_Match */
|
||||
|
||||
uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Destination_Match */
|
||||
|
||||
uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
|
||||
This parameter can be a value from 0x0 to 0xFFFFFFFF */
|
||||
|
||||
uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
|
||||
This parameter can be a value from 0 to 0xFFFFFFFF */
|
||||
|
||||
uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
|
||||
This parameter must be a table of 4 words (4* 32 bits) */
|
||||
}ETH_L3FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ETH L4 filter structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
|
||||
This parameter can be a value of @ref ETHEx_L4_Protocol */
|
||||
|
||||
uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Source_Match */
|
||||
|
||||
uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Destination_Match */
|
||||
|
||||
uint32_t SourcePort; /*!< Sets the L4 filter source port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
|
||||
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
}ETH_L4FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
|
||||
* @{
|
||||
*/
|
||||
#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
|
||||
#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
|
||||
#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
|
||||
#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_FILTER_0 ((uint32_t)0x00000000)
|
||||
#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_FILTER_0 ((uint32_t)0x00000000)
|
||||
#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
|
||||
#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
|
||||
#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
|
||||
#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
|
||||
#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
|
||||
#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
|
||||
#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
|
||||
#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
|
||||
#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
|
||||
#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
|
||||
#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
|
||||
#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
|
||||
#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
|
||||
#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
|
||||
* @{
|
||||
*/
|
||||
#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
|
||||
#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
|
||||
#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
|
||||
#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
|
||||
#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ETHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ETHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* MAC ARP Offloading APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
|
||||
|
||||
/* MAC L3 L4 Filtering APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
|
||||
/* MAC VLAN Processing APIs ************************************************/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
|
||||
|
||||
/* Energy Efficient Ethernet APIs *********************************************/
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
|
||||
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* ETH */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_ETH_EX_LEGACY_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,6 +5,17 @@
|
|||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -19,17 +30,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -47,11 +47,11 @@
|
|||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief STM32H7xx HAL Driver version number V1.10.0
|
||||
* @brief STM32H7xx HAL Driver version number
|
||||
*/
|
||||
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB1 (0x0AUL) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
|
||||
|
|
@ -78,11 +78,11 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
|||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Private_Functions HAL Private Functions
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Group1 Initialization and de-initialization Functions
|
||||
/** @addtogroup HAL_Group1
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
|
|
@ -252,7 +252,7 @@ __weak void HAL_MspDeInit(void)
|
|||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The the SysTick interrupt must have higher priority (numerically lower)
|
||||
* the SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
|
|
@ -292,7 +292,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Group2 HAL Control functions
|
||||
/** @addtogroup HAL_Group2
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
|
|
@ -383,7 +383,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
|||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
* @retval Tick frequency.
|
||||
* Value of @ref HAL_TickFreqTypeDef.
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
|
|
@ -421,7 +422,7 @@ __weak void HAL_Delay(uint32_t Delay)
|
|||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
|
|
@ -437,7 +438,7 @@ __weak void HAL_SuspendTick(void)
|
|||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
|
|
@ -887,9 +888,6 @@ void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)
|
|||
|
||||
MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
|
||||
|
||||
#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
|
||||
|
|
@ -905,16 +903,13 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)
|
|||
|
||||
MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGSleepMode(void)
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
|
||||
}
|
||||
|
|
@ -923,7 +918,7 @@ void HAL_EnableDBGSleepMode(void)
|
|||
* @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGSleepMode(void)
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
|
||||
}
|
||||
|
|
@ -933,7 +928,7 @@ void HAL_DisableDBGSleepMode(void)
|
|||
* @brief Enable the Debug Module during Domain1/CDomain STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGStopMode(void)
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
|
||||
}
|
||||
|
|
@ -942,7 +937,7 @@ void HAL_EnableDBGStopMode(void)
|
|||
* @brief Disable the Debug Module during Domain1/CDomain STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGStopMode(void)
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
|
||||
}
|
||||
|
|
@ -951,7 +946,7 @@ void HAL_DisableDBGStopMode(void)
|
|||
* @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableDBGStandbyMode(void)
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
|
||||
}
|
||||
|
|
@ -960,7 +955,7 @@ void HAL_EnableDBGStandbyMode(void)
|
|||
* @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableDBGStandbyMode(void)
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
|
||||
}
|
||||
|
|
@ -1314,4 +1309,4 @@ void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , ui
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -7,13 +7,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -53,18 +52,30 @@ typedef enum
|
|||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup REV_ID device revision ID
|
||||
* @{
|
||||
*/
|
||||
#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */
|
||||
#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */
|
||||
#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */
|
||||
#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */
|
||||
#if (STM32H7_DEV_ID == 0x450UL)
|
||||
#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */
|
||||
#else
|
||||
#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */
|
||||
#endif /* STM32H7_DEV_ID */
|
||||
#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
|
|
@ -231,7 +242,9 @@ typedef enum
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup EXTI_Event_Input_Config Event Input Config
|
||||
|
|
@ -697,9 +710,14 @@ typedef enum
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
/** @defgroup ART_Exported_Macros ART Exported Macros
|
||||
* @{
|
||||
|
|
@ -836,6 +854,10 @@ typedef enum
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBG_Exported_Macros DBG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
|
||||
|
|
@ -1003,6 +1025,12 @@ typedef enum
|
|||
#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
|
||||
|
||||
#endif /*DUAL_CORE*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
|
|
@ -1027,15 +1055,27 @@ extern HAL_TickFreqTypeDef uwTickFreq;
|
|||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
/** @defgroup HAL_Group1 Initialization and de-initialization Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
/** @defgroup HAL_Group2 HAL Control functions
|
||||
*
|
||||
*/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
|
|
@ -1079,12 +1119,12 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG
|
|||
#if defined(SYSCFG_CCCR_NCC_MMC)
|
||||
void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
|
||||
#endif /* SYSCFG_CCCR_NCC_MMC */
|
||||
void HAL_EnableDBGSleepMode(void);
|
||||
void HAL_DisableDBGSleepMode(void);
|
||||
void HAL_EnableDBGStopMode(void);
|
||||
void HAL_DisableDBGStopMode(void);
|
||||
void HAL_EnableDBGStandbyMode(void);
|
||||
void HAL_DisableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
#if defined(DUAL_CORE)
|
||||
void HAL_EnableDomain2DBGSleepMode(void);
|
||||
void HAL_DisableDomain2DBGSleepMode(void);
|
||||
|
|
@ -1126,6 +1166,14 @@ void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0);
|
|||
void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
|
||||
#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1140,4 +1188,4 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
|
|||
|
||||
#endif /* STM32H7xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -5,20 +5,22 @@
|
|||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Converter (ADC)
|
||||
* peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* ++ Initialization and Configuration of ADC
|
||||
* + Operation functions
|
||||
* ++ Start, stop, get result of conversions of regular
|
||||
* group, using 3 possible modes: polling, interruption or DMA.
|
||||
* + Control functions
|
||||
* ++ Channels configuration on regular group
|
||||
* ++ Analog Watchdog configuration
|
||||
* + State functions
|
||||
* ++ ADC state machine management
|
||||
* ++ Interrupts and flags management
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
* Other functions (extended functions) are available in file
|
||||
* "stm32h7xx_hal_adc_ex.c".
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### ADC peripheral features #####
|
||||
|
|
@ -221,11 +223,11 @@
|
|||
|
||||
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions @ref HAL_ADC_RegisterCallback()
|
||||
Use Functions HAL_ADC_RegisterCallback()
|
||||
to register an interrupt callback.
|
||||
[..]
|
||||
|
||||
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
|
||||
Function HAL_ADC_RegisterCallback() allows to register following callbacks:
|
||||
(+) ConvCpltCallback : ADC conversion complete callback
|
||||
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
|
||||
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
|
||||
|
|
@ -241,11 +243,11 @@
|
|||
and a pointer to the user callback function.
|
||||
[..]
|
||||
|
||||
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
|
||||
Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
|
||||
weak function.
|
||||
[..]
|
||||
|
||||
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) ConvCpltCallback : ADC conversion complete callback
|
||||
|
|
@ -261,27 +263,27 @@
|
|||
(+) MspDeInitCallback : ADC Msp DeInit callback
|
||||
[..]
|
||||
|
||||
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
|
||||
By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
|
||||
examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
|
||||
reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
[..]
|
||||
|
||||
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
|
||||
If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
[..]
|
||||
|
||||
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
|
||||
Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
|
||||
in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
[..]
|
||||
|
||||
Then, the user first registers the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
|
||||
or @ref HAL_ADC_Init() function.
|
||||
using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
|
||||
or HAL_ADC_Init() function.
|
||||
[..]
|
||||
|
||||
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
|
||||
|
|
@ -290,17 +292,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -2529,44 +2520,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
|
|||
/* group having no further conversion upcoming (same conditions as */
|
||||
/* regular group interruption disabling above), */
|
||||
/* and if injected scan sequence is completed. */
|
||||
if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
|
||||
((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
|
||||
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
|
||||
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
|
||||
if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
|
||||
{
|
||||
/* If End of Sequence is reached, disable interrupts */
|
||||
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
|
||||
if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
|
||||
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
|
||||
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
|
||||
{
|
||||
/* Particular case if injected contexts queue is enabled: */
|
||||
/* when the last context has been fully processed, JSQR is reset */
|
||||
/* by the hardware. Even if no injected conversion is planned to come */
|
||||
/* (queue empty, triggers are ignored), it can start again */
|
||||
/* immediately after setting a new context (JADSTART is still set). */
|
||||
/* Therefore, state of HAL ADC injected group is kept to busy. */
|
||||
if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
|
||||
/* If End of Sequence is reached, disable interrupts */
|
||||
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
|
||||
{
|
||||
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
|
||||
/* JADSTART==0 (no conversion on going) */
|
||||
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
/* Particular case if injected contexts queue is enabled: */
|
||||
/* when the last context has been fully processed, JSQR is reset */
|
||||
/* by the hardware. Even if no injected conversion is planned to come */
|
||||
/* (queue empty, triggers are ignored), it can start again */
|
||||
/* immediately after setting a new context (JADSTART is still set). */
|
||||
/* Therefore, state of HAL ADC injected group is kept to busy. */
|
||||
if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
|
||||
{
|
||||
/* Disable ADC end of sequence conversion interrupt */
|
||||
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
|
||||
|
||||
/* Set ADC state */
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
||||
|
||||
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
|
||||
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
|
||||
/* JADSTART==0 (no conversion on going) */
|
||||
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
/* Disable ADC end of sequence conversion interrupt */
|
||||
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
|
||||
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
/* Set ADC state */
|
||||
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
||||
|
||||
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
|
||||
{
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update ADC state machine to error */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
||||
|
||||
/* Set ADC error code to ADC peripheral internal error */
|
||||
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2895,17 +2888,19 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
|
|||
/* - Channel rank */
|
||||
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance != ADC3)
|
||||
if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
|
||||
{
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
|
||||
}
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance != ADC3)
|
||||
{
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
|
||||
}
|
||||
#else
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
|
||||
#endif /* ADC_VER_V5_V90 */
|
||||
}
|
||||
|
||||
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
|
||||
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
|
||||
|
|
@ -4059,4 +4054,3 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -131,8 +130,8 @@ typedef struct
|
|||
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
|
||||
Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
|
||||
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
|
||||
and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,
|
||||
use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
|
||||
and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,
|
||||
use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
|
||||
|
||||
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
|
||||
after the first ADC conversion start trigger occurred (software start or external trigger).
|
||||
|
|
@ -257,8 +256,8 @@ typedef struct
|
|||
|
||||
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
|
||||
0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
|
||||
Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024).
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
|
|
@ -756,14 +755,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
|||
/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
|
||||
* @{
|
||||
*/
|
||||
#define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
#define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -911,7 +910,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
|||
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
|
||||
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
|
||||
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
|
||||
|
||||
#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC LDO output voltage ready bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1373,7 +1372,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
|
|||
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
|
||||
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
|
||||
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
|
||||
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
|
||||
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
|
||||
* @arg @ref ADC_FLAG_LDORDY ADC LDO output voltage ready bit.
|
||||
* @retval State of flag (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
|
|
@ -2032,4 +2032,3 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
|
|||
|
||||
#endif /* STM32H7xx_HAL_ADC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -5,20 +5,21 @@
|
|||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Converter (ADC)
|
||||
* peripheral:
|
||||
* + Operation functions
|
||||
* ++ Start, stop, get result of conversions of ADC group injected,
|
||||
* using 2 possible modes: polling, interruption.
|
||||
* ++ Calibration
|
||||
* +++ ADC automatic self-calibration
|
||||
* +++ Calibration factors get or set
|
||||
* ++ Multimode feature when available
|
||||
* + Control functions
|
||||
* ++ Channels configuration on ADC group injected
|
||||
* + State functions
|
||||
* ++ ADC group injected contexts queue management
|
||||
* + Peripheral Control functions
|
||||
* Other functions (generic functions) are available in file
|
||||
* "stm32h7xx_hal_adc.c".
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
[..]
|
||||
(@) Sections "ADC peripheral features" and "How to use this driver" are
|
||||
|
|
@ -26,17 +27,6 @@
|
|||
[..]
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -265,7 +255,9 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc,
|
|||
* @param SingleDiff This parameter can be only:
|
||||
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
|
||||
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
|
||||
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
|
||||
* @param CalibrationFactor Calibration factor On devices STM32H72xx and STM32H73xx this parameter is coded on 11 bits
|
||||
* maximum for ADC1/2 and on 7 bits for ADC3.
|
||||
* On devices STM32H74xx and STM32H75xx this parameter is coded on 11 bits.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
|
||||
|
|
@ -277,7 +269,19 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
|
|||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
||||
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
|
||||
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance == ADC3)
|
||||
{
|
||||
assert_param(IS_ADC_CALFACT_ADC3(CalibrationFactor));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_ADC_CALFACT(CalibrationFactor));
|
||||
}
|
||||
#else
|
||||
assert_param(IS_ADC_CALFACT(CalibrationFactor));
|
||||
#endif
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
|
@ -1001,8 +1005,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
|
|||
* Interruptions enabled in this function:
|
||||
* overrun, DMA half transfer, DMA transfer complete.
|
||||
* Each of these interruptions has its dedicated callback function.
|
||||
* @note Case of ADC slave using its own DMA channel (typical case being both ADC instances using DMA channel
|
||||
* of ADC master with data concatenated): multimode must be configured without data packing and
|
||||
* this function must be called first with handle of ADC slave, then with handle of ADC master.
|
||||
* @note State field of Slave ADC handle is not updated in this configuration:
|
||||
* user should not rely on it for information related to Slave regular
|
||||
* user should not rely on it for information related to Slave regular
|
||||
* conversions.
|
||||
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
|
||||
* @param pData Destination Buffer address.
|
||||
|
|
@ -1029,28 +1036,38 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hadc);
|
||||
|
||||
tmphadcSlave.State = HAL_ADC_STATE_RESET;
|
||||
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
|
||||
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
||||
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
||||
|
||||
if (tmphadcSlave.Instance == NULL)
|
||||
/* Case of ADC slave using its own DMA channel: check whether handle selected
|
||||
corresponds to ADC master or slave instance */
|
||||
if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
|
||||
{
|
||||
/* Set ADC state */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_ERROR;
|
||||
/* Case of ADC slave selected: enable ADC instance */
|
||||
tmp_hal_status = ADC_Enable(hadc);
|
||||
}
|
||||
|
||||
/* Enable the ADC peripherals: master and slave (in case if not already */
|
||||
/* enabled previously) */
|
||||
tmp_hal_status = ADC_Enable(hadc);
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
else
|
||||
{
|
||||
tmp_hal_status = ADC_Enable(&tmphadcSlave);
|
||||
tmphadcSlave.State = HAL_ADC_STATE_RESET;
|
||||
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
|
||||
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
||||
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
||||
|
||||
if (tmphadcSlave.Instance == NULL)
|
||||
{
|
||||
/* Set ADC state */
|
||||
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hadc);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Enable the ADC peripherals: master and slave (in case if not already */
|
||||
/* enabled previously) */
|
||||
tmp_hal_status = ADC_Enable(hadc);
|
||||
if (tmp_hal_status == HAL_OK)
|
||||
{
|
||||
tmp_hal_status = ADC_Enable(&tmphadcSlave);
|
||||
}
|
||||
}
|
||||
|
||||
/* Start multimode conversion of ADCs pair */
|
||||
|
|
@ -1073,9 +1090,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
|
|||
/* Set the DMA error callback */
|
||||
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
|
||||
|
||||
/* Pointer to the common control register */
|
||||
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
||||
|
||||
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
|
||||
/* start (in case of SW start): */
|
||||
|
||||
|
|
@ -1091,15 +1105,29 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
|
|||
/* Enable ADC overrun interrupt */
|
||||
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
|
||||
|
||||
/* Start the DMA channel */
|
||||
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
|
||||
/* Case of ADC slave using its own DMA channel: check whether handle selected
|
||||
corresponds to ADC master or slave instance */
|
||||
if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
|
||||
{
|
||||
/* Case of ADC slave selected: Start the DMA channel. */
|
||||
/* Note: Data transfer will start upon next call of this function using handle of ADC master */
|
||||
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Pointer to the common control register */
|
||||
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
||||
|
||||
/* Enable conversion of regular group. */
|
||||
/* If software start has been selected, conversion starts immediately. */
|
||||
/* If external trigger has been selected, conversion will start at next */
|
||||
/* trigger event. */
|
||||
/* Start ADC group regular conversion */
|
||||
LL_ADC_REG_StartConversion(hadc->Instance);
|
||||
/* Start the DMA channel */
|
||||
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
|
||||
|
||||
/* Enable conversion of regular group. */
|
||||
/* If software start has been selected, conversion starts immediately. */
|
||||
/* If external trigger has been selected, conversion will start at next */
|
||||
/* trigger event. */
|
||||
/* Start ADC group regular conversion */
|
||||
LL_ADC_REG_StartConversion(hadc->Instance);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -2025,16 +2053,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
|||
/* mode is disabled. */
|
||||
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
|
||||
{
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance != ADC3)
|
||||
if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)))
|
||||
{
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
|
||||
}
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance != ADC3)
|
||||
{
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
|
||||
}
|
||||
#else
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
|
||||
/* ADC channels preselection */
|
||||
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
|
||||
#endif /* ADC_VER_V5_V90 */
|
||||
}
|
||||
|
||||
/* If auto-injected mode is disabled: no constraint */
|
||||
if (sConfigInjected->AutoInjectedConv == DISABLE)
|
||||
|
|
@ -2102,7 +2133,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
|||
|
||||
if (sConfigInjected->InjecOversamplingMode == ENABLE)
|
||||
{
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance == ADC3)
|
||||
{
|
||||
assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(sConfigInjected->InjecOversampling.Ratio));
|
||||
}
|
||||
else
|
||||
{
|
||||
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
|
||||
}
|
||||
#else
|
||||
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
|
||||
#endif
|
||||
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
|
||||
|
||||
/* JOVSE must be reset in case of triggered regular mode */
|
||||
|
|
@ -2113,14 +2155,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
|||
/* - Right bit shift */
|
||||
|
||||
/* Enable OverSampling mode */
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
if (hadc->Instance != ADC3)
|
||||
{
|
||||
MODIFY_REG(hadc->Instance->CFGR2,
|
||||
ADC_CFGR2_JOVSE |
|
||||
ADC_CFGR2_OVSR |
|
||||
ADC_CFGR2_OVSS,
|
||||
ADC_CFGR2_JOVSE |
|
||||
((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
|
||||
sConfigInjected->InjecOversampling.RightBitShift
|
||||
);
|
||||
}
|
||||
else
|
||||
{
|
||||
MODIFY_REG(hadc->Instance->CFGR2,
|
||||
ADC_CFGR2_JOVSE |
|
||||
ADC3_CFGR2_OVSR |
|
||||
ADC_CFGR2_OVSS,
|
||||
ADC_CFGR2_JOVSE |
|
||||
(sConfigInjected->InjecOversampling.Ratio) |
|
||||
sConfigInjected->InjecOversampling.RightBitShift
|
||||
);
|
||||
}
|
||||
#else
|
||||
MODIFY_REG(hadc->Instance->CFGR2,
|
||||
ADC_CFGR2_JOVSE |
|
||||
ADC_CFGR2_OVSR |
|
||||
ADC_CFGR2_OVSS,
|
||||
ADC_CFGR2_JOVSE |
|
||||
((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
|
||||
sConfigInjected->InjecOversampling.RightBitShift
|
||||
);
|
||||
ADC_CFGR2_JOVSE |
|
||||
ADC_CFGR2_OVSR |
|
||||
ADC_CFGR2_OVSS,
|
||||
ADC_CFGR2_JOVSE |
|
||||
((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
|
||||
sConfigInjected->InjecOversampling.RightBitShift
|
||||
);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -2145,7 +2212,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
|
|||
{
|
||||
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
|
||||
}
|
||||
|
||||
|
||||
if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
|
||||
{
|
||||
/* Set ADC selected offset number */
|
||||
|
|
@ -2590,4 +2657,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -113,8 +112,8 @@ typedef struct
|
|||
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
|
||||
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
|
||||
Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024).
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
|
|
@ -138,7 +137,7 @@ typedef struct
|
|||
FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
|
||||
This parameter is applied only for 16-bit or 8-bit resolution.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
|
|
@ -250,8 +249,10 @@ typedef struct
|
|||
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
|
||||
#if defined(HRTIM1)
|
||||
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
|
||||
#endif /* HRTIM1 */
|
||||
#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */
|
||||
|
|
@ -917,12 +918,20 @@ typedef struct
|
|||
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
|
||||
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum).
|
||||
* @brief Calibration factor size verification (11 bits maximum).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FFU))
|
||||
|
||||
#if defined(ADC_VER_V5_V90)
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum on ADC3).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT_ADC3(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting.
|
||||
|
|
@ -1044,6 +1053,7 @@ typedef struct
|
|||
* @param __INJTRIG__ programmed ADC injected conversions external trigger.
|
||||
* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
|
||||
*/
|
||||
#if defined (HRTIM1)
|
||||
#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
|
|
@ -1060,9 +1070,36 @@ typedef struct
|
|||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
|
||||
\
|
||||
((__INJTRIG__) == ADC_SOFTWARE_START) )
|
||||
|
||||
#else
|
||||
#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
|
||||
\
|
||||
((__INJTRIG__) == ADC_SOFTWARE_START) )
|
||||
#endif /* HRTIM */
|
||||
/**
|
||||
* @brief Verify the ADC edge trigger setting for injected group.
|
||||
* @param __EDGE__ programmed ADC edge trigger setting.
|
||||
|
|
@ -1349,4 +1386,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *h
|
|||
#endif /* STM32H7xx_HAL_ADC_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -11,6 +11,17 @@
|
|||
* + Peripheral Control function
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -47,10 +58,10 @@
|
|||
|
||||
The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
|
||||
Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
|
||||
to register an interrupt callback.
|
||||
|
||||
Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
|
||||
Function HAL_CEC_RegisterCallback() allows to register following callbacks:
|
||||
(+) TxCpltCallback : Tx Transfer completed callback.
|
||||
(+) ErrorCallback : callback for error detection.
|
||||
(+) MspInitCallback : CEC MspInit.
|
||||
|
|
@ -59,11 +70,11 @@
|
|||
and a pointer to the user callback function.
|
||||
|
||||
For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
|
||||
@ref HAL_CEC_RegisterRxCpltCallback().
|
||||
HAL_CEC_RegisterRxCpltCallback().
|
||||
|
||||
Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
|
||||
Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
|
||||
weak function.
|
||||
@ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TxCpltCallback : Tx Transfer completed callback.
|
||||
|
|
@ -72,15 +83,15 @@
|
|||
(+) MspDeInitCallback : CEC MspDeInit.
|
||||
|
||||
For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
|
||||
@ref HAL_CEC_UnRegisterRxCpltCallback().
|
||||
HAL_CEC_UnRegisterRxCpltCallback().
|
||||
|
||||
By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
|
||||
By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions :
|
||||
examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
|
||||
examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
|
||||
reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
|
||||
if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit functions (registered beforehand)
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
|
||||
|
|
@ -88,25 +99,14 @@
|
|||
in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
|
||||
or @ref HAL_CEC_Init() function.
|
||||
using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
|
||||
or HAL_CEC_Init() function.
|
||||
|
||||
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -233,7 +233,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
|
|||
|
||||
/* Write to CEC Control Register */
|
||||
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
|
||||
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
|
||||
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
|
||||
hcec->Init.BroadcastMsgNoErrorBitGen | \
|
||||
hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
|
||||
hcec->Init.ListenMode;
|
||||
|
||||
|
|
@ -412,10 +413,10 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
|
|||
* @param hcec CEC handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
@ -497,14 +498,14 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call
|
|||
|
||||
/**
|
||||
* @brief Unregister an CEC Callback
|
||||
* CEC callabck is redirected to the weak predefined callback
|
||||
* CEC callback is redirected to the weak predefined callback
|
||||
* @param hcec uart handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
|
||||
* @arg HAL_CEC_ERROR_CB_ID Error callback ID
|
||||
* @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
|
||||
|
|
@ -694,9 +695,9 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
uint8_t *pData, uint32_t Size)
|
||||
const uint8_t *pData, uint32_t Size)
|
||||
{
|
||||
/* if the IP isn't already busy and if there is no previous transmission
|
||||
/* if the peripheral isn't already busy and if there is no previous transmission
|
||||
already pending due to arbitration lost */
|
||||
if (hcec->gState == HAL_CEC_STATE_READY)
|
||||
{
|
||||
|
|
@ -749,7 +750,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
|
|||
* @param hcec CEC handle
|
||||
* @retval Frame size
|
||||
*/
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
return hcec->RxXferSize;
|
||||
}
|
||||
|
|
@ -775,13 +776,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
{
|
||||
|
||||
/* save interrupts register for further error or interrupts handling purposes */
|
||||
uint32_t reg;
|
||||
reg = hcec->Instance->ISR;
|
||||
uint32_t itflag;
|
||||
itflag = hcec->Instance->ISR;
|
||||
|
||||
|
||||
/* ----------------------------Arbitration Lost Management----------------------------------*/
|
||||
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
|
||||
if ((reg & CEC_FLAG_ARBLST) != 0U)
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
|
||||
{
|
||||
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
|
||||
|
|
@ -789,7 +790,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
|
||||
/* ----------------------------Rx Management----------------------------------*/
|
||||
/* CEC RX byte received interrupt ---------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_RXBR) != 0U)
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
|
||||
{
|
||||
/* reception is starting */
|
||||
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
|
||||
|
|
@ -801,7 +802,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
}
|
||||
|
||||
/* CEC RX end received interrupt ---------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_RXEND) != 0U)
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
|
||||
{
|
||||
/* clear IT */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
|
||||
|
|
@ -820,7 +821,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
|
||||
/* ----------------------------Tx Management----------------------------------*/
|
||||
/* CEC TX byte request interrupt ------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_TXBR) != 0U)
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
|
||||
{
|
||||
--hcec->TxXferCount;
|
||||
if (hcec->TxXferCount == 0U)
|
||||
|
|
@ -829,14 +830,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
|
||||
}
|
||||
/* In all cases transmit the byte */
|
||||
hcec->Instance->TXDR = *hcec->pTxBuffPtr;
|
||||
hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
|
||||
hcec->pTxBuffPtr++;
|
||||
/* clear Tx-Byte request flag */
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
|
||||
}
|
||||
|
||||
/* CEC TX end interrupt ------------------------------------------------*/
|
||||
if ((reg & CEC_FLAG_TXEND) != 0U)
|
||||
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
|
||||
{
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
|
||||
|
||||
|
|
@ -854,21 +855,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
|||
}
|
||||
|
||||
/* ----------------------------Rx/Tx Error Management----------------------------------*/
|
||||
if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
|
||||
CEC_ISR_TXACKE)) != 0U)
|
||||
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
|
||||
CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
|
||||
{
|
||||
hcec->ErrorCode = reg;
|
||||
hcec->ErrorCode = itflag;
|
||||
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
|
||||
HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
|
||||
|
||||
|
||||
if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
|
||||
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
|
||||
{
|
||||
hcec->Init.RxBuffer -= hcec->RxXferSize;
|
||||
hcec->RxXferSize = 0U;
|
||||
hcec->RxState = HAL_CEC_STATE_READY;
|
||||
}
|
||||
else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
|
||||
else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
|
||||
{
|
||||
/* Set the CEC state ready to be able to start again the process */
|
||||
hcec->gState = HAL_CEC_STATE_READY;
|
||||
|
|
@ -957,9 +958,10 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
|
|||
* the configuration information for the specified CEC module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
uint32_t temp1, temp2;
|
||||
uint32_t temp1;
|
||||
uint32_t temp2;
|
||||
temp1 = hcec->gState;
|
||||
temp2 = hcec->RxState;
|
||||
|
||||
|
|
@ -972,7 +974,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
|
|||
* the configuration information for the specified CEC.
|
||||
* @retval CEC Error Code
|
||||
*/
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
|
||||
{
|
||||
return hcec->ErrorCode;
|
||||
}
|
||||
|
|
@ -993,5 +995,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -49,70 +48,80 @@ extern "C" {
|
|||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of @ref CEC_Signal_Free_Time
|
||||
It can be one of CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
|
||||
or CEC_EXTENDED_TOLERANCE */
|
||||
it can be a value of CEC_Tolerance :
|
||||
it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
|
||||
Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
|
||||
Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
|
||||
Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error
|
||||
handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
|
||||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if
|
||||
BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
|
||||
there is no error-bit generation in case of Short Bit Period Error detection in
|
||||
a broadcast message while LSTN bit is set. */
|
||||
no error-bit generation in case neither a) nor b) are satisfied.
|
||||
Additionally, there is no error-bit generation in case of Short Bit
|
||||
Period Error detection in a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
|
||||
of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
||||
uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
|
||||
It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
|
||||
own address (OAR). Messages addressed to different destination are ignored.
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
|
||||
to its own address (OAR). Messages addressed to different destination
|
||||
are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
|
||||
address (OAR) with positive acknowledge. Messages addressed to different destination
|
||||
are received, but without interfering with the CEC bus: no acknowledge sent. */
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
|
||||
own address (OAR) with positive acknowledge. Messages addressed to
|
||||
different destination are received, but without interfering with the
|
||||
CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of @ref CEC_OWN_ADDRESS */
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
|
||||
|
||||
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
|
||||
(see CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
|
|
@ -121,14 +130,14 @@ typedef struct
|
|||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL CEC Init function already called)
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
|
|
@ -138,9 +147,9 @@ typedef struct
|
|||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b5 CEC peripheral initialization status
|
||||
* 0 : Reset (peripheral not initialized)
|
||||
* 1 : Init done (peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
|
|
@ -160,37 +169,37 @@ typedef struct __CEC_HandleTypeDef
|
|||
typedef struct
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
This parameter can be a value of HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
in case error is reported */
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
|
||||
*hcec); /*!< CEC Tx Transfer completed callback */
|
||||
*hcec); /*!< CEC Tx Transfer completed callback */
|
||||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
} CEC_HandleTypeDef;
|
||||
|
|
@ -203,7 +212,7 @@ typedef enum
|
|||
{
|
||||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
|
||||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
|
||||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
|
||||
} HAL_CEC_CallbackIDTypeDef;
|
||||
|
|
@ -213,7 +222,8 @@ typedef enum
|
|||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
|
||||
callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -359,16 +369,16 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
|||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
|
||||
|
|
@ -422,8 +432,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
|||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -431,7 +441,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
|||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -439,7 +449,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
|||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -623,7 +633,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
|||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
|
||||
(__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -661,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
|||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
|
||||
const uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
|
|
@ -676,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -732,8 +743,9 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
|||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
|
||||
(((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
|
||||
|
|
@ -790,5 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xxHAL_CEC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,10 +6,19 @@
|
|||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Start/Stop operation functions in polling mode
|
||||
* + Start/Stop operation functions in interrupt mode
|
||||
* + Peripheral control functions
|
||||
* + Peripheral state functions
|
||||
* + Peripheral state functions
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### COMP Peripheral features #####
|
||||
|
|
@ -98,11 +107,11 @@
|
|||
|
||||
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions @ref HAL_COMP_RegisterCallback()
|
||||
Use Functions HAL_COMP_RegisterCallback()
|
||||
to register an interrupt callback.
|
||||
[..]
|
||||
|
||||
Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
|
||||
Function HAL_COMP_RegisterCallback() allows to register following callbacks:
|
||||
(+) TriggerCallback : callback for COMP trigger.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
|
|
@ -110,11 +119,11 @@
|
|||
and a pointer to the user callback function.
|
||||
[..]
|
||||
|
||||
Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
|
||||
Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
|
||||
weak function.
|
||||
[..]
|
||||
|
||||
@ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TriggerCallback : callback for COMP trigger.
|
||||
|
|
@ -122,27 +131,27 @@
|
|||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
[..]
|
||||
|
||||
By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
|
||||
By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
example @ref HAL_COMP_TriggerCallback().
|
||||
example HAL_COMP_TriggerCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
|
||||
reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
[..]
|
||||
|
||||
If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
|
||||
If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
[..]
|
||||
|
||||
Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
|
||||
Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
|
||||
in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
[..]
|
||||
|
||||
Then, the user first registers the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
|
||||
or @ref HAL_COMP_Init() function.
|
||||
using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
|
||||
or HAL_COMP_Init() function.
|
||||
[..]
|
||||
|
||||
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
|
||||
|
|
@ -179,17 +188,6 @@
|
|||
(1) GPIO must be set to alternate function for comparator
|
||||
(2) Comparators output to timers is set in timers instances.
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -1247,4 +1245,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -951,4 +950,4 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
|
|||
|
||||
#endif /* STM32H7xx_HAL_COMP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,18 @@
|
|||
* + IRQ handler management
|
||||
* + Peripheral State functions
|
||||
*
|
||||
* @verbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
|
|
@ -79,9 +90,9 @@
|
|||
|
||||
The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback.
|
||||
Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.
|
||||
|
||||
Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks:
|
||||
Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
|
||||
(+) ErrorCallback : Error Callback.
|
||||
(+) CalculateCpltCallback : Calculate complete Callback.
|
||||
(+) MspInitCallback : CORDIC MspInit.
|
||||
|
|
@ -89,9 +100,9 @@
|
|||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
|
||||
Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
|
||||
weak function.
|
||||
@ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) ErrorCallback : Error Callback.
|
||||
|
|
@ -101,11 +112,11 @@
|
|||
|
||||
By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback().
|
||||
examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when
|
||||
reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit()
|
||||
if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
|
||||
|
||||
Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
|
||||
|
|
@ -113,7 +124,7 @@
|
|||
in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit()
|
||||
using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
|
||||
or HAL_CORDIC_Init() function.
|
||||
|
||||
When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
|
||||
|
|
@ -121,18 +132,6 @@
|
|||
are set to the corresponding weak functions.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -160,8 +159,8 @@
|
|||
/** @defgroup CORDIC_Private_Functions CORDIC Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff);
|
||||
static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
|
||||
static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff);
|
||||
static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
|
||||
static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
|
||||
static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
|
||||
static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
|
||||
|
|
@ -556,7 +555,7 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H
|
|||
* contains the CORDIC configuration information.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig)
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -603,12 +602,12 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con
|
|||
* @param Timeout Specify Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t index;
|
||||
int32_t *p_tmp_in_buff = pInBuff;
|
||||
const int32_t *p_tmp_in_buff = pInBuff;
|
||||
int32_t *p_tmp_out_buff = pOutBuff;
|
||||
|
||||
/* Check parameters setting */
|
||||
|
|
@ -697,12 +696,12 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p
|
|||
* @param Timeout Specify Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t index;
|
||||
int32_t *p_tmp_in_buff = pInBuff;
|
||||
const int32_t *p_tmp_in_buff = pInBuff;
|
||||
int32_t *p_tmp_out_buff = pOutBuff;
|
||||
|
||||
/* Check parameters setting */
|
||||
|
|
@ -790,10 +789,10 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t
|
|||
* @param NbCalc Number of CORDIC calculation to process.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc)
|
||||
{
|
||||
int32_t *tmp_pInBuff = pInBuff;
|
||||
const int32_t *tmp_pInBuff = pInBuff;
|
||||
|
||||
/* Check parameters setting */
|
||||
if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
|
||||
|
|
@ -882,13 +881,11 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t
|
|||
* DMA transfer to and from the Peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t DMADirection)
|
||||
{
|
||||
uint32_t sizeinbuff;
|
||||
uint32_t sizeoutbuff;
|
||||
uint32_t inputaddr;
|
||||
uint32_t outputaddr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
|
||||
|
|
@ -961,10 +958,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
|
|||
sizeoutbuff = NbCalc;
|
||||
}
|
||||
|
||||
outputaddr = (uint32_t)pOutBuff;
|
||||
|
||||
/* Enable the DMA stream managing CORDIC output data read */
|
||||
if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff)
|
||||
!= HAL_OK)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
|
||||
|
|
@ -996,10 +992,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
|
|||
sizeinbuff = NbCalc;
|
||||
}
|
||||
|
||||
inputaddr = (uint32_t)pInBuff;
|
||||
|
||||
/* Enable the DMA stream managing CORDIC input data write */
|
||||
if (HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) != HAL_OK)
|
||||
if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff)
|
||||
!= HAL_OK)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
|
||||
|
|
@ -1138,7 +1133,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
|
|||
/*Call registered callback*/
|
||||
hcordic->CalculateCpltCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_CalculateCpltCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1170,7 +1165,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
|
|||
* the configuration information for CORDIC module
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic)
|
||||
{
|
||||
/* Return CORDIC handle state */
|
||||
return hcordic->State;
|
||||
|
|
@ -1183,7 +1178,7 @@ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
|
|||
* @note The returned error is a bit-map combination of possible errors
|
||||
* @retval Error bit-map
|
||||
*/
|
||||
uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
|
||||
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic)
|
||||
{
|
||||
/* Return CORDIC error code */
|
||||
return hcordic->ErrorCode;
|
||||
|
|
@ -1208,7 +1203,7 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
|
|||
* @param ppInBuff Pointer to pointer to input buffer.
|
||||
* @retval none
|
||||
*/
|
||||
static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff)
|
||||
static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff)
|
||||
{
|
||||
/* First write of input data in the Write Data register */
|
||||
WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
|
||||
|
|
@ -1234,7 +1229,7 @@ static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_
|
|||
* @param ppOutBuff Pointer to pointer to output buffer.
|
||||
* @retval none
|
||||
*/
|
||||
static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
|
||||
static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
|
||||
{
|
||||
/* First read of output data from the Read Data register */
|
||||
**ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
|
||||
|
|
@ -1279,7 +1274,7 @@ static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
|
|||
/*Call registered callback*/
|
||||
hcordic->CalculateCpltCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_CalculateCpltCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1308,7 +1303,7 @@ static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
|
|||
/*Call registered callback*/
|
||||
hcordic->CalculateCpltCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_CalculateCpltCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1333,7 +1328,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
|
|||
/*Call registered callback*/
|
||||
hcordic->ErrorCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_ErrorCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1352,5 +1347,3 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
|
|||
|
||||
#endif /* HAL_CORDIC_MODULE_ENABLED */
|
||||
#endif /* CORDIC */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -7,13 +7,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -65,7 +64,7 @@ typedef struct
|
|||
{
|
||||
CORDIC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
|
||||
const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
|
||||
|
||||
int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
|
||||
|
||||
|
|
@ -547,14 +546,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H
|
|||
*/
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t DMADirection);
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -583,8 +582,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic);
|
||||
uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
|
||||
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -608,5 +607,3 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_CORDIC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -68,13 +68,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -289,10 +288,43 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
|
|||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the MPU Region.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Enable the Region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the MPU Region.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
|
|
@ -300,38 +332,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != 0UL)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00;
|
||||
MPU->RASR = 0x00;
|
||||
}
|
||||
/* Apply configuration */
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
|
|
@ -530,4 +556,3 @@ uint32_t HAL_GetCurrentCPUID(void)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -308,6 +307,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
|||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
|
|
@ -458,4 +459,3 @@ uint32_t HAL_GetCurrentCPUID(void);
|
|||
#endif /* STM32H7xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -9,6 +9,17 @@
|
|||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -29,17 +40,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -62,8 +62,8 @@
|
|||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
|
|
@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
|
|||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
|
|
@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
|||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Reset IDR register content */
|
||||
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
|
||||
CLEAR_REG(hcrc->Instance->IDR);
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
|
@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
|||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
|
@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
|||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
|
|
@ -403,7 +403,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
|||
* @param hcrc CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Return CRC handle state */
|
||||
return hcrc->State;
|
||||
|
|
@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
|||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
|
|
@ -514,5 +514,3 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -60,19 +59,22 @@ typedef struct
|
|||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
|
||||
X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
|
||||
CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
|
||||
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal,
|
||||
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
|
||||
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
|
||||
DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
|
|
@ -87,14 +89,18 @@ typedef struct
|
|||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
|
||||
becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
|
||||
0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
|
||||
becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
|
||||
into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -112,12 +118,16 @@ typedef struct
|
|||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
|
||||
(8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
|
||||
half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
|
||||
(32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
|
||||
error must occur if InputBufferFormat is not one of the three values listed
|
||||
above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -199,15 +209,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -317,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
|
|||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -339,5 +340,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,6 +6,17 @@
|
|||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the CRC peripheral.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -16,17 +27,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
|
|||
/* Check the parameters */
|
||||
assert_param(IS_CRC_POL_LENGTH(PolyLength));
|
||||
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
/* Ensure that the generating polynomial is odd */
|
||||
if ((Pol & (uint32_t)(0x1U)) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
switch (PolyLength)
|
||||
else
|
||||
{
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
{
|
||||
}
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
switch (PolyLength)
|
||||
{
|
||||
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
|
|
@ -221,5 +230,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -149,5 +148,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_CRC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -48,8 +47,8 @@ extern "C" {
|
|||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t DataType; /*!< no swap(32-bit data), halfword swap(16-bit data), byte swap(8-bit data)
|
||||
or bit swap(1-bit data).this parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
|
|
@ -61,9 +60,9 @@ typedef struct
|
|||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to configure Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processing.
|
||||
|
|
@ -211,7 +210,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< Size unit is byte, but all input will be loaded in HW CRYPT IP by block of 4 words */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -222,7 +221,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< Size unit is byte, but all input will be loaded in HW CRYPT IP by block of 4 words */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -262,10 +261,10 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATATYPE_32B 0x00000000U
|
||||
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
|
||||
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
|
||||
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
|
||||
#define CRYP_NO_SWAP 0x00000000U
|
||||
#define CRYP_HALFWORD_SWAP CRYP_CR_DATATYPE_0
|
||||
#define CRYP_BYTE_SWAP CRYP_CR_DATATYPE_1
|
||||
#define CRYP_BIT_SWAP CRYP_CR_DATATYPE
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -359,8 +358,11 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
*/
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) &\
|
||||
((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->RISR) &\
|
||||
((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
|
|
@ -371,7 +373,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
|
|||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR &\
|
||||
(__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
|
|
@ -488,10 +491,10 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
|||
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_NO_SWAP) || \
|
||||
((DATATYPE) == CRYP_HALFWORD_SWAP) || \
|
||||
((DATATYPE) == CRYP_BYTE_SWAP) || \
|
||||
((DATATYPE) == CRYP_BIT_SWAP))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
|
|
@ -565,4 +568,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
|||
|
||||
#endif /* STM32H7xx_HAL_CRYP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -7,6 +7,17 @@
|
|||
* functionalities of CRYP extension peripheral:
|
||||
* + Extended AES processing functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -16,18 +27,6 @@
|
|||
Encryption/Decryption to get the authentication messages.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -103,9 +102,9 @@
|
|||
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
|
||||
* the configuration information for CRYP module
|
||||
* @param AuthTag: Pointer to the authentication buffer
|
||||
* the AuthTag generated here is 128bits length, if the TAG length is
|
||||
* the AuthTag generated here is 128bits length, if the TAG length is
|
||||
* less than 128bits, user should consider only the valid part of AuthTag
|
||||
* buffer which correspond exactly to TAG length.
|
||||
* buffer which correspond exactly to TAG length.
|
||||
* @param Timeout: Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
@ -116,7 +115,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
|
||||
uint32_t tagaddr = (uint32_t)AuthTag;
|
||||
|
||||
/* Correct header length if Init.HeaderSize is actually in bytes */
|
||||
/* Correct header length if Init.HeaderSize is actually in bytes */
|
||||
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
|
||||
{
|
||||
headerlength /= 4U;
|
||||
|
|
@ -179,28 +178,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
#if !defined (CRYP_VER_2_2)
|
||||
else/* data has to be swapped according to the DATATYPE */
|
||||
{
|
||||
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
|
||||
if (hcryp->Init.DataType == CRYP_BIT_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
|
||||
}
|
||||
else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
|
||||
else if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
|
||||
}
|
||||
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
|
||||
else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
|
||||
}
|
||||
else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
|
||||
else if (hcryp->Init.DataType == CRYP_NO_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = 0U;
|
||||
hcryp->Instance->DIN = (uint32_t)(headerlength);
|
||||
|
|
@ -269,9 +268,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
|
||||
* the configuration information for CRYP module
|
||||
* @param AuthTag: Pointer to the authentication buffer
|
||||
* the AuthTag generated here is 128bits length, if the TAG length is
|
||||
* the AuthTag generated here is 128bits length, if the TAG length is
|
||||
* less than 128bits, user should consider only the valid part of AuthTag
|
||||
* buffer which correspond exactly to TAG length.
|
||||
* buffer which correspond exactly to TAG length.
|
||||
* @param Timeout: Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
|
@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
#if !defined (CRYP_VER_2_2)
|
||||
else /* data has to be swapped according to the DATATYPE */
|
||||
{
|
||||
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
|
||||
if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
|
||||
ctr0addr += 4U;
|
||||
|
|
@ -354,7 +353,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
ctr0addr += 4U;
|
||||
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
|
||||
}
|
||||
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
|
||||
else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
|
||||
ctr0addr += 4U;
|
||||
|
|
@ -364,7 +363,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
ctr0addr += 4U;
|
||||
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
|
||||
}
|
||||
else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
|
||||
else if (hcryp->Init.DataType == CRYP_BIT_SWAP)
|
||||
{
|
||||
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
|
||||
ctr0addr += 4U;
|
||||
|
|
@ -455,4 +454,3 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -120,4 +119,3 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
|
|||
|
||||
#endif /* STM32H7xx_HAL_CRYP_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -11,6 +11,17 @@
|
|||
* + Peripheral State and Errors functions
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
|
|
@ -48,6 +59,7 @@
|
|||
(DAC_TRIGGER_HR1_TRGO1, DAC_TRIGGER_HR1_TRGO2)
|
||||
|
||||
(#) Software using DAC_TRIGGER_SOFTWARE
|
||||
|
||||
*** DAC Buffer mode feature ***
|
||||
===============================
|
||||
[..]
|
||||
|
|
@ -60,15 +72,6 @@
|
|||
(@) Refer to the device datasheet for more details about output
|
||||
impedance value with and without output buffer.
|
||||
|
||||
*** DAC connect feature ***
|
||||
===============================
|
||||
[..]
|
||||
Each DAC channel can be connected internally.
|
||||
To connect, use
|
||||
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
|
||||
or
|
||||
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
|
||||
|
||||
*** GPIO configurations guidelines ***
|
||||
=====================
|
||||
[..]
|
||||
|
|
@ -219,7 +222,7 @@
|
|||
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
|
||||
Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
|
||||
Use Functions HAL_DAC_RegisterCallback() to register a user callback,
|
||||
it allows to register following callbacks:
|
||||
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
|
||||
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
|
||||
|
|
@ -234,8 +237,8 @@
|
|||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function. It allows to reset following callbacks:
|
||||
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
|
||||
weak (overridden) function. It allows to reset following callbacks:
|
||||
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
|
||||
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
|
||||
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
|
||||
|
|
@ -249,12 +252,12 @@
|
|||
(+) All Callbacks
|
||||
This function) takes as parameters the HAL peripheral handle and the Callback ID.
|
||||
|
||||
By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
|
||||
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (overridden) functions.
|
||||
Exception done for MspInit and MspDeInit callbacks that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
|
||||
and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
|
||||
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
|
||||
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
|
||||
|
||||
Callbacks can be registered/unregistered in READY state only.
|
||||
|
|
@ -262,12 +265,12 @@
|
|||
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
|
||||
during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
|
||||
or @ref HAL_DAC_Init function.
|
||||
using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
|
||||
or HAL_DAC_Init function.
|
||||
|
||||
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak (overridden) callbacks are used.
|
||||
|
||||
*** DAC HAL driver macros list ***
|
||||
=============================================
|
||||
|
|
@ -283,17 +286,6 @@
|
|||
(@) You can refer to the DAC HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -357,7 +349,7 @@
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
|
|
@ -418,7 +410,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Check DAC handle */
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
|
|
@ -521,6 +513,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
|
|
@ -542,6 +540,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Check if software trigger enabled */
|
||||
|
|
@ -552,6 +551,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
|
|
@ -574,6 +574,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
|
|
@ -595,7 +601,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @param pData The destination peripheral Buffer address.
|
||||
* @param pData The source Buffer address.
|
||||
* @param Length The length of data to be transferred from memory to DAC peripheral
|
||||
* @param Alignment Specifies the data alignment for DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -604,11 +610,17 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
uint32_t tmpreg = 0U;
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
|
@ -645,14 +657,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
|
|||
/* Get DHR12L1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
default: /* case DAC_ALIGN_8B_R */
|
||||
/* Get DHR8R1 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Set the DMA transfer complete callback for channel2 */
|
||||
|
|
@ -678,16 +689,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
|
|||
/* Get DHR12L2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||
break;
|
||||
case DAC_ALIGN_8B_R:
|
||||
default: /* case DAC_ALIGN_8B_R */
|
||||
/* Get DHR8R2 address */
|
||||
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the DMA Stream */
|
||||
if (Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
|
|
@ -696,6 +704,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
|
|||
/* Enable the DMA Stream */
|
||||
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Enable the DAC DMA underrun interrupt */
|
||||
|
|
@ -705,6 +714,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
|
|||
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||
}
|
||||
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdac);
|
||||
|
||||
|
|
@ -734,6 +744,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
|
|
@ -754,6 +770,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
/* Disable the DAC DMA underrun interrupt */
|
||||
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||
}
|
||||
|
||||
else /* Channel2 is used for */
|
||||
{
|
||||
/* Disable the DMA Stream */
|
||||
|
|
@ -763,6 +780,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||
}
|
||||
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
||||
|
|
@ -780,22 +798,25 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
*/
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
|
||||
uint32_t itsource = hdac->Instance->CR;
|
||||
uint32_t itflag = hdac->Instance->SR;
|
||||
|
||||
if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
|
||||
{
|
||||
/* Check underrun flag of DAC channel 1 */
|
||||
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||
if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
||||
/* Set DAC error code to chanel1 DMA underrun error */
|
||||
/* Set DAC error code to channel1 DMA underrun error */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
|
||||
|
||||
/* Clear the underrun flag */
|
||||
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
|
||||
|
||||
/* Disable the selected DAC channel1 DMA request */
|
||||
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
|
||||
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
|
||||
|
||||
/* Error callback */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
|
|
@ -806,10 +827,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
|
|||
}
|
||||
}
|
||||
|
||||
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
|
||||
|
||||
if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
|
||||
{
|
||||
/* Check underrun flag of DAC channel 2 */
|
||||
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
|
||||
if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
|
||||
{
|
||||
/* Change DAC state to error state */
|
||||
hdac->State = HAL_DAC_STATE_ERROR;
|
||||
|
|
@ -821,7 +843,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
|
|||
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
|
||||
|
||||
/* Disable the selected DAC channel2 DMA request */
|
||||
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
|
||||
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
|
||||
|
||||
/* Error callback */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
|
|
@ -831,6 +853,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
|
|||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -851,7 +874,13 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
__IO uint32_t tmp = 0UL;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
|
@ -863,11 +892,13 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui
|
|||
{
|
||||
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
|
||||
}
|
||||
|
||||
|
||||
/* Set the DAC channel selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
|
||||
|
|
@ -968,20 +999,28 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
|||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
assert_param(hdac != NULL);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
if (Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
return hdac->Instance->DOR1;
|
||||
result = hdac->Instance->DOR1;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
return hdac->Instance->DOR2;
|
||||
result = hdac->Instance->DOR2;
|
||||
}
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -995,13 +1034,21 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmpreg1;
|
||||
uint32_t tmpreg2;
|
||||
uint32_t tickstart;
|
||||
uint32_t connectOnChip;
|
||||
|
||||
/* Check the DAC peripheral handle and channel configuration struct */
|
||||
if ((hdac == NULL) || (sConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
||||
|
|
@ -1040,18 +1087,22 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
HAL_Delay(1);
|
||||
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
|
||||
}
|
||||
|
||||
else /* Channel 2 */
|
||||
{
|
||||
/* SHSR2 can be written when BWST2 is cleared */
|
||||
|
|
@ -1060,19 +1111,23 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
|
||||
{
|
||||
/* Update error code */
|
||||
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
/* Change the DMA state */
|
||||
hdac->State = HAL_DAC_STATE_TIMEOUT;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
HAL_Delay(1U);
|
||||
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
|
||||
}
|
||||
|
||||
|
||||
/* HoldTime */
|
||||
MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
|
||||
(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
|
||||
|
|
@ -1103,6 +1158,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
/* Clear DAC_MCR_MODEx bits */
|
||||
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
|
||||
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
|
||||
|
||||
|
||||
if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
|
||||
{
|
||||
connectOnChip = 0x00000000UL;
|
||||
|
|
@ -1143,7 +1200,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
/* Write to DAC CR */
|
||||
hdac->Instance->CR = tmpreg1;
|
||||
/* Disable wave generation */
|
||||
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
|
||||
CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
|
||||
|
||||
/* Change DAC state */
|
||||
hdac->State = HAL_DAC_STATE_READY;
|
||||
|
|
@ -1152,7 +1209,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
__HAL_UNLOCK(hdac);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1181,7 +1238,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
* the configuration information for the specified DAC.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Return DAC handle state */
|
||||
return hdac->State;
|
||||
|
|
@ -1194,7 +1251,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
|
|||
* the configuration information for the specified DAC.
|
||||
* @retval DAC Error Code
|
||||
*/
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
return hdac->ErrorCode;
|
||||
}
|
||||
|
|
@ -1217,7 +1274,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
|||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User DAC Callback
|
||||
* To be used instead of the weak (surcharged) predefined callback
|
||||
* To be used instead of the weak (overridden) predefined callback
|
||||
* @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
|
||||
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
|
||||
* @param hdac DAC handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -1241,6 +1300,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
|
|
@ -1248,9 +1313,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
||||
if (hdac->State == HAL_DAC_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
|
|
@ -1267,6 +1329,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
|
|||
case HAL_DAC_CH1_UNDERRUN_CB_ID :
|
||||
hdac->DMAUnderrunCallbackCh1 = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DAC_CH2_COMPLETE_CB_ID :
|
||||
hdac->ConvCpltCallbackCh2 = pCallback;
|
||||
break;
|
||||
|
|
@ -1279,6 +1342,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
|
|||
case HAL_DAC_CH2_UNDERRUN_CB_ID :
|
||||
hdac->DMAUnderrunCallbackCh2 = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DAC_MSPINIT_CB_ID :
|
||||
hdac->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
|
@ -1319,14 +1383,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
|
|||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdac);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister a User DAC Callback
|
||||
* DAC Callback is redirected to the weak (surcharged) predefined callback
|
||||
* DAC Callback is redirected to the weak (overridden) predefined callback
|
||||
* @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
|
||||
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
|
||||
* @param hdac DAC handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -1347,8 +1411,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (hdac->State == HAL_DAC_STATE_READY)
|
||||
{
|
||||
|
|
@ -1366,6 +1433,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
|
|||
case HAL_DAC_CH1_UNDERRUN_CB_ID :
|
||||
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
|
||||
break;
|
||||
|
||||
case HAL_DAC_CH2_COMPLETE_CB_ID :
|
||||
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
|
||||
break;
|
||||
|
|
@ -1378,6 +1446,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
|
|||
case HAL_DAC_CH2_UNDERRUN_CB_ID :
|
||||
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
|
||||
break;
|
||||
|
||||
case HAL_DAC_MSPINIT_CB_ID :
|
||||
hdac->MspInitCallback = HAL_DAC_MspInit;
|
||||
break;
|
||||
|
|
@ -1389,10 +1458,12 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
|
|||
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
|
||||
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
|
||||
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
|
||||
|
||||
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
|
||||
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
|
||||
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
|
||||
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
|
||||
|
||||
hdac->MspInitCallback = HAL_DAC_MspInit;
|
||||
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
|
||||
break;
|
||||
|
|
@ -1430,8 +1501,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
|
|||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdac);
|
||||
return status;
|
||||
}
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
|
@ -1517,9 +1586,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
|
|||
#endif /* DAC1 || DAC2 */
|
||||
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -83,11 +82,13 @@ typedef struct
|
|||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
|
@ -126,7 +127,7 @@ typedef struct
|
|||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
|
||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
|
||||
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
|
||||
|
||||
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
|
||||
|
|
@ -136,9 +137,7 @@ typedef struct
|
|||
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
|
||||
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
|
||||
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
|
|
@ -151,10 +150,12 @@ typedef enum
|
|||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
|
|
@ -208,19 +209,19 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
#if defined(HRTIM1)
|
||||
#define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* HRTIM12 */
|
||||
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#if defined(TIM23)
|
||||
#define DAC_TRIGGER_T23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* TIM23 */
|
||||
#if defined(TIM24)
|
||||
#define DAC_TRIGGER_T24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* TIM24 */
|
||||
#if defined(DAC2)
|
||||
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
|
||||
#endif
|
||||
#endif /* DAC2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -240,7 +241,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -260,8 +263,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -270,8 +275,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -351,12 +358,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
|||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
|
|
@ -469,7 +478,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
|||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
|
|
@ -495,8 +504,9 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -505,8 +515,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -541,7 +551,4 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
|||
#endif
|
||||
|
||||
|
||||
#endif /*STM32H7xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
#endif /* STM32H7xx_HAL_DAC_H */
|
||||
|
|
|
|||
|
|
@ -7,6 +7,17 @@
|
|||
* functionalities of the DAC peripheral.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -14,6 +25,7 @@
|
|||
[..]
|
||||
*** Dual mode IO operation ***
|
||||
==============================
|
||||
[..]
|
||||
(+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
|
||||
for dual mode operation.
|
||||
If software trigger is selected, using HAL_DACEx_DualStart() will start
|
||||
|
|
@ -32,9 +44,9 @@
|
|||
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
|
||||
Channel 1 and Channel 2.
|
||||
|
||||
*** Signal generation operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
|
||||
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
|
||||
|
||||
|
|
@ -45,17 +57,6 @@
|
|||
at least one time after reset).
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -78,6 +79,16 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Delay for DAC minimum trimming time. */
|
||||
/* Note: minimum time needed between two calibration steps */
|
||||
/* The delay below is specified under conditions: */
|
||||
/* - DAC channel output buffer enabled */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* electrical characteristics, parameter "tTRIM"). */
|
||||
/* Unit: us */
|
||||
#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
|
@ -106,6 +117,7 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables DAC and starts conversion of both channels.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
|
|
@ -116,6 +128,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
|
|||
{
|
||||
uint32_t tmp_swtrig = 0UL;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdac);
|
||||
|
|
@ -157,6 +175,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
|
||||
|
|
@ -186,12 +210,18 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
|
|||
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment)
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
|
||||
const uint32_t *pData, uint32_t Length, uint32_t Alignment)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
uint32_t tmpreg = 0UL;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
|
|
@ -299,6 +329,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
|
|||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
|
||||
|
|
@ -343,6 +379,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the selected DAC channel wave generation.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
|
|
@ -369,6 +406,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
|
@ -419,6 +462,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
|
||||
{
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||
|
|
@ -443,6 +492,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual DAC channel.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
|
|
@ -463,6 +513,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align
|
|||
uint32_t data;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the DAC peripheral handle */
|
||||
if (hdac == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(Alignment));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
|
|
@ -552,6 +608,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
|||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Run the self calibration of one DAC channel.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
|
|
@ -569,9 +626,9 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
__IO uint32_t tmp;
|
||||
uint32_t trimmingvalue;
|
||||
uint32_t delta;
|
||||
__IO uint32_t wait_loop_index;
|
||||
|
||||
/* store/restore channel configuration structure purpose */
|
||||
uint32_t oldmodeconfiguration;
|
||||
|
|
@ -581,7 +638,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
|
|||
|
||||
/* Check the DAC handle allocation */
|
||||
/* Check if DAC running */
|
||||
if (hdac == NULL)
|
||||
if ((hdac == NULL) || (sConfig == NULL))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
|
@ -603,20 +660,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
|
|||
/* Set mode in MCR for calibration */
|
||||
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
|
||||
|
||||
/* Set DAC Channel1 DHR register to the middle value */
|
||||
tmp = (uint32_t)hdac->Instance;
|
||||
|
||||
if (Channel == DAC_CHANNEL_1)
|
||||
{
|
||||
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
|
||||
}
|
||||
|
||||
*(__IO uint32_t *) tmp = 0x0800UL;
|
||||
|
||||
/* Enable the selected DAC channel calibration */
|
||||
/* i.e. set DAC_CR_CENx bit */
|
||||
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
|
||||
|
|
@ -630,9 +673,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
|
|||
/* Set candidate trimming */
|
||||
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
||||
|
||||
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
|
||||
/* i.e. minimum time needed between two calibration steps */
|
||||
HAL_Delay(1);
|
||||
/* Wait minimum time needed between two calibration steps (OTRIM) */
|
||||
/* Wait loop initialization and execution */
|
||||
/* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
|
||||
/* 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
|
||||
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
|
||||
{
|
||||
|
|
@ -652,14 +701,24 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
|
|||
/* Set candidate trimming */
|
||||
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
||||
|
||||
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
|
||||
/* i.e. minimum time needed between two calibration steps */
|
||||
HAL_Delay(1U);
|
||||
/* Wait minimum time needed between two calibration steps (OTRIM) */
|
||||
/* Wait loop initialization and execution */
|
||||
/* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
|
||||
/* 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
||||
while (wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
|
||||
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
|
||||
{
|
||||
/* Trimming is actually one value more */
|
||||
trimmingvalue++;
|
||||
/* Check trimming value below maximum */
|
||||
if (trimmingvalue < 0x1FU)
|
||||
{
|
||||
/* Trimming is actually one value more */
|
||||
trimmingvalue++;
|
||||
}
|
||||
/* Set right trimming */
|
||||
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
|
||||
}
|
||||
|
|
@ -702,8 +761,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
|
|||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
|
||||
|
||||
/* Check the DAC handle allocation */
|
||||
if (hdac == NULL)
|
||||
/* Check the DAC handle and channel configuration struct allocation */
|
||||
if ((hdac == NULL) || (sConfig == NULL))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
|
@ -735,7 +794,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
|
|||
* @retval Trimming value : range: 0->31
|
||||
*
|
||||
*/
|
||||
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_DAC_CHANNEL(Channel));
|
||||
|
|
@ -762,13 +821,14 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the last data output value of the selected DAC channel.
|
||||
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DAC.
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
|
||||
{
|
||||
uint32_t tmp = 0UL;
|
||||
|
||||
|
|
@ -780,10 +840,10 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
|
|||
return tmp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -794,6 +854,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA conversion complete callback.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
|
|
@ -852,6 +913,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
|||
hdac->State = HAL_DAC_STATE_READY;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -867,5 +929,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -82,6 +81,7 @@ extern "C" {
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -141,7 +141,7 @@ extern "C" {
|
|||
((TRIGGER) == DAC_TRIGGER_T23_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T24_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
#endif
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
|
||||
|
||||
|
|
@ -206,11 +206,11 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
|
|||
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
|
||||
const uint32_t *pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
|
@ -230,7 +230,7 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
|||
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
|
||||
uint32_t NewTrimmingValue);
|
||||
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -268,6 +268,4 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
|||
}
|
||||
#endif
|
||||
|
||||
#endif /*STM32H7xx_HAL_DAC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
#endif /* STM32H7xx_HAL_DAC_EX_H */
|
||||
|
|
|
|||
|
|
@ -10,6 +10,17 @@
|
|||
* + Peripheral Control functions
|
||||
* + Peripheral State and Error functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -105,18 +116,6 @@
|
|||
(@) You can refer to the DCMI HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -135,8 +134,13 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
|
@ -1023,7 +1027,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
|
|||
|
||||
/**
|
||||
* @brief Unregister a DCMI Callback
|
||||
* DCMI callabck is redirected to the weak predefined callback
|
||||
* DCMI callback is redirected to the weak predefined callback
|
||||
* @param hdcmi DCMI handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -1107,6 +1111,10 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
|
|||
}
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1211,9 +1219,6 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* DCMI */
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
/**
|
||||
|
|
@ -1224,4 +1229,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -581,6 +580,13 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
|||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Defines DCMI Private Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
||||
|
|
@ -668,4 +674,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
|||
|
||||
#endif /* STM32H7xx_HAL_DCMI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -7,13 +7,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -67,7 +66,9 @@ typedef enum
|
|||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#define UNUSED(x) ((void)(x))
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(x) ((void)(x)) /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
|
|
@ -218,4 +219,4 @@ typedef enum
|
|||
|
||||
#endif /* STM32H7xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,17 @@
|
|||
* + Clock absence detector feature
|
||||
* + Break generation on analog watchdog or short-circuit event
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -251,17 +262,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -819,7 +819,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
|
|||
* @param Timeout Timeout value in milliseconds.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
|
@ -1109,7 +1109,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_
|
|||
* @param Timeout Timeout value in milliseconds.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
|
@ -1342,7 +1342,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
|
|||
* @param hdfsdm_channel DFSDM channel handle.
|
||||
* @retval Channel analog watchdog value.
|
||||
*/
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
|
||||
{
|
||||
return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
|
||||
}
|
||||
|
|
@ -1401,7 +1401,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf
|
|||
* @param hdfsdm_channel DFSDM channel handle.
|
||||
* @retval DFSDM channel state.
|
||||
*/
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
|
||||
{
|
||||
/* Return DFSDM channel handle state */
|
||||
return hdfsdm_channel->State;
|
||||
|
|
@ -2393,7 +2393,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd
|
|||
* @param Channel Corresponding channel of regular conversion.
|
||||
* @retval Regular conversion value
|
||||
*/
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
uint32_t *Channel)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
|
@ -2810,7 +2810,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h
|
|||
* @param Channel Corresponding channel of injected conversion.
|
||||
* @retval Injected conversion value
|
||||
*/
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
uint32_t *Channel)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
|
@ -2841,7 +2841,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
DFSDM_Filter_AwdParamTypeDef *awdParam)
|
||||
const DFSDM_Filter_AwdParamTypeDef *awdParam)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -2998,7 +2998,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
|
|||
* @retval Extreme detector maximum value
|
||||
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
|
||||
*/
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
uint32_t *Channel)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
|
@ -3029,7 +3029,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
|
|||
* @retval Extreme detector minimum value
|
||||
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
|
||||
*/
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
uint32_t *Channel)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
|
@ -3059,7 +3059,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
|
|||
* @retval Conversion time value
|
||||
* @note To get time in second, this value has to be divided by DFSDM clock frequency.
|
||||
*/
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t value;
|
||||
|
|
@ -3413,7 +3413,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
|
|||
* @param hdfsdm_filter DFSDM filter handle.
|
||||
* @retval DFSDM filter state.
|
||||
*/
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
||||
{
|
||||
/* Return DFSDM filter handle state */
|
||||
return hdfsdm_filter->State;
|
||||
|
|
@ -3424,7 +3424,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe
|
|||
* @param hdfsdm_filter DFSDM filter handle.
|
||||
* @retval DFSDM filter error code.
|
||||
*/
|
||||
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
||||
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
||||
{
|
||||
return hdfsdm_filter->ErrorCode;
|
||||
}
|
||||
|
|
@ -3795,4 +3795,3 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -401,12 +400,12 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
|
|||
#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
|
||||
#if (STM32H7_DEV_ID == 0x480UL)
|
||||
#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
|
||||
DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
|
||||
DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
|
||||
#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
|
||||
DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
|
||||
#elif (STM32H7_DEV_ID == 0x483UL)
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM23_TRGO (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | \
|
||||
DFSDM_FLTCR1_JEXTSEL_0)
|
||||
DFSDM_FLTCR1_JEXTSEL_0)
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM24_TRGO (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2 )
|
||||
#endif /* STM32H7_DEV_ID == 0x480UL */
|
||||
/**
|
||||
|
|
@ -600,11 +599,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
|
|||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
|
||||
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
|
||||
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
|
|
@ -616,7 +615,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
|||
* @{
|
||||
*/
|
||||
/* Channel state function *****************************************************/
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -677,16 +676,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
|
|||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
DFSDM_Filter_AwdParamTypeDef *awdParam);
|
||||
const DFSDM_Filter_AwdParamTypeDef *awdParam);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
|
|
@ -707,8 +706,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
|||
* @{
|
||||
*/
|
||||
/* Filter state functions *****************************************************/
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -870,4 +869,3 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
|
|||
|
||||
#endif /* STM32H7xx_HAL_DFSDM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -10,13 +10,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -95,7 +94,7 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeD
|
|||
* @param PulsesValue Value of pulses to be skipped.
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
|
||||
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
|
|
@ -132,4 +131,3 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -52,7 +51,7 @@ extern "C" {
|
|||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);
|
||||
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
|
||||
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -90,4 +89,3 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD
|
|||
|
||||
#endif /* STM32H7xx_HAL_DFSDM_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -8,6 +8,17 @@
|
|||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -78,18 +89,6 @@
|
|||
(@) You can refer to the DMA HAL driver header file for more useful macros.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -107,6 +106,9 @@
|
|||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @addtogroup DMA_Private_Types
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISR; /*!< DMA interrupt status register */
|
||||
|
|
@ -119,6 +121,9 @@ typedef struct
|
|||
__IO uint32_t ISR; /*!< BDMA interrupt status register */
|
||||
__IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */
|
||||
} BDMA_Base_Registers;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
|
@ -244,12 +249,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|||
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
|
||||
}
|
||||
|
||||
/* Allocate lock resource */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Allocate lock resource */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
|
|
@ -358,12 +363,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|||
assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
|
||||
}
|
||||
|
||||
/* Allocate lock resource */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Allocate lock resource */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Get the CR register value */
|
||||
registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
|
||||
|
||||
|
|
@ -652,12 +657,12 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
|
|||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
|
@ -748,12 +753,12 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
|
|||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Set the error code to busy */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
|
@ -835,12 +840,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -873,11 +878,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -945,12 +950,12 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if(hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
|
|
@ -1173,10 +1178,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
|
|||
(*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
|
||||
}
|
||||
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
|
||||
{
|
||||
|
|
@ -1324,12 +1329,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
/* Clear all interrupt flags at correct offset within the register */
|
||||
regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
|
|
@ -1366,11 +1371,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
/* Disable the transfer complete interrupt */
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
}
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
|
|
@ -1401,9 +1406,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
}
|
||||
while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
|
||||
{
|
||||
/* Change the DMA state to error if DMA disable fails */
|
||||
|
|
@ -1414,6 +1416,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
/* Change the DMA state to Ready if DMA disable success */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
}
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
|
|
@ -1509,11 +1514,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
/* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
}
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
|
|
@ -1537,12 +1542,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
|
|
@ -1613,6 +1618,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
|
|||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -2054,4 +2060,3 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -1229,6 +1228,14 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Types DMA Private Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @brief DMA private macros
|
||||
|
|
@ -1324,4 +1331,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
|||
|
||||
#endif /* STM32H7xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -10,6 +10,17 @@
|
|||
* + Peripheral Control functions
|
||||
* + Peripheral State and Errors functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -107,7 +118,7 @@
|
|||
and a pointer to the user callback function.
|
||||
|
||||
(#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
weak (overridden) function.
|
||||
@ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
|
|
@ -119,16 +130,16 @@
|
|||
(+) MspDeInitCallback : DMA2D MspDeInit.
|
||||
|
||||
(#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
|
||||
all callbacks are reset to the corresponding legacy weak (overridden) functions:
|
||||
examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
|
||||
Exception done for MspInit and MspDeInit callbacks that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
|
||||
reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init
|
||||
and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
|
||||
If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
||||
Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
|
||||
as weak (surcharged) functions. They must be defined by the user to be resorted to.
|
||||
as weak (overridden) functions. They must be defined by the user to be resorted to.
|
||||
|
||||
Callbacks can be registered/unregistered in READY state only.
|
||||
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
|
||||
|
|
@ -140,24 +151,13 @@
|
|||
|
||||
When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak (overridden) callbacks are used.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA2D HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -431,7 +431,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
|
|||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User DMA2D Callback
|
||||
* To be used instead of the weak (surcharged) predefined callback
|
||||
* To be used instead of the weak (overridden) predefined callback
|
||||
* @param hdma2d DMA2D handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -530,7 +530,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM
|
|||
|
||||
/**
|
||||
* @brief Unregister a DMA2D Callback
|
||||
* DMA2D Callback is redirected to the weak (surcharged) predefined callback
|
||||
* DMA2D Callback is redirected to the weak (overridden) predefined callback
|
||||
* @param hdma2d DMA2D handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -571,11 +571,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
|
|||
break;
|
||||
|
||||
case HAL_DMA2D_MSPINIT_CB_ID :
|
||||
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
|
||||
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
|
||||
break;
|
||||
|
||||
case HAL_DMA2D_MSPDEINIT_CB_ID :
|
||||
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
|
||||
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -591,11 +591,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA2D_MSPINIT_CB_ID :
|
||||
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
|
||||
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
|
||||
break;
|
||||
|
||||
case HAL_DMA2D_MSPDEINIT_CB_ID :
|
||||
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
|
||||
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -2183,5 +2183,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
|
|||
*/
|
||||
#endif /* DMA2D */
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -342,15 +341,6 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
|
||||
for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DMA2D common Callback ID enumeration definition
|
||||
|
|
@ -723,6 +713,3 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_DMA2D_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -37,13 +37,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -290,18 +289,7 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
|
|||
{
|
||||
/* Enable Common interrupts*/
|
||||
MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
|
||||
|
||||
/* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
|
||||
* If it's not enabled, then this interrupt can trigger spuriously from memory bus
|
||||
* stalls that the DMA engine encounters, and this creates random DMA failures.
|
||||
* Reference forum thread here:
|
||||
* https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
|
||||
* also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
|
||||
*/
|
||||
if(((DMA_Stream_TypeDef *)hdma->Instance)->FCR & DMA_SxFCR_DMDIS)
|
||||
{
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
|
||||
}
|
||||
((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
|
||||
|
||||
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
||||
{
|
||||
|
|
@ -722,4 +710,3 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -309,4 +308,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
|||
|
||||
#endif /* STM32H7xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -9,6 +9,17 @@
|
|||
* + IO operation functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State and Errors functions
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -119,7 +130,7 @@
|
|||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
|
||||
reset to the legacy weak (overridden) functions in the HAL_DSI_Init()
|
||||
and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
|
@ -140,17 +151,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -200,12 +200,14 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32
|
|||
uint32_t Data1);
|
||||
|
||||
static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
|
||||
uint32_t ChannelID,
|
||||
uint32_t Mode,
|
||||
uint32_t Param1,
|
||||
uint32_t Param2);
|
||||
|
||||
uint32_t ChannelID,
|
||||
uint32_t Mode,
|
||||
uint32_t Param1,
|
||||
uint32_t Param2);
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Functions DSI Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Generic DSI packet header configuration
|
||||
* @param DSIx Pointer to DSI register base
|
||||
|
|
@ -255,10 +257,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
|
|||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for Command FIFO Empty */
|
||||
while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
|
||||
while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
|
@ -271,6 +273,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DSI_Exported_Functions
|
||||
* @{
|
||||
|
|
@ -365,11 +371,17 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
|
|||
|
||||
/* Set the PLL division factors */
|
||||
hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
|
||||
hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
|
||||
hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
|
||||
((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
|
||||
((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
|
||||
|
||||
/* Enable the DSI PLL */
|
||||
__HAL_DSI_PLL_ENABLE(hdsi);
|
||||
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
|
|
@ -383,24 +395,53 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
|
|||
}
|
||||
}
|
||||
|
||||
__HAL_DSI_ENABLE(hdsi);
|
||||
|
||||
/************************ Set the DSI clock parameters ************************/
|
||||
/* Set the TX escape clock division factor */
|
||||
hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
|
||||
hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
|
||||
|
||||
/*************************** Set the PHY parameters ***************************/
|
||||
|
||||
/* D-PHY clock and digital enable*/
|
||||
hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
|
||||
hdsi->Instance->PCTLR |= DSI_PCTLR_DEN;
|
||||
|
||||
hdsi->Instance->PCTLR |= DSI_PCTLR_CKE;
|
||||
|
||||
/* Clock lane configuration */
|
||||
hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
|
||||
hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
|
||||
|
||||
/* Configure the number of active data lanes */
|
||||
hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
|
||||
hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
|
||||
|
||||
/************************ Set the DSI clock parameters ************************/
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC))
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
/* Set the TX escape clock division factor */
|
||||
hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
|
||||
hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \
|
||||
DSI_PSR_PSS1 | DSI_PSR_PSSC))
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
|
||||
/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
|
||||
|
|
@ -419,7 +460,13 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
|
|||
hdsi->Instance->IER[1U] = 0U;
|
||||
hdsi->ErrorMsk = 0U;
|
||||
|
||||
/* Initialise the error code */
|
||||
__HAL_DSI_DISABLE(hdsi);
|
||||
|
||||
/* Clock lane configuration */
|
||||
hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
|
||||
hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
|
||||
|
||||
/* Initialize the error code */
|
||||
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
|
||||
|
||||
/* Initialize the DSI state*/
|
||||
|
|
@ -473,7 +520,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
|
|||
HAL_DSI_MspDeInit(hdsi);
|
||||
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
|
||||
|
||||
/* Initialise the error code */
|
||||
/* Initialize the error code */
|
||||
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
|
||||
|
||||
/* Initialize the DSI state*/
|
||||
|
|
@ -698,7 +745,7 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call
|
|||
|
||||
/**
|
||||
* @brief Unregister a DSI Callback
|
||||
* DSI callabck is redirected to the weak predefined callback
|
||||
* DSI callback is redirected to the weak predefined callback
|
||||
* @param hdsi dsi handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -733,11 +780,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca
|
|||
break;
|
||||
|
||||
case HAL_DSI_MSPINIT_CB_ID :
|
||||
hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
|
||||
hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
|
||||
break;
|
||||
|
||||
case HAL_DSI_MSPDEINIT_CB_ID :
|
||||
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
|
||||
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -753,11 +800,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca
|
|||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DSI_MSPINIT_CB_ID :
|
||||
hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
|
||||
hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
|
||||
break;
|
||||
|
||||
case HAL_DSI_MSPDEINIT_CB_ID :
|
||||
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
|
||||
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
|
||||
break;
|
||||
|
||||
default :
|
||||
|
|
@ -808,7 +855,8 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca
|
|||
*/
|
||||
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
|
||||
{
|
||||
uint32_t ErrorStatus0, ErrorStatus1;
|
||||
uint32_t ErrorStatus0;
|
||||
uint32_t ErrorStatus1;
|
||||
|
||||
/* Tearing Effect Interrupt management ***************************************/
|
||||
if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
|
||||
|
|
@ -1365,7 +1413,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
|
|||
High-Speed transmission.
|
||||
To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
|
||||
to Low-Power and from Low-Power to High-Speed.
|
||||
This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
|
||||
This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
|
||||
Register (DSI_CLTCR).
|
||||
But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
|
||||
|
||||
Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
|
||||
|
|
@ -1587,7 +1636,7 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hdsi);
|
||||
|
||||
status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
|
||||
status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
|
@ -1614,12 +1663,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
|
|||
uint32_t Mode,
|
||||
uint32_t NbParams,
|
||||
uint32_t Param1,
|
||||
uint8_t *ParametersTable)
|
||||
const uint8_t *ParametersTable)
|
||||
{
|
||||
uint32_t uicounter, nbBytes, count;
|
||||
uint32_t uicounter;
|
||||
uint32_t nbBytes;
|
||||
uint32_t count;
|
||||
uint32_t tickstart;
|
||||
uint32_t fifoword;
|
||||
uint8_t *pparams = ParametersTable;
|
||||
const uint8_t *pparams = ParametersTable;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdsi);
|
||||
|
|
@ -1721,7 +1772,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
|
|||
{
|
||||
/* set max return packet size */
|
||||
if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
|
||||
(((datasize) >> 8U) & 0xFFU)) != HAL_OK)
|
||||
(((datasize) >> 8U) & 0xFFU)) != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
|
@ -1782,6 +1833,21 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
|
|||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */
|
||||
/* issued to the panel and the read data is not captured by the DSI Host */
|
||||
/* which returns Packet Size Error. */
|
||||
/* Need to ensure that the Read command has finished before checking PSE */
|
||||
if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
|
||||
{
|
||||
if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
|
|
@ -1804,6 +1870,95 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hdsi);
|
||||
|
||||
/* Verify the initial status of the DSI Host */
|
||||
|
||||
/* Verify that the clock lane and the digital section of the D-PHY are enabled */
|
||||
if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that the D-PHY PLL and the reference bias are enabled */
|
||||
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
/* Verify that there are no ULPS exit or request on data lanes */
|
||||
if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that there are no Transmission trigger */
|
||||
if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Verify that D-PHY PLL is locked */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U))
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Verify that all active lanes are in Stop state */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* ULPS Request on Data Lanes */
|
||||
hdsi->Instance->PUCR |= DSI_PUCR_URDL;
|
||||
|
||||
|
|
@ -1867,6 +2022,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hdsi);
|
||||
|
||||
/* Verify that all active lanes are in ULPM */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Turn on the DSI PLL */
|
||||
__HAL_DSI_PLL_ENABLE(hdsi);
|
||||
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for the lock of the PLL */
|
||||
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Exit ULPS on Data Lanes */
|
||||
hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
|
||||
|
||||
|
|
@ -1916,6 +2123,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
|
|||
/* De-assert the ULPM requests and the ULPM exit bits */
|
||||
hdsi->Instance->PUCR = 0U;
|
||||
|
||||
/* Verify that D-PHY PLL is enabled */
|
||||
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that all active lanes are in Stop state */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that D-PHY PLL is locked */
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for the lock of the PLL */
|
||||
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
|
|
@ -1936,6 +2198,96 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hdsi);
|
||||
|
||||
/* Verify the initial status of the DSI Host */
|
||||
|
||||
/* Verify that the clock lane and the digital section of the D-PHY are enabled */
|
||||
if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that the D-PHY PLL and the reference bias are enabled */
|
||||
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
/* Verify that there are no ULPS exit or request on both data and clock lanes */
|
||||
if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that there are no Transmission trigger */
|
||||
if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Verify that D-PHY PLL is locked */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U))
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Verify that all active lanes are in Stop state */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \
|
||||
DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clock lane configuration: no more HS request */
|
||||
hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
|
||||
|
||||
|
|
@ -1948,7 +2300,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
|
|||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until all active lanes exit ULPM */
|
||||
/* Wait until all active lanes enter ULPM */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
|
||||
|
|
@ -2008,9 +2360,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
|
|||
/* Process locked */
|
||||
__HAL_LOCK(hdsi);
|
||||
|
||||
/* Verify that all active lanes are in ULPM */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \
|
||||
DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \
|
||||
DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Turn on the DSI PLL */
|
||||
__HAL_DSI_PLL_ENABLE(hdsi);
|
||||
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
|
|
@ -2077,12 +2464,68 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
|
|||
/* De-assert the ULPM requests and the ULPM exit bits */
|
||||
hdsi->Instance->PUCR = 0U;
|
||||
|
||||
/* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
|
||||
/* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
|
||||
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PHY);
|
||||
|
||||
/* Restore clock lane configuration to HS */
|
||||
hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
|
||||
|
||||
/* Verify that D-PHY PLL is enabled */
|
||||
if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that all active lanes are in Stop state */
|
||||
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
|
||||
{
|
||||
if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \
|
||||
DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1))
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Verify that D-PHY PLL is locked */
|
||||
/* Requires min of 400us delay before reading the PLLLS flag */
|
||||
/* 1ms delay is inserted that is the minimum HAL delay granularity */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for the lock of the PLL */
|
||||
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdsi);
|
||||
|
||||
|
|
@ -2691,7 +3134,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
|
|||
* the configuration information for the DSI.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi)
|
||||
{
|
||||
return hdsi->State;
|
||||
}
|
||||
|
|
@ -2702,7 +3145,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
|
|||
* the configuration information for the DSI.
|
||||
* @retval DSI Error Code
|
||||
*/
|
||||
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
|
||||
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi)
|
||||
{
|
||||
/* Get the error code */
|
||||
return hdsi->ErrorCode;
|
||||
|
|
@ -2727,5 +3170,3 @@ uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -40,6 +39,9 @@ extern "C" {
|
|||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DSI_Exported_Types DSI Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DSI Init Structure definition
|
||||
*/
|
||||
|
|
@ -61,14 +63,14 @@ typedef struct
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLNDIV; /*!< PLL Loop Division Factor
|
||||
This parameter must be a value between 10 and 125 */
|
||||
uint32_t PLLNDIV; /*!< PLL Loop Division Factor
|
||||
This parameter must be a value between 10 and 125 */
|
||||
|
||||
uint32_t PLLIDF; /*!< PLL Input Division Factor
|
||||
This parameter can be any value of @ref DSI_PLL_IDF */
|
||||
uint32_t PLLIDF; /*!< PLL Input Division Factor
|
||||
This parameter can be any value of @ref DSI_PLL_IDF */
|
||||
|
||||
uint32_t PLLODF; /*!< PLL Output Division Factor
|
||||
This parameter can be any value of @ref DSI_PLL_ODF */
|
||||
uint32_t PLLODF; /*!< PLL Output Division Factor
|
||||
This parameter can be any value of @ref DSI_PLL_ODF */
|
||||
|
||||
} DSI_PLLInitTypeDef;
|
||||
|
||||
|
|
@ -346,6 +348,9 @@ typedef enum
|
|||
typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
|
||||
|
||||
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DSI_Exported_Constants DSI Exported Constants
|
||||
|
|
@ -700,8 +705,8 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
|
||||
#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
|
||||
#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
|
||||
#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
|
||||
DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
|
||||
#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
|
||||
DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
|
||||
DSI_FLOW_CONTROL_EOTP_TX)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -841,18 +846,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @{
|
||||
*/
|
||||
#define HAL_DSI_ERROR_NONE 0U
|
||||
#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
|
||||
#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
|
||||
#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
|
||||
#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
|
||||
#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
|
||||
#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
|
||||
#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
|
||||
#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
|
||||
#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
|
||||
#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
|
||||
#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */
|
||||
#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
|
||||
#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */
|
||||
#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */
|
||||
#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
|
||||
#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
|
||||
#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
|
||||
#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
|
||||
#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
|
||||
#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
|
||||
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
|
||||
#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
|
||||
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -912,6 +917,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -955,11 +961,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DSI_DISABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
|
||||
/* Delay after an DSI Host disabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
|
||||
UNUSED(tmpreg); \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
|
||||
/* Delay after an DSI Host disabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
|
|
@ -968,11 +974,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI warpper enabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI wrapper enabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
|
|
@ -981,11 +987,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI warpper disabling*/ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
/* Delay after an DSI wrapper disabling*/ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
|
|
@ -994,11 +1000,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
/* Delay after an DSI PLL enabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
UNUSED(tmpreg); \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
/* Delay after an DSI PLL enabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
|
|
@ -1007,11 +1013,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
/* Delay after an DSI PLL disabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
UNUSED(tmpreg); \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
/* Delay after an DSI PLL disabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
|
|
@ -1033,11 +1039,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
|
||||
/* Delay after an DSI regulator disabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
|
||||
/* Delay after an DSI regulator disabling */ \
|
||||
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
|
|
@ -1121,23 +1127,41 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to
|
|||
/** @defgroup DSI_Exported_Functions DSI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup DSI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
|
||||
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
|
||||
|
||||
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
|
||||
|
||||
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
|
||||
pDSI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DSI_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
|
||||
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DSI_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
|
||||
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
|
||||
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
|
||||
|
|
@ -1160,7 +1184,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
|
|||
uint32_t Mode,
|
||||
uint32_t NbParams,
|
||||
uint32_t Param1,
|
||||
uint8_t *ParametersTable);
|
||||
const uint8_t *ParametersTable);
|
||||
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
|
||||
uint32_t ChannelNbr,
|
||||
uint8_t *Array,
|
||||
|
|
@ -1190,40 +1214,28 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional
|
|||
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
|
||||
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
|
||||
|
||||
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
|
||||
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DSI_Group4 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
|
||||
HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Types DSI Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Defines DSI Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Variables DSI Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Constants DSI Private Constants
|
||||
* @{
|
||||
|
|
@ -1249,45 +1261,73 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
|||
((ODF) == DSI_PLL_OUT_DIV2) || \
|
||||
((ODF) == DSI_PLL_OUT_DIV4) || \
|
||||
((ODF) == DSI_PLL_OUT_DIV8))
|
||||
#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
|
||||
#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
|
||||
#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
|
||||
|| ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
|
||||
#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
|
||||
|| ((NumberOfLanes) == DSI_TWO_DATA_LANES))
|
||||
#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
|
||||
#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
|
||||
#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
|
||||
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
|
||||
#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
|
||||
|| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
|
||||
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
|
||||
|| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
|
||||
#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
|
||||
|| ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
|
||||
|| ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
|
||||
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
|
||||
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
|
||||
((VideoModeType) == DSI_VID_MODE_BURST))
|
||||
#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
|
||||
#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\
|
||||
|| ((ColorMode) == DSI_COLOR_MODE_EIGHT))
|
||||
#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
|
||||
#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
|
||||
#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
|
||||
|| ((LPCommand) == DSI_LP_COMMAND_ENABLE))
|
||||
#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
|
||||
#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
|
||||
#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
|
||||
#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\
|
||||
|| ((LPVActive) == DSI_LP_VACT_ENABLE))
|
||||
#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
|
||||
#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
|
||||
#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
|
||||
#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
|
||||
#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
|
||||
|| ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
|
||||
#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
|
||||
|| ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
|
||||
#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
|
||||
#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
|
||||
#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
|
||||
#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
|
||||
#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
|
||||
#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
|
||||
#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
|
||||
#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
|
||||
#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
|
||||
#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
|
||||
#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
|
||||
#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
|
||||
#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
|
||||
#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
|
||||
#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
|
||||
#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
|
||||
#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
|
||||
#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
|
||||
#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\
|
||||
|| ((TEPolarity) == DSI_TE_FALLING_EDGE))
|
||||
#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\
|
||||
|| ((AutomaticRefresh) == DSI_AR_ENABLE))
|
||||
#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\
|
||||
|| ((VSPolarity) == DSI_VSYNC_RISING))
|
||||
#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
|
||||
|| ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
|
||||
#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
|
||||
|| ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
|
||||
#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
|
||||
|| ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
|
||||
#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
|
||||
|| ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
|
||||
#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
|
||||
|| ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
|
||||
#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
|
||||
|| ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
|
||||
#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
|
||||
|| ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
|
||||
#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
|
||||
|| ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
|
||||
#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\
|
||||
|| ((LP_GLW) == DSI_LP_GLW_ENABLE))
|
||||
#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
|
||||
|| ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
|
||||
#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
|
||||
|| ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
|
||||
#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
|
||||
|| ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
|
||||
#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\
|
||||
|| ((LP_DLW) == DSI_LP_DLW_ENABLE))
|
||||
#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
|
||||
|| ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
|
||||
#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
|
||||
((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
|
||||
((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
|
||||
|
|
@ -1299,10 +1339,14 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
|||
((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
|
||||
((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
|
||||
((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
|
||||
#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
|
||||
#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
|
||||
((CommDelay) == DSI_SLEW_RATE_LPTX) || \
|
||||
((CommDelay) == DSI_HS_DELAY))
|
||||
#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
|
||||
#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
|
||||
#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
|
||||
#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\
|
||||
|| ((CustomLane) == DSI_INVERT_HS_SIGNAL))
|
||||
#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \
|
||||
((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
|
||||
#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
|
||||
((Timing) == DSI_TLPX_CLK ) || \
|
||||
((Timing) == DSI_THS_EXIT ) || \
|
||||
|
|
@ -1317,24 +1361,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DSI_Private_Functions DSI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1349,5 +1375,3 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_DSI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -11,6 +11,17 @@
|
|||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### DTS Peripheral features #####
|
||||
|
|
@ -27,17 +38,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -76,6 +76,12 @@
|
|||
*/
|
||||
#define TS_TIMEOUT_MS (5UL)
|
||||
|
||||
/* @brief DTS factory temperatures
|
||||
* @note Unit: degree Celsius
|
||||
*/
|
||||
#define DTS_FACTORY_TEMPERATURE1 (30UL)
|
||||
#define DTS_FACTORY_TEMPERATURE2 (130UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -83,9 +89,6 @@
|
|||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
static void DTS_ResetCallback(DTS_HandleTypeDef *hdts);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DTS_Exported_Functions DTS Exported Functions
|
||||
|
|
@ -131,8 +134,13 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
|
|||
if (hdts->State == HAL_DTS_STATE_RESET)
|
||||
{
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
/* Reset interrupt callbacks to legacy weak callbacks */
|
||||
DTS_ResetCallback(hdts);
|
||||
/* Reset the DTS callback to the legacy weak callbacks */
|
||||
hdts->EndCallback = HAL_DTS_EndCallback; /* End measure Callback */
|
||||
hdts->LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */
|
||||
hdts->HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */
|
||||
hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */
|
||||
hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */
|
||||
hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */
|
||||
|
||||
if (hdts->MspInitCallback == NULL)
|
||||
{
|
||||
|
|
@ -277,6 +285,180 @@ __weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
|
|||
*/
|
||||
}
|
||||
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a user DTS callback to be used instead of the weak predefined callback.
|
||||
* @param hdts DTS handle.
|
||||
* @param CallbackID ID of the callback to be registered.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID.
|
||||
* @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID.
|
||||
* @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID.
|
||||
* @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID.
|
||||
* @param pCallback pointer to the callback function.
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID,
|
||||
pDTS_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check parameters */
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (hdts->State == HAL_DTS_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DTS_MEAS_COMPLETE_CB_ID :
|
||||
hdts->EndCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID :
|
||||
hdts->AsyncEndCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_LOW_THRESHOLD_CB_ID :
|
||||
hdts->LowCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID :
|
||||
hdts->AsyncLowCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_HIGH_THRESHOLD_CB_ID :
|
||||
hdts->HighCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID :
|
||||
hdts->AsyncHighCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_MSPINIT_CB_ID :
|
||||
hdts->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_MSPDEINIT_CB_ID :
|
||||
hdts->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (hdts->State == HAL_DTS_STATE_RESET)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DTS_MSPINIT_CB_ID :
|
||||
hdts->MspInitCallback = pCallback;
|
||||
break;
|
||||
case HAL_DTS_MSPDEINIT_CB_ID :
|
||||
hdts->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
default :
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister a user DTS callback.
|
||||
* DTS callback is redirected to the weak predefined callback.
|
||||
* @param hdts DTS handle.
|
||||
* @param CallbackID ID of the callback to be unregistered.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID.
|
||||
* @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID.
|
||||
* @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID.
|
||||
* @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID.
|
||||
* @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID.
|
||||
* @retval HAL status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (hdts->State == HAL_DTS_STATE_READY)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DTS_MEAS_COMPLETE_CB_ID :
|
||||
hdts->EndCallback = HAL_DTS_EndCallback;
|
||||
break;
|
||||
case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID :
|
||||
hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback;
|
||||
break;
|
||||
case HAL_DTS_LOW_THRESHOLD_CB_ID :
|
||||
hdts->LowCallback = HAL_DTS_LowCallback;
|
||||
break;
|
||||
case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID :
|
||||
hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback;
|
||||
break;
|
||||
case HAL_DTS_HIGH_THRESHOLD_CB_ID :
|
||||
hdts->HighCallback = HAL_DTS_HighCallback;
|
||||
break;
|
||||
case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID :
|
||||
hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback;
|
||||
break;
|
||||
case HAL_DTS_MSPINIT_CB_ID :
|
||||
hdts->MspInitCallback = HAL_DTS_MspInit;
|
||||
break;
|
||||
case HAL_DTS_MSPDEINIT_CB_ID :
|
||||
hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (hdts->State == HAL_DTS_STATE_RESET)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DTS_MSPINIT_CB_ID :
|
||||
hdts->MspInitCallback = HAL_DTS_MspInit;
|
||||
break;
|
||||
case HAL_DTS_MSPDEINIT_CB_ID :
|
||||
hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
|
||||
break;
|
||||
default :
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -538,11 +720,11 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe
|
|||
|
||||
if (t0_temp == 0UL)
|
||||
{
|
||||
t0_temp = 30UL; /* 30 deg C */
|
||||
t0_temp = DTS_FACTORY_TEMPERATURE1; /* 30 deg C */
|
||||
}
|
||||
else if (t0_temp == 1UL)
|
||||
{
|
||||
t0_temp = 110UL; /* 110 deg C */
|
||||
t0_temp = DTS_FACTORY_TEMPERATURE2; /* 130 deg C */
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -785,33 +967,6 @@ HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DTS_Private_Functions DTS Private Functions
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Reset interrupt callbacks to the legacy weak callbacks.
|
||||
* @param hdts pointer to a DTS_HandleTypeDef structure that contains
|
||||
* the configuration information for DTS module.
|
||||
* @retval None
|
||||
*/
|
||||
static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
|
||||
{
|
||||
/* Reset the DTS callback to the legacy weak callbacks */
|
||||
hdts->DTS_EndCallback = HAL_DTS_EndCallback; /* End measure Callback */
|
||||
hdts->DTS_LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */
|
||||
hdts->DTS_HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */
|
||||
hdts->DTS_AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */
|
||||
hdts->DTS_AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */
|
||||
hdts->DTS_AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */
|
||||
}
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -824,4 +979,3 @@ static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -25,14 +24,15 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(DTS)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DTS)
|
||||
/** @addtogroup DTS
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -96,15 +96,37 @@ typedef struct
|
|||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp Init Callback */
|
||||
void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp DeInit Callback */
|
||||
void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */
|
||||
void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */
|
||||
void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */
|
||||
void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */
|
||||
void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */
|
||||
void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */
|
||||
void (* EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */
|
||||
void (* LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */
|
||||
void (* HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */
|
||||
void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */
|
||||
void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */
|
||||
void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
} DTS_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief DTS callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DTS_MEAS_COMPLETE_CB_ID = 0x00U, /*!< Measure complete callback ID */
|
||||
HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID = 0x01U, /*!< Asynchronous measure complete callback ID */
|
||||
HAL_DTS_LOW_THRESHOLD_CB_ID = 0x02U, /*!< Low threshold detection callback ID */
|
||||
HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID = 0x03U, /*!< Asynchronous low threshold detection callback ID */
|
||||
HAL_DTS_HIGH_THRESHOLD_CB_ID = 0x04U, /*!< High threshold detection callback ID */
|
||||
HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U, /*!< Asynchronous high threshold detection callback ID */
|
||||
HAL_DTS_MSPINIT_CB_ID = 0x06U, /*!< MSP init callback ID */
|
||||
HAL_DTS_MSPDEINIT_CB_ID = 0x07U /*!< MSP de-init callback ID */
|
||||
} HAL_DTS_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DTS callback pointers definition
|
||||
*/
|
||||
typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -213,7 +235,15 @@ typedef struct
|
|||
* @param __HANDLE__ DTS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DTS_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DTS sensor
|
||||
|
|
@ -372,6 +402,13 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
|
|||
HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
|
||||
void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
|
||||
#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID,
|
||||
pDTS_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts,
|
||||
HAL_DTS_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -397,6 +434,9 @@ void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
|
@ -436,7 +476,7 @@ void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
|
|||
|
||||
#define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL)
|
||||
|
||||
#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL)))
|
||||
#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL)
|
||||
|
||||
#define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \
|
||||
((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \
|
||||
|
|
@ -480,4 +520,3 @@ void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
|
|||
|
||||
#endif /* __STM32H7xx_HAL_DTS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -7,13 +7,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -34,7 +33,6 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
|
||||
|
|
@ -58,6 +56,9 @@
|
|||
|
||||
#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
|
||||
ETH_MACVIR_VLP | ETH_MACVIR_VLC)
|
||||
|
||||
#define ETH_MAC_L4_SRSP_MASK 0x0000FFFFU
|
||||
#define ETH_MAC_L4_DSTP_MASK 0xFFFF0000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -71,7 +72,7 @@
|
|||
|
||||
/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
|
|
@ -92,6 +93,7 @@
|
|||
* the configuration information for ETHERNET module
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
|
||||
|
|
@ -133,25 +135,35 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
|
|||
* that contains L4 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
{
|
||||
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
|
||||
|
||||
if(pL4FilterConfig == NULL)
|
||||
if (pL4FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write configuration to (MACL3L4C0R + filter )register */
|
||||
MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
if (Filter == ETH_L4_FILTER_0)
|
||||
{
|
||||
/* Write configuration to MACL3L4C0R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
|
||||
configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
|
||||
/* Write configuration to MACL4A0R register */
|
||||
WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
|
||||
|
||||
/* Write configuration to (MACL4A0R + filter )register */
|
||||
MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
|
||||
(pL4FilterConfig->DestinationPort << 16)));
|
||||
}
|
||||
else /* Filter == ETH_L4_FILTER_1 */
|
||||
{
|
||||
/* Write configuration to MACL3L4C1R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
|
||||
/* Write configuration to MACL4A1R register */
|
||||
WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
|
||||
}
|
||||
|
||||
/* Enable L4 filter */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
|
|
@ -172,21 +184,40 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
* that contains L4 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
{
|
||||
if(pL4FilterConfig == NULL)
|
||||
if (pL4FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get configuration to (MACL3L4C0R + filter )register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
if (Filter == ETH_L4_FILTER_0)
|
||||
{
|
||||
/* Get configuration from MACL3L4C0R register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
|
||||
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
|
||||
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
|
||||
/* Get configuration to (MACL3L4C0R + filter )register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
|
||||
/* Get configuration from MACL4A0R register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
|
||||
}
|
||||
else /* Filter == ETH_L4_FILTER_1 */
|
||||
{
|
||||
/* Get configuration from MACL3L4C1R register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
|
||||
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
|
||||
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
|
||||
/* Get configuration from MACL4A1R register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -204,43 +235,84 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
* that contains L3 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
{
|
||||
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
|
||||
|
||||
if(pL3FilterConfig == NULL)
|
||||
if (pL3FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write configuration to (MACL3L4C0R + filter )register */
|
||||
MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
if (Filter == ETH_L3_FILTER_0)
|
||||
{
|
||||
/* Write configuration to MACL3L4C0R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
}
|
||||
else /* Filter == ETH_L3_FILTER_1 */
|
||||
{
|
||||
/* Write configuration to MACL3L4C1R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
}
|
||||
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
if (Filter == ETH_L3_FILTER_0)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
|
||||
/* Set the IPv4 destination address match */
|
||||
WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
|
||||
}
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
else /* Filter == ETH_L3_FILTER_1 */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
|
||||
/* Set the IPv4 destination address match */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]);
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]);
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]);
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]);
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr);
|
||||
/* Set the IPv4 destination address match */
|
||||
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable L3 filter */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -257,30 +329,53 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
* that will contain the L3 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
{
|
||||
if(pL3FilterConfig == NULL)
|
||||
if (pL3FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
ETH_MACL3L4CR_L3PEN);
|
||||
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
(ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
|
||||
pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
(ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
|
||||
pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
ETH_MACL3L4CR_L3HSBM) >> 6);
|
||||
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
ETH_MACL3L4CR_L3HDBM) >> 11);
|
||||
|
||||
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
|
||||
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
|
||||
pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
|
||||
pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
|
||||
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
|
||||
|
||||
if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
if (Filter == ETH_L3_FILTER_0)
|
||||
{
|
||||
pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
|
||||
}
|
||||
}
|
||||
else
|
||||
else /* ETH_L3_FILTER_1 */
|
||||
{
|
||||
pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
|
||||
pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R);
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -318,22 +413,29 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
|
|||
* that will contain the VLAN filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if(pVlanConfig == NULL)
|
||||
if (pVlanConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
|
||||
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
|
||||
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
|
||||
pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
|
||||
(ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
|
||||
pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U)
|
||||
? DISABLE : ENABLE;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -348,7 +450,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if(pVlanConfig == NULL)
|
||||
if (pVlanConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
|
@ -356,13 +458,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
|
|||
/* Write config to MACVTR */
|
||||
MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
|
||||
pVlanConfig->StripInnerVLANTag |
|
||||
((uint32_t)pVlanConfig->InnerVLANTag << 27) |
|
||||
((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
|
||||
((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
|
||||
((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
|
||||
pVlanConfig->StripVLANTag |
|
||||
pVlanConfig->VLANTypeCheck |
|
||||
((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
|
||||
((uint32_t)pVlanConfig->InnerVLANTag << 27) |
|
||||
((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
|
||||
((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
|
||||
((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
|
||||
pVlanConfig->StripVLANTag |
|
||||
pVlanConfig->VLANTypeCheck |
|
||||
((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -390,14 +492,15 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
|
|||
* that will contain the Tx VLAN filter configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if (pVlanConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if(VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
if (VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
|
||||
|
|
@ -424,13 +527,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
|
|||
* that contains Tx VLAN filter configuration.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
const ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if(VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
if (VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
|
||||
((uint32_t)pVlanConfig->SVLANType << 19) |
|
||||
pVlanConfig->VLANTagControl));
|
||||
((uint32_t)pVlanConfig->SVLANType << 19) |
|
||||
pVlanConfig->VLANTagControl));
|
||||
/* Enable Double VLAN processing */
|
||||
SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
|
||||
}
|
||||
|
|
@ -438,7 +542,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
|
|||
{
|
||||
MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
|
||||
((uint32_t)pVlanConfig->SVLANType << 19) |
|
||||
pVlanConfig->VLANTagControl));
|
||||
pVlanConfig->VLANTagControl));
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -454,9 +558,9 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
|
|||
* @param VLANIdentifier: VLAN Identifier 16 bit value
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
|
||||
{
|
||||
if(VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
if (VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
|
||||
}
|
||||
|
|
@ -504,9 +608,10 @@ void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
|
|||
__HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
|
||||
|
||||
/* Write to LPI Control register: Enter low power mode */
|
||||
MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
|
||||
((uint32_t)TxClockStop << 21) |
|
||||
ETH_MACLCSR_LPIEN));
|
||||
MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE),
|
||||
(((uint32_t)TxAutomate << 19) |
|
||||
((uint32_t)TxClockStop << 21) |
|
||||
ETH_MACLCSR_LPIEN));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -524,14 +629,13 @@ void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
|
|||
__HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the ETH MAC LPI event
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @retval ETH MAC WakeUp event
|
||||
*/
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth)
|
||||
{
|
||||
return heth->MACLPIEvent;
|
||||
}
|
||||
|
|
@ -551,9 +655,6 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
|
|||
#endif /* ETH */
|
||||
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,23 +6,22 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_ETH_EX_H
|
||||
#define STM32H7xx_HAL_ETH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(ETH)
|
||||
|
|
@ -42,131 +41,136 @@
|
|||
/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
|
||||
/**
|
||||
* @brief ETH RX VLAN structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
|
||||
|
||||
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
|
||||
|
||||
|
||||
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of
|
||||
@ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
|
||||
|
||||
FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
|
||||
|
||||
FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
|
||||
|
||||
|
||||
FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
|
||||
|
||||
|
||||
FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
|
||||
|
||||
uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
|
||||
|
||||
uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
|
||||
This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
|
||||
|
||||
|
||||
uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
|
||||
|
||||
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
|
||||
}ETH_RxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
|
||||
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
|
||||
} ETH_RxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
|
||||
/**
|
||||
* @brief ETH TX VLAN structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
|
||||
|
||||
|
||||
FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
|
||||
|
||||
|
||||
uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
|
||||
This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
|
||||
}ETH_TxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
} ETH_TxVLANConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief ETH L3 filter structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
|
||||
This parameter can be a value of @ref ETHEx_L3_Protocol */
|
||||
|
||||
|
||||
uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Source_Match */
|
||||
|
||||
|
||||
uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
|
||||
This parameter can be a value of @ref ETHEx_L3_Destination_Match */
|
||||
|
||||
|
||||
uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
|
||||
uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
|
||||
This parameter can be a value from 0 to 31 */
|
||||
|
||||
|
||||
uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
|
||||
This parameter can be a value from 0x0 to 0xFFFFFFFF */
|
||||
|
||||
|
||||
uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
|
||||
This parameter can be a value from 0 to 0xFFFFFFFF */
|
||||
|
||||
|
||||
uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
|
||||
This parameter must be a table of 4 words (4* 32 bits) */
|
||||
}ETH_L3FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
} ETH_L3FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
/**
|
||||
* @brief ETH L4 filter structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
|
||||
This parameter can be a value of @ref ETHEx_L4_Protocol */
|
||||
|
||||
|
||||
uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Source_Match */
|
||||
|
||||
|
||||
uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
|
||||
This parameter can be a value of @ref ETHEx_L4_Destination_Match */
|
||||
|
||||
uint32_t SourcePort; /*!< Sets the L4 filter source port
|
||||
|
||||
uint32_t SourcePort; /*!< Sets the L4 filter source port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
|
||||
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
}ETH_L4FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
|
||||
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
|
||||
This parameter must be a value from 0x0 to 0xFFFF */
|
||||
} ETH_L4FilterConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
|
||||
* @{
|
||||
*/
|
||||
#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
|
||||
#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
|
||||
*/
|
||||
#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
|
||||
#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
|
||||
#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
|
||||
#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_FILTER_0 ((uint32_t)0x00000000)
|
||||
#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C)
|
||||
#define ETH_L3_FILTER_0 0x00000000U
|
||||
#define ETH_L3_FILTER_1 0x0000000CU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -174,8 +178,8 @@ typedef struct{
|
|||
/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_FILTER_0 ((uint32_t)0x00000000)
|
||||
#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C)
|
||||
#define ETH_L4_FILTER_0 0x00000000U
|
||||
#define ETH_L4_FILTER_1 0x0000000CU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -184,7 +188,7 @@ typedef struct{
|
|||
* @{
|
||||
*/
|
||||
#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
|
||||
#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)
|
||||
#define ETH_L3_IPV4_MATCH 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -194,53 +198,53 @@ typedef struct{
|
|||
*/
|
||||
#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
|
||||
#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
|
||||
#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
#define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
|
||||
#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
|
||||
#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
#define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
|
||||
#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000)
|
||||
#define ETH_L4_TCP_MATCH 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
|
||||
#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
|
||||
#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
|
||||
#define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
|
||||
* @{
|
||||
*/
|
||||
#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
|
||||
#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
|
||||
#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
|
||||
#define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
|
||||
#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
|
||||
|
|
@ -251,7 +255,7 @@ typedef struct{
|
|||
|
||||
/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
|
||||
#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
|
||||
|
|
@ -259,17 +263,17 @@ typedef struct{
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
|
||||
#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
|
||||
#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)
|
||||
#define ETH_VLANTYPECHECK_CVLAN 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -279,21 +283,21 @@ typedef struct{
|
|||
#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
*/
|
||||
|
||||
/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
|
||||
* @{
|
||||
*/
|
||||
#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
|
||||
#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
*/
|
||||
#define ETH_INNER_TX_VLANTAG 0x00000001U
|
||||
#define ETH_OUTER_TX_VLANTAG 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ETHEx_Exported_Functions
|
||||
* @{
|
||||
|
|
@ -305,42 +309,49 @@ typedef struct{
|
|||
/* MAC ARP Offloading APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
|
||||
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
|
||||
|
||||
/* MAC L3 L4 Filtering APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
|
||||
/* MAC VLAN Processing APIs ************************************************/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
const ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
|
||||
|
||||
/* Energy Efficient Ethernet APIs *********************************************/
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
|
||||
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
|
||||
FunctionalState TxClockStop);
|
||||
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -353,5 +364,3 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_ETH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -8,6 +8,17 @@
|
|||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
|
|
@ -87,7 +98,7 @@
|
|||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
|
|
@ -98,23 +109,11 @@
|
|||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -440,6 +439,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
}
|
||||
#endif /*DUAL_CORE*/
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00U;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
|
||||
{
|
||||
|
|
@ -451,10 +454,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
|
|
@ -472,29 +471,18 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
|
||||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->GPIOSel = 0x00U;
|
||||
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00U;
|
||||
}
|
||||
|
||||
/* Get default Pend Clear Source */
|
||||
pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
|
||||
|
||||
/* 3] Get D3 Pend Clear source */
|
||||
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
|
||||
{
|
||||
regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
if(((*regaddr) & linepos) == 0UL)
|
||||
{
|
||||
/* if PMR unset, then no pend clear source is used */
|
||||
pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
|
||||
}
|
||||
else
|
||||
if(((*regaddr) & linepos) != 0UL)
|
||||
{
|
||||
/* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */
|
||||
if(linepos < 16UL)
|
||||
|
|
@ -511,11 +499,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
|
|||
pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* if line wakeup target is not any, then no pend clear source is used */
|
||||
pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -759,6 +742,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
|||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Edge);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
|
@ -805,6 +791,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
|||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Edge);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
|
@ -874,4 +863,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -536,4 +535,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
|||
|
||||
#endif /* STM32H7xx_HAL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -304,12 +303,15 @@ typedef struct
|
|||
uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
|
||||
This parameter must be a number between:
|
||||
- 0 and 127, if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and 63, if IdType is FDCAN_EXTENDED_ID */
|
||||
- 0 and 63, if IdType is FDCAN_EXTENDED_ID
|
||||
When the frame is a Non-Filter matching frame, this parameter
|
||||
is unused. */
|
||||
|
||||
uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
|
||||
Acceptance of non-matching frames may be enabled via
|
||||
HAL_FDCAN_ConfigGlobalFilter().
|
||||
This parameter can be 0 or 1 */
|
||||
Acceptance of non-matching frames may be enabled via
|
||||
HAL_FDCAN_ConfigGlobalFilter().
|
||||
This parameter takes 0 if the frame matched an Rx filter or
|
||||
1 if it did not match any Rx filter */
|
||||
|
||||
} FDCAN_RxHeaderTypeDef;
|
||||
|
||||
|
|
@ -389,52 +391,55 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
|
||||
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
|
||||
frame with its BRS flag set.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
|
||||
of a CAN FD format frame with its BRS flag set.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
|
||||
uint32_t Activity; /*!< Specifies the FDCAN module communication state.
|
||||
This parameter can be a value of @ref FDCAN_communication_state */
|
||||
This parameter can be a value of @ref FDCAN_communication_state */
|
||||
|
||||
uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
|
||||
This parameter can be:
|
||||
- 0 : The FDCAN is in Error_Active state
|
||||
- 1 : The FDCAN is in Error_Passive state */
|
||||
- 1 : The FDCAN is in Error_Passive state */
|
||||
|
||||
uint32_t Warning; /*!< Specifies the FDCAN module warning status.
|
||||
This parameter can be:
|
||||
- 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
|
||||
- 1 : at least one of error counters has reached the Error_Warning limit of 96 */
|
||||
- 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
|
||||
Error_Warning limit of 96
|
||||
- 1 : at least one of error counters has reached the Error_Warning
|
||||
limit of 96 */
|
||||
|
||||
uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
|
||||
This parameter can be:
|
||||
- 0 : The FDCAN is not in Bus_Off state
|
||||
- 1 : The FDCAN is in Bus_Off state */
|
||||
- 1 : The FDCAN is in Bus_Off state */
|
||||
|
||||
uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
|
||||
This parameter can be:
|
||||
- 0 : Last received CAN FD message did not have its ESI flag set
|
||||
- 1 : Last received CAN FD message had its ESI flag set */
|
||||
- 1 : Last received CAN FD message had its ESI flag set */
|
||||
|
||||
uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
|
||||
This parameter can be:
|
||||
- 0 : Last received CAN FD message did not have its BRS flag set
|
||||
- 1 : Last received CAN FD message had its BRS flag set */
|
||||
- 1 : Last received CAN FD message had its BRS flag set */
|
||||
|
||||
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
|
||||
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
|
||||
since last protocol status.
|
||||
This parameter can be:
|
||||
- 0 : no CAN FD message received
|
||||
- 1 : CAN FD message received */
|
||||
- 0 : No CAN FD message received
|
||||
- 1 : CAN FD message received */
|
||||
|
||||
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
|
||||
This parameter can be:
|
||||
- 0 : No protocol exception event occurred since last read access
|
||||
- 1 : Protocol exception event occurred */
|
||||
- 1 : Protocol exception event occurred */
|
||||
|
||||
uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
|
||||
This parameter can be a number between 0 and 127 */
|
||||
This parameter can be a number between 0 and 127 */
|
||||
|
||||
} FDCAN_ProtocolStatusTypeDef;
|
||||
|
||||
|
|
@ -444,21 +449,24 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
|
||||
This parameter can be a number between 0 and 127 */
|
||||
This parameter can be a number between 0 and 127 */
|
||||
|
||||
uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
|
||||
This parameter can be:
|
||||
- 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
|
||||
- 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
|
||||
- 0 : The Receive Error Counter (RxErrorCnt) is below the error
|
||||
passive level of 128
|
||||
- 1 : The Receive Error Counter (RxErrorCnt) has reached the error
|
||||
passive level of 128 */
|
||||
|
||||
uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
|
||||
This parameter can be a number between 0 and 255.
|
||||
This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
|
||||
or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
|
||||
TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
|
||||
This counter is incremented each time when a FDCAN protocol error causes
|
||||
the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
|
||||
the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
|
||||
FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
|
||||
|
||||
} FDCAN_ErrorCountersTypeDef;
|
||||
|
||||
|
|
@ -514,7 +522,7 @@ typedef struct
|
|||
This parameter is ignored if OperationMode is set to
|
||||
FDCAN_TT_COMMUNICATION_LEVEL0 */
|
||||
|
||||
uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix.
|
||||
uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix.
|
||||
This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */
|
||||
|
||||
uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
|
||||
|
|
@ -529,7 +537,7 @@ typedef struct
|
|||
This parameter must be a number between 0 and 4095 */
|
||||
|
||||
uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator.
|
||||
It is adviced to set this parameter to the largest applicable value.
|
||||
It is advised to set this parameter to the largest applicable value.
|
||||
This parameter must be a number between 0x10000 and 0x1FFFF */
|
||||
|
||||
uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator.
|
||||
|
|
@ -641,7 +649,7 @@ typedef struct
|
|||
- 0 : No Gap in schedule
|
||||
- 1 : Gap time after Basic Cycle has started */
|
||||
|
||||
uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced.
|
||||
uint32_t WaitForEvt; /*!< Specifies whether a Gap is announced.
|
||||
This parameter can be:
|
||||
- 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
|
||||
- 1 : Reference message with Next_is_Gap = 1 received */
|
||||
|
|
@ -757,15 +765,15 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
|
||||
HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
|
||||
HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
|
||||
HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
|
||||
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
|
||||
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
|
||||
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
|
||||
HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
|
||||
HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
|
||||
HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
|
||||
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
|
||||
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
|
||||
|
||||
HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
|
||||
HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
|
||||
HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
|
||||
HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
|
||||
|
||||
} HAL_FDCAN_CallbackIDTypeDef;
|
||||
|
||||
|
|
@ -807,8 +815,8 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
|
||||
#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
|
||||
#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
|
||||
#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */
|
||||
#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
|
||||
#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
|
||||
#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
|
||||
|
|
@ -866,21 +874,21 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* @{
|
||||
*/
|
||||
#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
|
||||
#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */
|
||||
#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */
|
||||
#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */
|
||||
#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */
|
||||
#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
|
||||
#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
|
||||
#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
|
||||
#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
|
||||
#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
|
||||
#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
|
||||
#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
|
||||
#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
|
||||
#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
|
||||
#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
|
||||
#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
|
||||
#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
|
||||
#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
|
||||
#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
|
||||
#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
|
||||
#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
|
||||
#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
|
||||
#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
|
||||
#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
|
||||
#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
|
||||
#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
|
||||
#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
|
||||
#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
|
||||
#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
|
||||
#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
|
||||
#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -960,21 +968,21 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* @{
|
||||
*/
|
||||
#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1213,7 +1221,7 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* @{
|
||||
*/
|
||||
#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
|
||||
#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
|
||||
#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1259,21 +1267,21 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* @{
|
||||
*/
|
||||
#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
|
||||
#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1658,9 +1666,9 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
|
||||
#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
|
||||
#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
|
||||
#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
|
||||
#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
|
||||
#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1778,10 +1786,10 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
|
||||
|
|
@ -1821,7 +1829,9 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* This parameter can be one of @arg FDCAN_Interrupts
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
|
||||
#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
|
||||
((__HANDLE__)->Instance->IR &\
|
||||
(__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FDCAN interrupts.
|
||||
|
|
@ -1830,11 +1840,11 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
|
|||
* This parameter can be any combination of @arg FDCAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do{ \
|
||||
#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do { \
|
||||
((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
|
||||
FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
|
||||
}while(0)
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FDCAN flag is set or not.
|
||||
|
|
@ -1843,7 +1853,9 @@ do{ \
|
|||
* This parameter can be one of @arg FDCAN_flags
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
|
||||
#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? \
|
||||
((__HANDLE__)->Instance->IR &\
|
||||
(__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FDCAN flags.
|
||||
|
|
@ -1852,11 +1864,11 @@ do{ \
|
|||
* This parameter can be any combination of @arg FDCAN_flags
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
do{ \
|
||||
#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
do { \
|
||||
((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
|
||||
FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \
|
||||
}while(0)
|
||||
} while(0);
|
||||
|
||||
/** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
|
|
@ -1864,7 +1876,10 @@ do{ \
|
|||
* This parameter can be a value of @arg FDCAN_Interrupts
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
|
||||
#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
|
||||
((__HANDLE__)->Instance->IE &\
|
||||
(__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & \
|
||||
(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FDCAN TT interrupts.
|
||||
|
|
@ -1950,29 +1965,41 @@ HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
|
|||
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
|
||||
pFDCAN_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxEventFifoCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_RxFifo0CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_RxFifo1CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_ErrorStatusCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
|
|
@ -1983,12 +2010,15 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *
|
|||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
|
||||
const FDCAN_ClkCalUnitTypeDef *sCcuConfig);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
|
||||
uint32_t HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
|
||||
uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
|
||||
uint32_t RejectRemoteExt);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
|
||||
|
|
@ -1996,14 +2026,16 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3
|
|||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
|
||||
uint32_t TimeoutPeriod);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
|
||||
uint32_t TdcFilter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
|
|
@ -2020,21 +2052,27 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
|
|||
/* Control functions **********************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
|
||||
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
|
||||
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_ErrorCountersTypeDef *ErrorCounters);
|
||||
uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
|
||||
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
|
||||
uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
|
||||
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
|
||||
uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
|
||||
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -2044,13 +2082,16 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd
|
|||
* @{
|
||||
*/
|
||||
/* TT Configuration and control functions**************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier,
|
||||
uint32_t Payload);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource,
|
||||
uint32_t TimeMarkValue, uint32_t RepeatFactor,
|
||||
uint32_t StartCycle);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
|
||||
|
|
@ -2064,7 +2105,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
|
|||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_TTOperationStatusTypeDef *TTOpStatus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -2074,8 +2116,10 @@ HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, F
|
|||
*/
|
||||
/* Interrupts management ******************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
|
||||
uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
|
||||
uint32_t BufferIndexes);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
|
||||
HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
|
||||
|
|
@ -2113,8 +2157,8 @@ void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlo
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -2190,8 +2234,8 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
|
|||
#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
|
||||
#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
|
||||
#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
|
||||
#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
|
||||
#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
|
||||
#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
|
||||
#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
|
||||
#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
|
||||
((SIZE) == FDCAN_DATA_BYTES_12) || \
|
||||
((SIZE) == FDCAN_DATA_BYTES_16) || \
|
||||
|
|
@ -2377,6 +2421,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
|
|||
((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
|
||||
((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
|
||||
((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
|
||||
|
||||
#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
|
||||
#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -2414,4 +2462,3 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
|
|||
#endif /* STM32H7xx_HAL_FDCAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -74,14 +74,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -110,7 +108,13 @@
|
|||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
|
|
@ -119,8 +123,8 @@ FLASH_ProcessTypeDef pFlash;
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
|
|
@ -169,6 +173,8 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
|
|||
#endif /* FLASH_OPTCR_PG_OTP */
|
||||
{
|
||||
bank = FLASH_BANK_1;
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(TypeProgram);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
|
||||
|
|
@ -335,6 +341,8 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
|
|||
#endif /* FLASH_OPTCR_PG_OTP */
|
||||
{
|
||||
bank = FLASH_BANK_1;
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(TypeProgram);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
|
||||
|
|
@ -651,6 +659,38 @@ void HAL_FLASH_IRQHandler(void)
|
|||
HAL_FLASH_OperationErrorCallback(temp);
|
||||
}
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/* Check FLASH Bank1 ECC single correction error flag */
|
||||
errorflag = FLASH->SR1 & FLASH_FLAG_SNECCERR_BANK1;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= errorflag;
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccCorrectionCallback();
|
||||
|
||||
/* Clear FLASH Bank1 ECC single correction error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
|
||||
}
|
||||
|
||||
/* Check FLASH Bank1 ECC double detection error flag */
|
||||
errorflag = FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= errorflag;
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear FLASH Bank1 ECC double detection error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
|
||||
}
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
/* Check FLASH Bank2 operation error flags */
|
||||
#if defined (FLASH_SR_OPERR)
|
||||
|
|
@ -694,6 +734,39 @@ void HAL_FLASH_IRQHandler(void)
|
|||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(temp);
|
||||
}
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/* Check FLASH Bank2 ECC single correction error flag */
|
||||
errorflag = FLASH->SR2 & FLASH_FLAG_SNECCERR_BANK2;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= (errorflag | 0x80000000U);
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccCorrectionCallback();
|
||||
|
||||
/* Clear FLASH Bank2 ECC single correction error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
|
||||
}
|
||||
|
||||
/* Check FLASH Bank2 ECC double detection error flag */
|
||||
errorflag = FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= (errorflag | 0x80000000U);
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear FLASH Bank2 ECC double detection error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
|
||||
}
|
||||
|
||||
#endif /* USE_FLASH_ECC */
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
|
|
@ -767,8 +840,8 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Management functions
|
||||
*
|
||||
* @brief Management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
|
|
@ -928,8 +1001,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
|||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
|
|
@ -967,7 +1040,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
|||
* @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
|
||||
* @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
|
||||
* @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
|
||||
*/
|
||||
*/
|
||||
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
|
|
@ -1001,7 +1074,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
|
|||
flag will be set */
|
||||
|
||||
uint32_t bsyflag = FLASH_FLAG_QW_BANK1;
|
||||
uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
|
||||
uint32_t errorflag = 0;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
|
||||
|
|
@ -1010,8 +1083,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
|
|||
|
||||
if (Bank == FLASH_BANK_2)
|
||||
{
|
||||
/* Get Error Flags */
|
||||
errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
|
||||
/* Select bsyflag depending on Bank */
|
||||
bsyflag = FLASH_FLAG_QW_BANK2;
|
||||
}
|
||||
|
|
@ -1028,6 +1099,18 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
|
|||
}
|
||||
}
|
||||
|
||||
/* Get Error Flags */
|
||||
if (Bank == FLASH_BANK_1)
|
||||
{
|
||||
errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
else
|
||||
{
|
||||
errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
/* In case of error reported in Flash SR1 or SR2 register */
|
||||
if((errorflag & 0x7FFFFFFFU) != 0U)
|
||||
{
|
||||
|
|
@ -1184,4 +1267,4 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
|
|||
|
|
@ -6,14 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -861,4 +859,3 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank
|
|||
|
||||
#endif /* STM32H7xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -58,18 +58,26 @@
|
|||
(++) Perform the CRC computation
|
||||
(++) Disable CRC feature
|
||||
|
||||
(#) Error correction code error functions:
|
||||
(++) Use the HAL_FLASHEx_EnableEccCorrectionInterrupt() and HAL_FLASHEx_DisableEccCorrectionInterrupt()
|
||||
functions to enable and disable the FLASH ECC correction interruption.
|
||||
(++) Use the HAL_FLASHEx_EnableEccDetectionInterrupt() and HAL_FLASHEx_DisableEccDetectionInterrupt()
|
||||
functions to enable and disable the FLASH ECC Detection interruption.
|
||||
(++) Handle ECCD interrupt by calling HAL_FLASHEx_BusFault_IRQHandler()
|
||||
(++) Use HAL_FLASHEx_BusFault_IRQHandler() function called under BusFault_IRQHandler() interrupt subroutine
|
||||
to handle the ECCD interrupt.
|
||||
(++) Use HAL_FLASHEx_GetEccInfo() function to get the flash ECC fail information.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -408,7 +416,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
|||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL Status
|
||||
|
|
@ -549,7 +557,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
|||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
|
||||
* contains the configuration information for the programming.
|
||||
* @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
|
||||
* as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
|
||||
|
|
@ -820,6 +828,251 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
|
|||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group2 Extended ECC operation functions
|
||||
* @brief Extended ECC operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended ECC operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the Extended FLASH
|
||||
ECC Operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ECC correction interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable ECC correction interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
}
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
/**
|
||||
* @brief Enable ECC correction interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
/**
|
||||
* @brief Enable ECC Detection interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC Detection interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable ECC Detection interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
}
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
/**
|
||||
* @brief Enable ECC Detection interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC Detection interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
/**
|
||||
* @brief Get the ECC error information.
|
||||
* @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
|
||||
* ECC error information.
|
||||
* @note This function should be called before ECC bit is cleared
|
||||
* (in callback function)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
|
||||
{
|
||||
uint32_t errorflag;
|
||||
|
||||
/* Check FLASH Bank1 ECC single correction and double detection error flags */
|
||||
errorflag = FLASH->SR1 & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1);
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
pData->Area = FLASH_ECC_AREA_USER_BANK1;
|
||||
pData->Address = ((((FLASH->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK1_BASE);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
/* Check FLASH Bank2 ECC single correction and double detection error flags */
|
||||
errorflag = FLASH->SR2 & (FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2);
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
pData->Area = FLASH_ECC_AREA_USER_BANK2;
|
||||
pData->Address = ((((FLASH->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK2_BASE);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle Flash ECC Detection interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_BusFault_IRQHandler(void)
|
||||
{
|
||||
/* Check if the ECC double error occured*/
|
||||
if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0)
|
||||
{
|
||||
/* FLASH ECC detection user callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear Bank 1 ECC double detection error flag
|
||||
note : this step will clear all the informations related to the flash ECC detection
|
||||
*/
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
/* Check if the ECC double error occured*/
|
||||
if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0)
|
||||
{
|
||||
/* FLASH ECC detection user callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear Bank 2 ECC double detection error flag
|
||||
note : this step will clear all the informations related to the flash ECC detection
|
||||
*/
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC Correction interrupt callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC Detection interrupt callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -971,7 +1224,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
|
|||
* @brief Enable the write protection of the desired bank1 or bank 2 sectors
|
||||
* @param WRPSector specifies the sector(s) to be write protected.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
|
||||
* @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL
|
||||
*
|
||||
* @param Banks the specific bank to apply WRP sectors
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -1006,7 +1259,7 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
|
|||
* @brief Disable the write protection of the desired bank1 or bank 2 sectors
|
||||
* @param WRPSector specifies the sector(s) to disable write protection.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
|
||||
* @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
|
||||
*
|
||||
* @param Banks the specific bank to apply WRP sectors
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -1045,7 +1298,7 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
|
|||
|
||||
* @param WRPSector gives the write protected sector(s) on the given bank .
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
|
||||
* @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
|
||||
*
|
||||
* @param Bank the specific bank to apply WRP sectors
|
||||
* This parameter can be exclusively one of the following values:
|
||||
|
|
@ -1819,7 +2072,7 @@ static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)
|
|||
*/
|
||||
static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
|
||||
{
|
||||
return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);;
|
||||
return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);
|
||||
}
|
||||
#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
|
||||
|
||||
|
|
@ -1846,7 +2099,7 @@ static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)
|
|||
*/
|
||||
static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
|
||||
{
|
||||
return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);;
|
||||
return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);
|
||||
}
|
||||
#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
|
||||
|
||||
|
|
@ -1860,4 +2113,3 @@ static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,14 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
|
@ -178,6 +176,20 @@ typedef struct
|
|||
|
||||
} FLASH_CRCInitTypeDef;
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/**
|
||||
* @brief ECC Info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Area; /*!< Area from which an ECC was detected.
|
||||
This parameter can be a value of @ref FLASHEx_ECC_Area */
|
||||
|
||||
uint32_t Address; /*!< ECC error address */
|
||||
|
||||
} FLASH_EccInfoTypeDef;
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -218,6 +230,18 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @defgroup FLASH_ECC_Area FLASH ECC Area
|
||||
* @brief FLASH ECC Area
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
|
||||
#define FLASH_ECC_AREA_USER_BANK2 0x00000001U /*!< FLASH bank 2 area */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -359,6 +383,8 @@ typedef struct
|
|||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
|
||||
|
||||
/* Unused FLASH Latency defines */
|
||||
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */
|
||||
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */
|
||||
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
|
||||
|
|
@ -744,6 +770,9 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OTPBL_LOCKBL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
|
||||
|
|
@ -756,9 +785,6 @@ typedef struct
|
|||
* @retval The FLASH Boot Base Address
|
||||
*/
|
||||
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_CR_PSIZE)
|
||||
/**
|
||||
|
|
@ -806,6 +832,9 @@ typedef struct
|
|||
* This return value can be a value of @ref FLASHEx_Programming_Delay
|
||||
*/
|
||||
#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
|
|
@ -834,6 +863,38 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
|
|||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void);
|
||||
#if defined (DUAL_BANK)
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void);
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void);
|
||||
#if defined (DUAL_BANK)
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void);
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
|
||||
void HAL_FLASHEx_BusFault_IRQHandler(void);
|
||||
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void);
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1002,14 +1063,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,18 +2,16 @@
|
|||
******************************************************************************
|
||||
* @file stm32h7xx_hal_fmac.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the FMAC firmware
|
||||
* library.
|
||||
* @brief Header for stm32h7xx_hal_fmac.c module
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -71,10 +69,12 @@ typedef struct
|
|||
uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
|
||||
Set to 0 if no valid configuration was applied. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
int16_t *pInput; /*!< Pointer to FMAC input data buffer */
|
||||
|
|
@ -82,20 +82,23 @@ typedef struct
|
|||
uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
|
||||
|
||||
uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
|
||||
In case of early interruption of the filter operation, its value will be updated. */
|
||||
In case of early interruption of the filter operation,
|
||||
its value will be updated. */
|
||||
|
||||
int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
|
||||
|
||||
uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
|
||||
|
||||
uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
|
||||
In case of early interruption of the filter operation, its value will be updated. */
|
||||
In case of early interruption of the filter operation,
|
||||
its value will be updated. */
|
||||
|
||||
DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */
|
||||
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle
|
||||
parameters */
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
|
||||
|
|
@ -136,7 +139,7 @@ typedef struct
|
|||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief FMAC Callback ID structure definition
|
||||
* @brief FMAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
|
|
@ -164,34 +167,41 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
|
||||
Ignored if InputBufferSize is set to 0 (previous configuration kept).
|
||||
NB: the buffers can overlap or even coincide exactly. */
|
||||
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory
|
||||
(0x00 to 0xFF). Ignored if InputBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
|
||||
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer
|
||||
(including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
|
||||
in the buffer is inferior to this threshold.
|
||||
This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
|
||||
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number
|
||||
of free spaces in the buffer is lower than this threshold.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
|
||||
Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
|
||||
NB: the buffers can overlap or even coincide exactly. */
|
||||
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal
|
||||
memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer.
|
||||
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
|
||||
Ignored if OuputBufferSize is set to 0 (previous configuration kept).
|
||||
NB: the buffers can overlap or even coincide exactly. */
|
||||
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal
|
||||
memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
|
||||
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer
|
||||
(including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
|
||||
in the buffer is inferior to this threshold.
|
||||
This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
|
||||
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number
|
||||
of unread values in the buffer is lower than this threshold.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
|
||||
If not needed, it should be set to NULL. */
|
||||
|
|
@ -199,21 +209,27 @@ typedef struct
|
|||
uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
|
||||
|
||||
int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
|
||||
If not needed (re-use of a previously loaded buffer), it should be set to NULL. */
|
||||
If not needed (re-use of a previously loaded buffer),
|
||||
it should be set to NULL. */
|
||||
|
||||
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None.
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded).
|
||||
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range
|
||||
is exceeded, wrapping is done when the clipping feature is disabled
|
||||
and saturation is done when the clipping feature is enabled.
|
||||
This parameter can be a value of @ref FMAC_Clip_State. */
|
||||
|
||||
uint32_t Filter; /*!< Filter type.
|
||||
This parameter can be a value of @ref FMAC_Functions (filter related values). */
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Functions (filter related values). */
|
||||
|
||||
uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
|
||||
|
||||
|
|
@ -238,17 +254,17 @@ typedef struct
|
|||
/** @defgroup FMAC_Error_Code FMAC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */
|
||||
#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */
|
||||
#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */
|
||||
#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */
|
||||
#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */
|
||||
#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */
|
||||
#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */
|
||||
#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
|
||||
#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
|
||||
#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
|
||||
#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
|
||||
#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
|
||||
#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */
|
||||
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */
|
||||
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -257,11 +273,11 @@ typedef struct
|
|||
/** @defgroup FMAC_Functions FMAC Functions
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */
|
||||
#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */
|
||||
#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */
|
||||
#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */
|
||||
#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */
|
||||
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
|
||||
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
|
||||
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
|
||||
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
|
||||
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -270,15 +286,23 @@ typedef struct
|
|||
* @{
|
||||
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
|
||||
*/
|
||||
#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
|
||||
#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
|
||||
#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
|
||||
#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
|
||||
Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
|
||||
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */
|
||||
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 1.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 1. */
|
||||
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 2.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 2. */
|
||||
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 4.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 4. */
|
||||
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 8.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 8. */
|
||||
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -287,7 +311,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
|
||||
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */
|
||||
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
|
||||
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
|
||||
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
|
||||
/**
|
||||
|
|
@ -297,7 +321,7 @@ typedef struct
|
|||
/** @defgroup FMAC_Clip_State FMAC Clip State
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */
|
||||
#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
|
||||
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -310,7 +334,8 @@ typedef struct
|
|||
#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
|
||||
#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
|
||||
#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
|
||||
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
|
||||
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag
|
||||
(this helps in debugging a filter) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -322,62 +347,32 @@ typedef struct
|
|||
#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
|
||||
#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
|
||||
#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
|
||||
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
|
||||
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable
|
||||
(this helps in debugging a filter) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_DMAR DMA Read Request Enable bit
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_variables FMAC Exported variables
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_DMAW DMA Write Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_DMAS DMA START bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_START FMAC_PARAM_START /*!< DMA Start */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset FMAC handle state.
|
||||
/**
|
||||
* @brief Reset FMAC handle state.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -392,10 +387,10 @@ typedef struct
|
|||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the FMAC interrupt when result is ready
|
||||
* @brief Enable the specified FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
|
|
@ -410,7 +405,7 @@ typedef struct
|
|||
* @brief Disable the FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
|
|
@ -421,10 +416,11 @@ typedef struct
|
|||
#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified FMAC interrupt occurred or not.
|
||||
/**
|
||||
* @brief Check whether the specified FMAC interrupt occurred or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
|
|
@ -435,7 +431,8 @@ typedef struct
|
|||
#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Clear specified FMAC interrupt status. Dummy macro as the
|
||||
/**
|
||||
* @brief Clear specified FMAC interrupt status. Dummy macro as the
|
||||
interrupt status flags are read-only.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to clear.
|
||||
|
|
@ -443,10 +440,11 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified FMAC status flag is set or not.
|
||||
/**
|
||||
* @brief Check whether the specified FMAC status flag is set or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
|
|
@ -457,7 +455,8 @@ typedef struct
|
|||
#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear specified FMAC status flag. Dummy macro as no
|
||||
/**
|
||||
* @brief Clear specified FMAC status flag. Dummy macro as no
|
||||
flag can be cleared.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to clear.
|
||||
|
|
@ -465,7 +464,8 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified FMAC interrupt is enabled or not.
|
||||
/**
|
||||
* @brief Check whether the specified FMAC interrupt is enabled or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -483,8 +483,24 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Macros
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */
|
||||
#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
|
||||
#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */
|
||||
#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */
|
||||
#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */
|
||||
#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros-----------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -500,7 +516,7 @@ typedef struct
|
|||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function.
|
||||
* @brief Verify the FMAC load function used for input data, output data or coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
|
|
@ -509,7 +525,7 @@ typedef struct
|
|||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function.
|
||||
* @brief Verify the FMAC load function used with N values as input or output data.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
|
|
@ -517,7 +533,7 @@ typedef struct
|
|||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function.
|
||||
* @brief Verify the FMAC load function used with N + M values as coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
|
|
@ -549,10 +565,12 @@ typedef struct
|
|||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
|
||||
(((__P__) >= 2U) && ((__P__) <= 127U))) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__P__) >= 2U) && ((__P__) <= 64U))) )
|
||||
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_IIR))))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter Q.
|
||||
|
|
@ -562,7 +580,7 @@ typedef struct
|
|||
*/
|
||||
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__Q__) >= 1U) && ((__Q__) <= 63U))) )
|
||||
(((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter R.
|
||||
|
|
@ -572,7 +590,7 @@ typedef struct
|
|||
*/
|
||||
#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
|
||||
((__R__) <= 7U))
|
||||
((__R__) <= FMAC_PARAM_R_MAX))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC buffer access.
|
||||
|
|
@ -592,6 +610,21 @@ typedef struct
|
|||
#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
|
||||
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
|
||||
|
||||
/**
|
||||
* @brief Check whether the threshold is applicable.
|
||||
* @param __SIZE__ Size of the matching buffer.
|
||||
* @param __WM__ Watermark value.
|
||||
* @param __ACCESS__ Access to the buffer (polling, it, dma, none).
|
||||
* @retval THRESHOLD
|
||||
*/
|
||||
#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
|
||||
(( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
|
||||
((__WM__) == FMAC_THRESHOLD_2)? 2U: \
|
||||
((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
|
||||
((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
|
||||
((__WM__) == FMAC_THRESHOLD_1))|| \
|
||||
((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -624,8 +657,8 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
int16_t *pOutput, uint8_t OutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
|
|
@ -667,8 +700,8 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
|
|||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
|
||||
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
|
||||
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
|
||||
uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -692,5 +725,3 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_FMAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -10,7 +10,18 @@
|
|||
* + Modify physical buffer addresses.
|
||||
* + Modify cache and pre-fetch parameters.
|
||||
* + Error management.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
|
|
@ -121,17 +132,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -890,4 +890,3 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -450,4 +449,3 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
|
|||
|
||||
#endif /* STM32H7xx_HAL_GFXMMU_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -8,6 +8,17 @@
|
|||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
|
|
@ -90,17 +101,6 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -122,14 +122,6 @@
|
|||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE (0x00000003U)
|
||||
#define ANALOG_MODE (0x00000008U)
|
||||
#define EXTI_MODE (0x10000000U)
|
||||
#define GPIO_MODE_IT (0x00010000U)
|
||||
#define GPIO_MODE_EVT (0x00020000U)
|
||||
#define RISING_EDGE (0x00100000U)
|
||||
#define FALLING_EDGE (0x00200000U)
|
||||
#define GPIO_OUTPUT_TYPE (0x00000010U)
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
#define EXTI_CPU1 (0x01000000U)
|
||||
|
|
@ -187,7 +179,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00U)
|
||||
|
|
@ -199,11 +190,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
||||
|
|
@ -213,18 +204,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
|
|
@ -245,7 +242,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
|
@ -255,27 +252,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
|
||||
SYSCFG->EXTICR[position >> 2U] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI_CurrentCPU->IMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI_CurrentCPU->IMR1 = temp;
|
||||
|
||||
temp = EXTI_CurrentCPU->EMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI_CurrentCPU->EMR1 = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
|
|
@ -283,11 +263,28 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
|
||||
temp = EXTI->FTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR1 = temp;
|
||||
|
||||
temp = EXTI_CurrentCPU->EMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI_CurrentCPU->EMR1 = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI_CurrentCPU->IMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI_CurrentCPU->IMR1 = temp;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -338,8 +335,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR1 &= ~(iocurrent);
|
||||
EXTI->FTSR1 &= ~(iocurrent);
|
||||
EXTI->RTSR1 &= ~(iocurrent);
|
||||
|
||||
tmp = 0x0FUL << (4U * (position & 0x03U));
|
||||
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
|
||||
|
|
@ -556,4 +553,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -108,29 +107,26 @@ typedef enum
|
|||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING (0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (0x11120000U) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (0x11220000U) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -286,7 +282,25 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
|||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_Pos 0u
|
||||
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4u
|
||||
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16u
|
||||
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20u
|
||||
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -343,4 +357,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
|||
|
||||
#endif /* STM32H7xx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -55,7 +54,12 @@ extern "C" {
|
|||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#if defined(PWR_CPUCR_RETDS_CD) /* CPU domain power down Deepsleep */
|
||||
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
|
||||
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
|
||||
#define GPIO_AF0_NDSTOP2 ((uint8_t)0x00) /* NDSTOP2 Alternate Function mapping */
|
||||
#endif /* PWR_CPUCR_RETDS_CD */
|
||||
#if defined(PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
|
|
@ -486,4 +490,3 @@ extern "C" {
|
|||
|
||||
#endif /* STM32H7xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -22,7 +21,7 @@
|
|||
#define STM32H7xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -51,7 +50,7 @@ typedef struct
|
|||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
|
||||
|
||||
uint8_t* pKey; /*!< The key is used only in HMAC operation. */
|
||||
uint8_t *pKey; /*!< The key is used only in HMAC operation. */
|
||||
|
||||
} HASH_InitTypeDef;
|
||||
|
||||
|
|
@ -66,7 +65,7 @@ typedef enum
|
|||
HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
|
||||
HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
|
||||
HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
|
||||
}HAL_HASH_StateTypeDef;
|
||||
} HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL phase structures definition
|
||||
|
|
@ -81,7 +80,7 @@ typedef enum
|
|||
(step 2 consists in entering the message text) */
|
||||
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
|
||||
(step 3 consists in entering the outer hash function key) */
|
||||
}HAL_HASH_PhaseTypeDef;
|
||||
} HAL_HASH_PhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL HASH mode suspend definitions
|
||||
|
|
@ -90,7 +89,7 @@ typedef enum
|
|||
{
|
||||
HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
|
||||
HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
|
||||
}HAL_HASH_SuspendTypeDef;
|
||||
} HAL_HASH_SuspendTypeDef;
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
|
|
@ -103,7 +102,7 @@ typedef enum
|
|||
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
|
||||
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
|
||||
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
|
||||
}HAL_HASH_CallbackIDTypeDef;
|
||||
} HAL_HASH_CallbackIDTypeDef;
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
|
|
@ -118,13 +117,13 @@ typedef struct
|
|||
{
|
||||
HASH_InitTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
|
||||
|
||||
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
|
||||
|
||||
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
|
||||
uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
|
||||
|
||||
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
|
||||
|
||||
|
|
@ -155,15 +154,15 @@ typedef struct
|
|||
__IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
|
||||
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
|
||||
void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
|
||||
|
||||
void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
|
||||
void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
|
||||
|
||||
void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
|
||||
void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
|
||||
|
||||
void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
|
||||
void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
|
||||
void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
|
||||
} HASH_HandleTypeDef;
|
||||
|
|
@ -172,7 +171,7 @@ typedef struct
|
|||
/**
|
||||
* @brief HAL HASH Callback pointer definition
|
||||
*/
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
|
||||
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
|
|
@ -244,13 +243,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
|
||||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -288,8 +280,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
|
|
@ -366,7 +358,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @brief Set the number of valid bits in the last word written in data register DIN.
|
||||
* @param __SIZE__ size in bytes of last data written in Data register.
|
||||
* @retval None
|
||||
*/
|
||||
*/
|
||||
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
|
||||
|
||||
/**
|
||||
|
|
@ -389,8 +381,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @retval Digest length
|
||||
*/
|
||||
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
|
||||
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
|
||||
/**
|
||||
* @brief Return number of words already pushed in the FIFO.
|
||||
* @retval Number of words already pushed in the FIFO
|
||||
|
|
@ -424,7 +416,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
|
|||
* @param __SIZE__ input data buffer size.
|
||||
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
|
||||
*/
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
|
||||
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
|
||||
|| (((__SIZE__) % 4U) == 0U))
|
||||
/**
|
||||
* @brief Ensure that handle phase is set to HASH processing.
|
||||
* @param __HANDLE__ HASH handle.
|
||||
|
|
@ -467,7 +460,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
|||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
|
||||
pHASH_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
|
||||
|
||||
|
|
@ -482,12 +476,18 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
|
|||
|
||||
|
||||
/* HASH processing using polling *********************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -499,12 +499,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
*/
|
||||
|
||||
/* HASH processing using IT **************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -515,10 +519,10 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
|||
*/
|
||||
|
||||
/* HASH processing using DMA *************************************************/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -529,8 +533,12 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
|
|||
*/
|
||||
|
||||
/* HASH-MAC processing using polling *****************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -540,8 +548,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -552,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
|
|||
*/
|
||||
|
||||
/* HASH-HMAC processing using DMA ********************************************/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -565,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
|
|||
|
||||
|
||||
/* Peripheral State methods **************************************************/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
|
||||
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
||||
uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -588,15 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
|
|||
*/
|
||||
|
||||
/* Private functions */
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Timeout, uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer,
|
||||
uint32_t Algorithm);
|
||||
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint32_t Algorithm);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -618,4 +640,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
|
|||
|
||||
#endif /* STM32H7xx_HAL_HASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -14,6 +14,17 @@
|
|||
* and SHA-256.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HASH peripheral extended features #####
|
||||
|
|
@ -39,14 +50,15 @@
|
|||
User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
|
||||
well the computed digest.
|
||||
|
||||
(##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
|
||||
(##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
|
||||
except for the last one.
|
||||
User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
|
||||
well the computed digest.
|
||||
|
||||
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
|
||||
|
||||
(+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
|
||||
(+++) HASH processing: once initialization is done, MDMAT bit must be set through
|
||||
__HAL_HASH_SET_MDMAT() macro.
|
||||
From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
|
||||
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
|
||||
macro then wrap-up the HASH processing in feeding the last input buffer through the
|
||||
|
|
@ -68,25 +80,12 @@
|
|||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
|
||||
|
||||
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -107,8 +106,8 @@
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
|
||||
* @brief HASH extended processing functions using polling mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using polling mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Polling mode HASH extended processing functions #####
|
||||
|
|
@ -147,7 +146,8 @@
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
|
@ -172,9 +172,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param Size length of the input buffer in bytes, must be a multiple of 4.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -187,7 +187,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
|
@ -203,7 +204,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
|
@ -228,9 +230,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param Size length of the input buffer in bytes, must be a multiple of 4.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -243,7 +245,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Timeout Timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
|
@ -253,8 +256,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
|
||||
* @brief HASH extended processing functions using interrupt mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using interrupt mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interruption mode HASH extended processing functions #####
|
||||
|
|
@ -285,9 +288,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -308,9 +312,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes, must be a multiple of 4.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -322,9 +326,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -337,9 +343,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -360,9 +367,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes, must be a multiple of 4.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -374,9 +381,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
|
||||
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -384,8 +393,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
||||
* @brief HASH extended processing functions using DMA mode.
|
||||
*
|
||||
* @brief HASH extended processing functions using DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA mode HASH extended processing functions #####
|
||||
|
|
@ -413,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
|
||||
* to feed the input buffer to the Peripheral.
|
||||
|
|
@ -425,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
|
@ -440,9 +447,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -455,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
|
@ -470,9 +477,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
return HASH_Finish(hhash, pOutBuffer, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -480,8 +487,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @brief HMAC extended processing functions using polling mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using polling mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Polling mode HMAC extended processing functions #####
|
||||
|
|
@ -498,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
|
||||
* read the computed digest.
|
||||
|
|
@ -512,7 +518,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
|
@ -530,7 +537,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param Timeout Timeout value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout)
|
||||
{
|
||||
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
|
@ -541,8 +549,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
|
||||
* @brief HMAC extended processing functions using interruption mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using interruption mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupt mode HMAC extended processing functions #####
|
||||
|
|
@ -559,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
|
||||
* read the computed digest in interrupt mode.
|
||||
|
|
@ -572,7 +579,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
|
@ -589,22 +597,21 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer)
|
||||
{
|
||||
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
|
||||
* @brief HMAC extended processing functions using DMA mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions using DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA mode HMAC extended processing functions #####
|
||||
|
|
@ -626,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
|
||||
* DMA transfers to feed the key and the input buffer to the Peripheral.
|
||||
|
|
@ -646,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
}
|
||||
|
|
@ -670,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
}
|
||||
|
|
@ -681,8 +687,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
|
||||
* @brief HMAC extended processing functions in multi-buffer DMA mode.
|
||||
*
|
||||
* @brief HMAC extended processing functions in multi-buffer DMA mode.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Multi-buffer DMA mode HMAC extended processing functions #####
|
||||
|
|
@ -746,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = SET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
|
||||
|
|
@ -767,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
if (hhash->DigestCalculationDisable != SET)
|
||||
{
|
||||
|
|
@ -793,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = RESET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
|
||||
|
|
@ -816,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = SET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
|
||||
|
|
@ -837,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
if (hhash->DigestCalculationDisable != SET)
|
||||
{
|
||||
|
|
@ -863,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = RESET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
|
||||
|
|
@ -885,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = SET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
|
|
@ -906,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
if (hhash->DigestCalculationDisable != SET)
|
||||
{
|
||||
|
|
@ -932,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = RESET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
|
||||
|
|
@ -954,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = SET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
|
|
@ -975,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
|
||||
{
|
||||
if (hhash->DigestCalculationDisable != SET)
|
||||
{
|
||||
|
|
@ -1001,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @param Size length of the input buffer in bytes.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size)
|
||||
{
|
||||
hhash->DigestCalculationDisable = RESET;
|
||||
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
|
||||
|
|
@ -1025,6 +1035,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -6,13 +6,12 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
|
@ -22,7 +21,7 @@
|
|||
#define STM32H7xx_HAL_HASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
|
@ -51,12 +50,16 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -66,12 +69,18 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -80,10 +89,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -92,8 +101,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
|
|||
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -102,8 +113,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
|
||||
uint8_t *pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -113,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -124,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
|
|||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
|
||||
uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -162,4 +179,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
|
|||
|
||||
#endif /* STM32H7xx_HAL_HASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue