mirror of https://github.com/ARMmbed/mbed-os.git
Update STM32H5 HAL driver, fix some DMA bugs (#344)
* Update STM32H5 HAL driver, fix some DMA bugs * Disable LL driver * Add scancode ignore rulespull/15530/head
Jamie Smith
GitHub
parent
2bc173e3f7
commit
f2a128b895
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@ -0,0 +1,79 @@
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/**
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******************************************************************************
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* @file partition_stm32h5xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32H5xx Device Header File for Initial Setup for Secure /
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* Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
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* Template.
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*
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* The file is included in system_stm32h5xx_s.c in secure application.
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* It includes the configuration section that allows to select the
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* STM32H5xx device partitioning file for system core secure attributes
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* and interrupt secure and non-secure assignment.
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*
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******************************************************************************
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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* Copyright (c) 2023 STMicroelectronics. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32h5xx
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* @{
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*/
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#ifndef PARTITION_STM32H5XX_H
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#define PARTITION_STM32H5XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Secure_configuration_section
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* @{
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*/
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#if defined(STM32H573xx)
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#include "partition_stm32h573xx.h"
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#elif defined(STM32H563xx)
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#include "partition_stm32h563xx.h"
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#elif defined(STM32H562xx)
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#include "partition_stm32h562xx.h"
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#elif defined(STM32H533xx)
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#include "partition_stm32h533xx.h"
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#elif defined(STM32H523xx)
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#include "partition_stm32h523xx.h"
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#else
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#error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)"
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#endif
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* PARTITION_STM32H5XX_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,4 @@
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/**
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/**
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******************************************************************************
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* @file stm32h562xx.h
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* @author MCD Application Team
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@ -7,7 +7,7 @@
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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* - Macros to access peripheral's registers hardware
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*
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******************************************************************************
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* @attention
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@ -176,6 +176,7 @@ typedef enum
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DTS_IRQn = 113, /*!< DTS global interrupt */
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RNG_IRQn = 114, /*!< RNG global interrupt */
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HASH_IRQn = 117, /*!< HASH global interrupt */
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PKA_IRQn = 118, /*!< PKA global interrupt */
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CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */
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TIM12_IRQn = 120, /*!< TIM12 global interrupt */
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TIM13_IRQn = 121, /*!< TIM13 global interrupt */
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@ -396,7 +397,7 @@ typedef struct
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__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
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__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
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__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
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uint32_t RESERVED;
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__IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */
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__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
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} RNG_TypeDef;
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@ -627,6 +628,7 @@ typedef struct
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__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
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__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
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} FMAC_TypeDef;
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/**
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* @brief General Purpose I/O
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*/
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@ -773,7 +775,8 @@ typedef struct
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__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
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__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
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__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
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uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */
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__IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */
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uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
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__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
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__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
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} TIM_TypeDef;
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@ -975,6 +978,18 @@ typedef struct
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__IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */
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} RCC_TypeDef;
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/**
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* @brief PKA
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */
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__IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */
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__IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */
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uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */
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__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */
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} PKA_TypeDef;
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/*
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* @brief RTC Specific device feature definitions
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*/
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@ -1692,11 +1707,11 @@ typedef struct
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#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL)
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#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL)
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#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL)
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#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
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#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
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#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
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#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL)
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#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL)
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/*!< APB3 Non secure peripherals */
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#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
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@ -1718,10 +1733,10 @@ typedef struct
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#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL)
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#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL)
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#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL)
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/*!< AHB4 Non secure peripherals */
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#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL)
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#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL)
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#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */
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#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */
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#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL)
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@ -1734,9 +1749,9 @@ typedef struct
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/* Flash, Peripheral and internal SRAMs base addresses - Secure */
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#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */
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#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */
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#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */
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#define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */
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#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (512 KB) secure base address */
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#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */
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#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
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/* Peripheral memory map - Secure */
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#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
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#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL)
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#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL)
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#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL)
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#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL)
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#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL)
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#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL)
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#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL)
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#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL)
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#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S)
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#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL)
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#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL)
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#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
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#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
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#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL)
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#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL)
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#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL)
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/*!< APB3 secure peripherals */
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#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL)
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/*!< AHB4 secure peripherals */
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#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL)
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#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL)
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#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */
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#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */
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#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL)
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@ -1900,12 +1914,10 @@ typedef struct
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/* Debug MCU registers base address */
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#define DBGMCU_BASE (0x44024000UL)
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#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */
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#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
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#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */
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/* Internal Flash OTP Area */
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#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
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#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */
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@ -1948,9 +1960,6 @@ typedef struct
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#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */
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#endif /* CMSE */
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/*!< USB PMA SIZE */
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#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */
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/*!< Root Secure Service Library */
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/************ RSSLIB SAU system Flash region definition constants *************/
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#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL)
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#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
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#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
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#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
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#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS)
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/*!< APB3 Non secure peripherals */
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@ -2378,6 +2388,7 @@ typedef struct
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#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
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#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
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#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
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#define PKA_S ((PKA_TypeDef *) PKA_BASE_S)
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/*!< APB3 secure peripherals */
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#define SBS_S ((SBS_TypeDef *) SBS_BASE_S)
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@ -2791,6 +2802,9 @@ typedef struct
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#define RNG RNG_S
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#define RNG_BASE RNG_BASE_S
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#define PKA PKA_S
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#define PKA_BASE PKA_BASE_S
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#define PKA_RAM_BASE PKA_RAM_BASE_S
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#define SDMMC1 SDMMC1_S
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@ -3197,6 +3211,10 @@ typedef struct
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#define RNG RNG_NS
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#define RNG_BASE RNG_BASE_NS
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#define PKA PKA_NS
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#define PKA_BASE PKA_BASE_NS
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#define PKA_RAM_BASE PKA_RAM_BASE_NS
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#define SDMMC1 SDMMC1_NS
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@ -4479,11 +4497,36 @@ typedef struct
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#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
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#define RNG_SR_SEIS RNG_SR_SEIS_Msk
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/******************** Bits definition for RNG_NSCR register *******************/
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#define RNG_NSCR_EN_OSC1_Pos (0U)
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#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
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#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk
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#define RNG_NSCR_EN_OSC2_Pos (3U)
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#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
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#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk
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#define RNG_NSCR_EN_OSC3_Pos (6U)
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#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
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#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk
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#define RNG_NSCR_EN_OSC4_Pos (9U)
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#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
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#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk
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#define RNG_NSCR_EN_OSC5_Pos (12U)
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#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
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#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk
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#define RNG_NSCR_EN_OSC6_Pos (15U)
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#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
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#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk
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/******************** Bits definition for RNG_HTCR register *******************/
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#define RNG_HTCR_HTCFG_Pos (0U)
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#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
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#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
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/******************** RNG Nist Compliance Values ******************************/
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#define RNG_CR_NIST_VALUE (0x00F00E00U)
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#define RNG_HTCR_NIST_VALUE (0x6A91U)
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#define RNG_NSCR_NIST_VALUE (0x3AF66U)
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/******************************************************************************/
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/* */
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/* Digital to Analog Converter */
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@ -6241,32 +6284,32 @@ typedef struct
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#define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */
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/****************** Bit definition for EXTI_RTSR2 register *******************/
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#define EXTI_RTSR2_TR_Pos (14U)
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#define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */
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#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
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#define EXTI_RTSR2_TR46_Pos (14U)
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#define EXTI_RTSR2_TR46_Msk (0x1UL << EXTI_RTSR2_TR46_Pos) /*!< 0x00004000 */
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#define EXTI_RTSR2_TR46 EXTI_RTSR2_TR46_Msk /*!< Rising trigger event configuration bit of line 46 */
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#define EXTI_RTSR2_TR50_Pos (18U)
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#define EXTI_RTSR2_TR50_Msk (0x1UL << EXTI_RTSR2_TR50_Pos) /*!< 0x00040000 */
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#define EXTI_RTSR2_TR50 EXTI_RTSR2_TR50_Msk /*!< Rising trigger event configuration bit of line 50 */
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#define EXTI_RTSR2_TR53_Pos (21U)
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#define EXTI_RTSR2_TR53_Msk (0x1UL << EXTI_RTSR2_TR53_Pos) /*!< 0x00200000 */
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#define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */
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#define EXTI_RTSR2_RT_Pos (12U)
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#define EXTI_RTSR2_RT_Msk (0x244UL << EXTI_RTSR2_RT_Pos) /*!< 0x00244000 */
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#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */
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#define EXTI_RTSR2_RT46_Pos (14U)
|
||||
#define EXTI_RTSR2_RT46_Msk (0x1UL << EXTI_RTSR2_RT46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_RTSR2_RT46 EXTI_RTSR2_RT46_Msk /*!< Rising trigger event configuration bit of line 46 */
|
||||
#define EXTI_RTSR2_RT50_Pos (18U)
|
||||
#define EXTI_RTSR2_RT50_Msk (0x1UL << EXTI_RTSR2_RT50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_RTSR2_RT50 EXTI_RTSR2_RT50_Msk /*!< Rising trigger event configuration bit of line 50 */
|
||||
#define EXTI_RTSR2_RT53_Pos (21U)
|
||||
#define EXTI_RTSR2_RT53_Msk (0x1UL << EXTI_RTSR2_RT53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_RTSR2_RT53 EXTI_RTSR2_RT53_Msk /*!< Rising trigger event configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register *******************/
|
||||
#define EXTI_FTSR2_TR_Pos (14U)
|
||||
#define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
|
||||
#define EXTI_FTSR2_TR46_Pos (14U)
|
||||
#define EXTI_FTSR2_TR46_Msk (0x1UL << EXTI_FTSR2_TR46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR2_TR46 EXTI_FTSR2_TR46_Msk /*!< Falling trigger event configuration bit of line 46 */
|
||||
#define EXTI_FTSR2_TR50_Pos (18U)
|
||||
#define EXTI_FTSR2_TR50_Msk (0x1UL << EXTI_FTSR2_TR50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR2_TR50 EXTI_FTSR2_TR50_Msk /*!< Falling trigger event configuration bit of line 50 */
|
||||
#define EXTI_FTSR2_TR53_Pos (21U)
|
||||
#define EXTI_FTSR2_TR53_Msk (0x1UL << EXTI_FTSR2_TR53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_FTSR2_TR53 EXTI_FTSR2_TR53_Msk /*!< Falling trigger event configuration bit of line 53 */
|
||||
#define EXTI_FTSR2_FT_Pos (12U)
|
||||
#define EXTI_FTSR2_FT_Msk (0x244 << EXTI_FTSR2_FT_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */
|
||||
#define EXTI_FTSR2_FT46_Pos (14U)
|
||||
#define EXTI_FTSR2_FT46_Msk (0x1UL << EXTI_FTSR2_FT46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR2_FT46 EXTI_FTSR2_FT46_Msk /*!< Falling trigger event configuration bit of line 46 */
|
||||
#define EXTI_FTSR2_FT50_Pos (18U)
|
||||
#define EXTI_FTSR2_FT50_Msk (0x1UL << EXTI_FTSR2_FT50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR2_FT50 EXTI_FTSR2_FT50_Msk /*!< Falling trigger event configuration bit of line 50 */
|
||||
#define EXTI_FTSR2_FT53_Pos (21U)
|
||||
#define EXTI_FTSR2_FT53_Msk (0x1UL << EXTI_FTSR2_FT53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_FTSR2_FT53 EXTI_FTSR2_FT53_Msk /*!< Falling trigger event configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register ******************/
|
||||
#define EXTI_SWIER2_SWIER46_Pos (14U)
|
||||
|
|
@ -6280,7 +6323,7 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_RPR2 register *******************/
|
||||
#define EXTI_RPR2_RPIF_Pos (14U)
|
||||
#define EXTI_RPR2_RPIF_Pos (12U)
|
||||
#define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */
|
||||
#define EXTI_RPR2_RPIF46_Pos (14U)
|
||||
|
|
@ -6294,7 +6337,7 @@ typedef struct
|
|||
#define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_FPR2 register *******************/
|
||||
#define EXTI_FPR2_FPIF_Pos (14U)
|
||||
#define EXTI_FPR2_FPIF_Pos (12U)
|
||||
#define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */
|
||||
#define EXTI_FPR2_FPIF46_Pos (14U)
|
||||
|
|
@ -6837,6 +6880,9 @@ typedef struct
|
|||
#define EXTI_IMR2_IM44_Pos (12U)
|
||||
#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
|
||||
#define EXTI_IMR2_IM45_Pos (13U)
|
||||
#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
|
||||
#define EXTI_IMR2_IM46_Pos (14U)
|
||||
#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
|
||||
|
|
@ -6918,6 +6964,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM44_Pos (12U)
|
||||
#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
|
||||
#define EXTI_EMR2_EM45_Pos (13U)
|
||||
#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
|
||||
#define EXTI_EMR2_EM46_Pos (14U)
|
||||
#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
|
||||
|
|
@ -7676,7 +7725,7 @@ typedef struct
|
|||
/* FLASH */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */
|
||||
#define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */
|
||||
#define FLASH_SIZE_DEFAULT (0x200000U) /*!< FLASH Size */
|
||||
#define FLASH_SECTOR_NB (128U) /*!< Flash Sector number */
|
||||
|
|
@ -7970,6 +8019,9 @@ typedef struct
|
|||
#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U)
|
||||
#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */
|
||||
#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */
|
||||
#define FLASH_OPTSR2_USBPD_DIS_Pos (8U)
|
||||
#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */
|
||||
#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */
|
||||
#define FLASH_OPTSR2_TZEN_Pos (24U)
|
||||
#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */
|
||||
#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */
|
||||
|
|
@ -8002,7 +8054,7 @@ typedef struct
|
|||
|
||||
/***************** Bits definition for FLASH_EDATA register ********************/
|
||||
#define FLASH_EDATAR_EDATA_STRT_Pos (0U)
|
||||
#define FLASH_EDATAR_EDATA_STRT_Msk (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000003 */
|
||||
#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */
|
||||
#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */
|
||||
#define FLASH_EDATAR_EDATA_EN_Pos (15U)
|
||||
#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -8050,7 +8102,6 @@ typedef struct
|
|||
#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */
|
||||
#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Filter Mathematical ACcelerator unit (FMAC) */
|
||||
|
|
@ -8166,7 +8217,6 @@ typedef struct
|
|||
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
|
||||
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Flexible Memory Controller */
|
||||
|
|
@ -8625,7 +8675,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -10386,27 +10436,27 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1_Pos (0U)
|
||||
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR2 register *******************/
|
||||
#define TIM_CCR2_CCR2_Pos (0U)
|
||||
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR3 register *******************/
|
||||
#define TIM_CCR3_CCR3_Pos (0U)
|
||||
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR4 register *******************/
|
||||
#define TIM_CCR4_CCR4_Pos (0U)
|
||||
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
|
|
@ -10420,7 +10470,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for TIM_CCR6 register *******************/
|
||||
#define TIM_CCR6_CCR6_Pos (0U)
|
||||
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
|
||||
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
|
||||
|
||||
/******************* Bit definition for TIM_BDTR register *******************/
|
||||
|
|
@ -10565,6 +10615,11 @@ typedef struct
|
|||
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<OCREF_CLR source selection */
|
||||
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
|
||||
|
||||
/******************* Bit definition for TIM_OR1 register *********************/
|
||||
#define TIM_OR1_RTCPREEN_Pos (1U)
|
||||
#define TIM_OR1_RTCPREEN_Msk (0x1UL << TIM_OR1_RTCPREEN_Pos) /*!< 0x00000002 */
|
||||
#define TIM_OR1_RTCPREEN TIM_OR1_RTCPREEN_Msk /*!< RTCPRE HSE divider enable */
|
||||
|
||||
/******************* Bit definition for TIM_TISEL register *********************/
|
||||
#define TIM_TISEL_TI1SEL_Pos (0U)
|
||||
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -11915,7 +11970,7 @@ typedef struct
|
|||
#define OCTOSPI_CR_TCIE_Msk XSPI_CR_TCIE_Msk /*!< 0x00020000 */
|
||||
#define OCTOSPI_CR_TCIE XSPI_CR_TCIE /*!< Transfer Complete Interrupt Enable */
|
||||
#define OCTOSPI_CR_FTIE_Pos XSPI_CR_FTIE_Pos
|
||||
#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk) /*!< 0x00040000 */
|
||||
#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk /*!< 0x00040000 */
|
||||
#define OCTOSPI_CR_FTIE XSPI_CR_FTIE /*!< FIFO Threshold Interrupt Enable */
|
||||
#define OCTOSPI_CR_SMIE_Pos XSPI_CR_SMIE_Pos
|
||||
#define OCTOSPI_CR_SMIE_Msk XSPI_CR_SMIE_Msk /*!< 0x00080000 */
|
||||
|
|
@ -12372,9 +12427,9 @@ typedef struct
|
|||
#define PWR_PMCR_AVD_READY_Pos (13U)
|
||||
#define PWR_PMCR_AVD_READY_Msk (0x1UL << PWR_PMCR_AVD_READY_Pos)
|
||||
#define PWR_PMCR_AVD_READY PWR_PMCR_AVD_READY_Msk
|
||||
#define PWR_PMCR_ETHERNETSO_Pos (16U)
|
||||
#define PWR_PMCR_ETHERNETSO_Msk (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
|
||||
#define PWR_PMCR_ETHERNETSO PWR_PMCR_ETHERNETSO_Msk
|
||||
#define PWR_PMCR_ETHERNETSO_Pos (16U)
|
||||
#define PWR_PMCR_ETHERNETSO_Msk (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
|
||||
#define PWR_PMCR_ETHERNETSO PWR_PMCR_ETHERNETSO_Msk
|
||||
#define PWR_PMCR_SRAM3SO_Pos (23U)
|
||||
#define PWR_PMCR_SRAM3SO_Msk (0x1UL << PWR_PMCR_SRAM3SO_Pos)
|
||||
#define PWR_PMCR_SRAM3SO PWR_PMCR_SRAM3SO_Msk
|
||||
|
|
@ -12472,9 +12527,9 @@ typedef struct
|
|||
#define PWR_SCCR_SMPSEN PWR_SCCR_SMPSEN_Msk
|
||||
|
||||
/******************** Bit definition for PWR_VMCR register ******************/
|
||||
#define PWR_VMCR_PVDEN_Pos (0U)
|
||||
#define PWR_VMCR_PVDEN_Msk (0x1UL << PWR_VMCR_PVDEN_Pos)
|
||||
#define PWR_VMCR_PVDEN PWR_VMCR_PVDEN_Msk
|
||||
#define PWR_VMCR_PVDEN_Pos (0U)
|
||||
#define PWR_VMCR_PVDEN_Msk (0x1UL << PWR_VMCR_PVDEN_Pos)
|
||||
#define PWR_VMCR_PVDEN PWR_VMCR_PVDEN_Msk
|
||||
#define PWR_VMCR_PLS_Pos (1U)
|
||||
#define PWR_VMCR_PLS_Msk (0x7UL << PWR_VMCR_PLS_Pos)
|
||||
#define PWR_VMCR_PLS PWR_VMCR_PLS_Msk
|
||||
|
|
@ -12491,12 +12546,12 @@ typedef struct
|
|||
#define PWR_VMCR_ALS_1 (0x2UL << PWR_VMCR_ALS_Pos)
|
||||
|
||||
/******************** Bit definition for PWR_USBSCR register ******************/
|
||||
#define PWR_USBSCR_USB33DEN_Pos (24U)
|
||||
#define PWR_USBSCR_USB33DEN_Msk (0x1UL << PWR_USBSCR_USB33DEN_Pos)
|
||||
#define PWR_USBSCR_USB33DEN PWR_USBSCR_USB33DEN_Msk
|
||||
#define PWR_USBSCR_USB33SV_Pos (25U)
|
||||
#define PWR_USBSCR_USB33SV_Msk (0x1UL << PWR_USBSCR_USB33SV_Pos)
|
||||
#define PWR_USBSCR_USB33SV PWR_USBSCR_USB33SV_Msk
|
||||
#define PWR_USBSCR_USB33DEN_Pos (24U)
|
||||
#define PWR_USBSCR_USB33DEN_Msk (0x1UL << PWR_USBSCR_USB33DEN_Pos)
|
||||
#define PWR_USBSCR_USB33DEN PWR_USBSCR_USB33DEN_Msk
|
||||
#define PWR_USBSCR_USB33SV_Pos (25U)
|
||||
#define PWR_USBSCR_USB33SV_Msk (0x1UL << PWR_USBSCR_USB33SV_Pos)
|
||||
#define PWR_USBSCR_USB33SV PWR_USBSCR_USB33SV_Msk
|
||||
|
||||
/******************** Bit definition for PWR_VMSR register ******************/
|
||||
#define PWR_VMSR_AVDO_Pos (19U)
|
||||
|
|
@ -13702,6 +13757,9 @@ typedef struct
|
|||
#define RCC_AHB2RSTR_RNGRST_Pos (18U)
|
||||
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
|
||||
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
|
||||
#define RCC_AHB2RSTR_PKARST_Pos (19U)
|
||||
#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00080000 */
|
||||
#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk
|
||||
|
||||
/******************** Bit definition for RCC_AHB4RSTR register **************/
|
||||
#define RCC_AHB4RSTR_SDMMC1RST_Pos (11U)
|
||||
|
|
@ -13968,6 +14026,9 @@ typedef struct
|
|||
#define RCC_AHB2ENR_RNGEN_Pos (18U)
|
||||
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
|
||||
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
|
||||
#define RCC_AHB2ENR_PKAEN_Pos (19U)
|
||||
#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00080000 */
|
||||
#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk
|
||||
#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
|
||||
|
|
@ -16929,9 +16990,6 @@ typedef struct
|
|||
#define SBS_SECCFGR_FPUSEC_Pos (3U)
|
||||
#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */
|
||||
#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN_Pos (31U)
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN_Msk (0x1UL << SBS_SECCFGR_SDCE_SEC_EN_Pos) /*!< 0x80000000 */
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN SBS_SECCFGR_SDCE_SEC_EN_Msk /*!< SMPS SBS security enable */
|
||||
|
||||
/****************** Bit definition for SBS_CNSLCKR register **************/
|
||||
#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U)
|
||||
|
|
@ -16989,7 +17047,7 @@ typedef struct
|
|||
#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
|
||||
|
||||
/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/
|
||||
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/
|
||||
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/
|
||||
|
||||
/*************** Bits definition for register x=1 (TZSC1) *************/
|
||||
#define GTZC_CFGR1_TIM2_Pos (0U)
|
||||
|
|
@ -17057,7 +17115,6 @@ typedef struct
|
|||
#define GTZC_CFGR1_LPTIM2_Pos (31U)
|
||||
#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
|
||||
|
||||
|
||||
/*************** Bits definition for register x=2 (TZSC1) *************/
|
||||
#define GTZC_CFGR2_FDCAN1_Pos (0U)
|
||||
#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos)
|
||||
|
|
@ -17145,6 +17202,7 @@ typedef struct
|
|||
#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos)
|
||||
#define GTZC_CFGR4_FLASH_REG_Pos (3U)
|
||||
#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
|
||||
|
||||
#define GTZC_CFGR4_SBS_Pos (6U)
|
||||
#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos)
|
||||
#define GTZC_CFGR4_RTC_Pos (7U)
|
||||
|
|
@ -17246,12 +17304,11 @@ typedef struct
|
|||
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos
|
||||
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -17325,6 +17382,7 @@ typedef struct
|
|||
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos
|
||||
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/
|
||||
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk
|
||||
|
|
@ -17394,8 +17452,8 @@ typedef struct
|
|||
/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/
|
||||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -17538,8 +17596,8 @@ typedef struct
|
|||
/******************* Bits definition for GTZC_TZIC_IER2 register ***************/
|
||||
#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_IER2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_IER2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -17581,7 +17639,6 @@ typedef struct
|
|||
#define GTZC_TZIC1_IER2_LPTIM5_Pos GTZC_CFGR2_LPTIM5_Pos
|
||||
#define GTZC_TZIC1_IER2_LPTIM5_Msk GTZC_CFGR2_LPTIM5_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZIC_IER3 register ***************/
|
||||
#define GTZC_TZIC1_IER3_LPTIM6_Pos GTZC_CFGR3_LPTIM6_Pos
|
||||
#define GTZC_TZIC1_IER3_LPTIM6_Msk GTZC_CFGR3_LPTIM6_Msk
|
||||
|
|
@ -17727,8 +17784,8 @@ typedef struct
|
|||
/******************* Bits definition for GTZC_TZIC_SR2 register **************/
|
||||
#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_SR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_SR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -17915,8 +17972,8 @@ typedef struct
|
|||
/******************* Bits definition for GTZC_TZIC_FCR2 register **************/
|
||||
#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_FCR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_FCR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -18482,6 +18539,7 @@ typedef struct
|
|||
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USART_DMAREQUESTS_SW_WA
|
||||
/****************** Bit definition for USART_CR1 register *******************/
|
||||
#define USART_CR1_UE_Pos (0U)
|
||||
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -19806,6 +19864,15 @@ typedef struct
|
|||
#define I3C_BCR_BCR2_Pos (2U)
|
||||
#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */
|
||||
#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */
|
||||
#define I3C_BCR_BCR3_Pos (3U)
|
||||
#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */
|
||||
#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */
|
||||
#define I3C_BCR_BCR4_Pos (4U)
|
||||
#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */
|
||||
#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */
|
||||
#define I3C_BCR_BCR5_Pos (5U)
|
||||
#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */
|
||||
#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */
|
||||
#define I3C_BCR_BCR6_Pos (6U)
|
||||
#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */
|
||||
#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */
|
||||
|
|
@ -20678,6 +20745,327 @@ typedef struct
|
|||
#define USB_PMA_RXBD_ADDMSK (0xFFFF0000UL)
|
||||
#define USB_PMA_RXBD_COUNTMSK (0x03FFFFFFUL)
|
||||
|
||||
/*!< USB PMA SIZE */
|
||||
#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */
|
||||
|
||||
#define USB_DRD_FS_EP_NBR (8U) /*!< Number of USB Device endpoints */
|
||||
#define USB_DRD_FS_CH_NBR (8U) /*!< Number of USB Host channels */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Public Key Accelerator (PKA) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************* Bit definition for PKA_CR register *********************/
|
||||
#define PKA_CR_EN_Pos (0U)
|
||||
#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */
|
||||
#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */
|
||||
#define PKA_CR_START_Pos (1U)
|
||||
#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */
|
||||
#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */
|
||||
#define PKA_CR_MODE_Pos (8U)
|
||||
#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */
|
||||
#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */
|
||||
#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */
|
||||
#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */
|
||||
#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */
|
||||
#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */
|
||||
#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */
|
||||
#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */
|
||||
#define PKA_CR_PROCENDIE_Pos (17U)
|
||||
#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */
|
||||
#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */
|
||||
#define PKA_CR_RAMERRIE_Pos (19U)
|
||||
#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */
|
||||
#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */
|
||||
#define PKA_CR_ADDRERRIE_Pos (20U)
|
||||
#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */
|
||||
#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< Address error interrupt enable */
|
||||
#define PKA_CR_OPERRIE_Pos (21U)
|
||||
#define PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) /*!< 0x00200000 */
|
||||
#define PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk /*!< Operation Error interrupt enable */
|
||||
|
||||
/******************* Bit definition for PKA_SR register *********************/
|
||||
#define PKA_SR_INITOK_Pos (0U)
|
||||
#define PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) /*!< 0x00000001 */
|
||||
#define PKA_SR_INITOK PKA_SR_INITOK_Msk /*!< PKA initialisation flag */
|
||||
#define PKA_SR_BUSY_Pos (16U)
|
||||
#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */
|
||||
#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */
|
||||
#define PKA_SR_PROCENDF_Pos (17U)
|
||||
#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */
|
||||
#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */
|
||||
#define PKA_SR_RAMERRF_Pos (19U)
|
||||
#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */
|
||||
#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */
|
||||
#define PKA_SR_ADDRERRF_Pos (20U)
|
||||
#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */
|
||||
#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */
|
||||
#define PKA_SR_OPERRF_Pos (21U)
|
||||
#define PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) /*!< 0x00200000 */
|
||||
#define PKA_SR_OPERRF PKA_SR_OPERRF_Msk /*!< PKA operation Error flag*/
|
||||
|
||||
/******************* Bit definition for PKA_CLRFR register ******************/
|
||||
#define PKA_CLRFR_PROCENDFC_Pos (17U)
|
||||
#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */
|
||||
#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */
|
||||
#define PKA_CLRFR_RAMERRFC_Pos (19U)
|
||||
#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */
|
||||
#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */
|
||||
#define PKA_CLRFR_ADDRERRFC_Pos (20U)
|
||||
#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */
|
||||
#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */
|
||||
#define PKA_CLRFR_OPERRFC_Pos (21U)
|
||||
#define PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) /*!< 0x00200000 */
|
||||
#define PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk /*!< Clear PKA operation Error flag*/
|
||||
|
||||
/******************* Bits definition for PKA RAM *************************/
|
||||
#define PKA_RAM_OFFSET (0x0400UL) /*!< PKA RAM address offset */
|
||||
|
||||
/* Compute Montgomery parameter input data */
|
||||
#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
|
||||
/* Compute Montgomery parameter output data */
|
||||
#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */
|
||||
|
||||
/* Compute modular exponentiation input data */
|
||||
#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
|
||||
#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
|
||||
#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
|
||||
#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */
|
||||
#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */
|
||||
|
||||
/* Compute modular exponentiation output data */
|
||||
#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */
|
||||
#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */
|
||||
#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */
|
||||
#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */
|
||||
|
||||
/* Compute ECC scalar multiplication input data */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */
|
||||
|
||||
/* Compute ECC scalar multiplication output data */
|
||||
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
|
||||
|
||||
/* Point check input data */
|
||||
#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
|
||||
#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
|
||||
|
||||
/* Point check output data */
|
||||
#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
|
||||
|
||||
/* ECDSA signature input data */
|
||||
#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
|
||||
#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
|
||||
#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */
|
||||
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
|
||||
#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */
|
||||
#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
|
||||
|
||||
/* ECDSA signature output data */
|
||||
#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
|
||||
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */
|
||||
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */
|
||||
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */
|
||||
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */
|
||||
|
||||
|
||||
/* ECDSA verification input data */
|
||||
#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
|
||||
#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */
|
||||
#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */
|
||||
#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
|
||||
#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
|
||||
|
||||
/* ECDSA verification output data */
|
||||
#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* RSA CRT exponentiation input data */
|
||||
#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */
|
||||
#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */
|
||||
#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */
|
||||
#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */
|
||||
#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */
|
||||
#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */
|
||||
#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
|
||||
|
||||
/* RSA CRT exponentiation output data */
|
||||
#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular reduction input data */
|
||||
#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */
|
||||
#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */
|
||||
#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */
|
||||
#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
|
||||
/* Modular reduction output data */
|
||||
#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Arithmetic addition input data */
|
||||
#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Arithmetic addition output data */
|
||||
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Arithmetic subtraction input data */
|
||||
#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Arithmetic subtraction output data */
|
||||
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Arithmetic multiplication input data */
|
||||
#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Arithmetic multiplication output data */
|
||||
#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Comparison input data */
|
||||
#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Comparison output data */
|
||||
#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular addition input data */
|
||||
#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */
|
||||
|
||||
/* Modular addition output data */
|
||||
#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular inversion input data */
|
||||
#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */
|
||||
|
||||
/* Modular inversion output data */
|
||||
#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular subtraction input data */
|
||||
#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
|
||||
|
||||
/* Modular subtraction output data */
|
||||
#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Montgomery multiplication input data */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
|
||||
/* Montgomery multiplication output data */
|
||||
#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Generic Arithmetic input data */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Generic Arithmetic output data */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */
|
||||
|
||||
/* Compute ECC complete addition input data */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
|
||||
|
||||
/* Compute ECC complete addition output data */
|
||||
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */
|
||||
|
||||
/* Compute ECC double base ladder input data */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
|
||||
|
||||
/* Compute ECC double base ladder output data */
|
||||
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */
|
||||
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */
|
||||
#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
|
||||
|
||||
/* Compute ECC projective to affine conversion input data */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
|
||||
|
||||
/* Compute ECC projective to affine conversion output data */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
|
||||
|
||||
|
||||
/** @addtogroup STM32H5xx_Peripheral_Exported_macros
|
||||
* @{
|
||||
|
|
@ -20695,6 +21083,8 @@ typedef struct
|
|||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \
|
||||
((INSTANCE) == ADC12_COMMON_S))
|
||||
/******************************* PKA Instances ********************************/
|
||||
#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))
|
||||
|
||||
/******************************* CORDIC Instances *****************************/
|
||||
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
|
||||
|
|
@ -20738,6 +21128,11 @@ typedef struct
|
|||
((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S))
|
||||
|
||||
#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \
|
||||
((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S))
|
||||
|
||||
/****************************** RAMCFG Instances ********************************/
|
||||
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \
|
||||
((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \
|
||||
|
|
@ -21261,6 +21656,9 @@ typedef struct
|
|||
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
|
||||
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
|
||||
|
||||
/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/
|
||||
#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
|
||||
|
||||
/****************** TIM Instances : Advanced timer instances *******************/
|
||||
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
|
||||
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
|
||||
|
|
@ -21458,7 +21856,6 @@ typedef struct
|
|||
/******************************* USB DRD FS PCD Instances *************************/
|
||||
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))
|
||||
|
||||
|
||||
/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
|
||||
|
||||
/** @} */ /* End of group STM32H562xx */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/**
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h563xx.h
|
||||
* @author MCD Application Team
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
* - Peripheral's registers declarations and bits definition
|
||||
* - Macros to access peripheral’s registers hardware
|
||||
* - Macros to access peripheral's registers hardware
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -181,6 +181,7 @@ typedef enum
|
|||
DTS_IRQn = 113, /*!< DTS global interrupt */
|
||||
RNG_IRQn = 114, /*!< RNG global interrupt */
|
||||
HASH_IRQn = 117, /*!< HASH global interrupt */
|
||||
PKA_IRQn = 118, /*!< PKA global interrupt */
|
||||
CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */
|
||||
TIM12_IRQn = 120, /*!< TIM12 global interrupt */
|
||||
TIM13_IRQn = 121, /*!< TIM13 global interrupt */
|
||||
|
|
@ -401,7 +402,7 @@ typedef struct
|
|||
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
|
||||
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
|
||||
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
|
||||
uint32_t RESERVED;
|
||||
__IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */
|
||||
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
|
||||
} RNG_TypeDef;
|
||||
|
||||
|
|
@ -805,6 +806,7 @@ typedef struct
|
|||
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
|
||||
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
|
||||
} FMAC_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief General Purpose I/O
|
||||
*/
|
||||
|
|
@ -951,7 +953,8 @@ typedef struct
|
|||
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
|
||||
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
|
||||
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
|
||||
uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */
|
||||
__IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */
|
||||
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
|
||||
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
|
||||
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
|
||||
} TIM_TypeDef;
|
||||
|
|
@ -1153,6 +1156,18 @@ typedef struct
|
|||
__IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */
|
||||
} RCC_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief PKA
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */
|
||||
__IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */
|
||||
__IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */
|
||||
uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */
|
||||
__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */
|
||||
} PKA_TypeDef;
|
||||
|
||||
/*
|
||||
* @brief RTC Specific device feature definitions
|
||||
*/
|
||||
|
|
@ -1873,11 +1888,11 @@ typedef struct
|
|||
#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL)
|
||||
#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL)
|
||||
#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL)
|
||||
|
||||
#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
|
||||
#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
|
||||
#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
|
||||
|
||||
#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL)
|
||||
#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL)
|
||||
|
||||
/*!< APB3 Non secure peripherals */
|
||||
#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
|
||||
|
|
@ -1899,12 +1914,12 @@ typedef struct
|
|||
#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL)
|
||||
#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL)
|
||||
#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL)
|
||||
|
||||
/*!< AHB4 Non secure peripherals */
|
||||
#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL)
|
||||
#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL)
|
||||
#define SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8C00UL)
|
||||
#define DLYB_SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8800UL)
|
||||
|
||||
#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */
|
||||
#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */
|
||||
#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL)
|
||||
|
|
@ -1917,9 +1932,9 @@ typedef struct
|
|||
|
||||
/* Flash, Peripheral and internal SRAMs base addresses - Secure */
|
||||
#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */
|
||||
#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */
|
||||
#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */
|
||||
#define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */
|
||||
#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (512 KB) secure base address */
|
||||
#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */
|
||||
#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
|
||||
|
||||
/* Peripheral memory map - Secure */
|
||||
|
|
@ -2006,7 +2021,6 @@ typedef struct
|
|||
#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
|
||||
#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL)
|
||||
#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL)
|
||||
|
||||
#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL)
|
||||
#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL)
|
||||
#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL)
|
||||
|
|
@ -2023,7 +2037,6 @@ typedef struct
|
|||
#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL)
|
||||
#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL)
|
||||
#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL)
|
||||
|
||||
#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S)
|
||||
#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL)
|
||||
#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL)
|
||||
|
|
@ -2048,6 +2061,8 @@ typedef struct
|
|||
#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
|
||||
#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
|
||||
#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL)
|
||||
#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL)
|
||||
#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL)
|
||||
|
||||
/*!< APB3 secure peripherals */
|
||||
#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL)
|
||||
|
|
@ -2075,7 +2090,6 @@ typedef struct
|
|||
#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL)
|
||||
#define SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8C00UL)
|
||||
#define DLYB_SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8800UL)
|
||||
|
||||
#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */
|
||||
#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */
|
||||
#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL)
|
||||
|
|
@ -2088,12 +2102,10 @@ typedef struct
|
|||
|
||||
/* Debug MCU registers base address */
|
||||
#define DBGMCU_BASE (0x44024000UL)
|
||||
|
||||
#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */
|
||||
#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
|
||||
#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */
|
||||
|
||||
|
||||
/* Internal Flash OTP Area */
|
||||
#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
|
||||
#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */
|
||||
|
|
@ -2136,9 +2148,6 @@ typedef struct
|
|||
#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */
|
||||
#endif /* CMSE */
|
||||
|
||||
/*!< USB PMA SIZE */
|
||||
#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */
|
||||
|
||||
/*!< Root Secure Service Library */
|
||||
/************ RSSLIB SAU system Flash region definition constants *************/
|
||||
#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL)
|
||||
|
|
@ -2424,6 +2433,7 @@ typedef struct
|
|||
#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
|
||||
#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
|
||||
#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
|
||||
#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS)
|
||||
|
||||
|
||||
/*!< APB3 Non secure peripherals */
|
||||
|
|
@ -2574,6 +2584,7 @@ typedef struct
|
|||
#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
|
||||
#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
|
||||
#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
|
||||
#define PKA_S ((PKA_TypeDef *) PKA_BASE_S)
|
||||
|
||||
/*!< APB3 secure peripherals */
|
||||
#define SBS_S ((SBS_TypeDef *) SBS_BASE_S)
|
||||
|
|
@ -2991,6 +3002,9 @@ typedef struct
|
|||
#define RNG RNG_S
|
||||
#define RNG_BASE RNG_BASE_S
|
||||
|
||||
#define PKA PKA_S
|
||||
#define PKA_BASE PKA_BASE_S
|
||||
#define PKA_RAM_BASE PKA_RAM_BASE_S
|
||||
|
||||
#define ETH ETH_S
|
||||
#define ETH_BASE ETH_BASE_S
|
||||
|
|
@ -3408,6 +3422,10 @@ typedef struct
|
|||
#define RNG RNG_NS
|
||||
#define RNG_BASE RNG_BASE_NS
|
||||
|
||||
#define PKA PKA_NS
|
||||
#define PKA_BASE PKA_BASE_NS
|
||||
#define PKA_RAM_BASE PKA_RAM_BASE_NS
|
||||
|
||||
|
||||
#define ETH ETH_NS
|
||||
#define ETH_BASE ETH_BASE_NS
|
||||
|
|
@ -4699,11 +4717,36 @@ typedef struct
|
|||
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
|
||||
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
|
||||
|
||||
/******************** Bits definition for RNG_NSCR register *******************/
|
||||
#define RNG_NSCR_EN_OSC1_Pos (0U)
|
||||
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
|
||||
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk
|
||||
#define RNG_NSCR_EN_OSC2_Pos (3U)
|
||||
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
|
||||
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk
|
||||
#define RNG_NSCR_EN_OSC3_Pos (6U)
|
||||
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
|
||||
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk
|
||||
#define RNG_NSCR_EN_OSC4_Pos (9U)
|
||||
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
|
||||
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk
|
||||
#define RNG_NSCR_EN_OSC5_Pos (12U)
|
||||
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
|
||||
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk
|
||||
#define RNG_NSCR_EN_OSC6_Pos (15U)
|
||||
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
|
||||
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk
|
||||
|
||||
/******************** Bits definition for RNG_HTCR register *******************/
|
||||
#define RNG_HTCR_HTCFG_Pos (0U)
|
||||
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
|
||||
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
|
||||
|
||||
/******************** RNG Nist Compliance Values ******************************/
|
||||
#define RNG_CR_NIST_VALUE (0x00F00E00U)
|
||||
#define RNG_HTCR_NIST_VALUE (0x6A91U)
|
||||
#define RNG_NSCR_NIST_VALUE (0x3AF66U)
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Digital to Analog Converter */
|
||||
|
|
@ -8325,32 +8368,32 @@ typedef struct
|
|||
#define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register *******************/
|
||||
#define EXTI_RTSR2_TR_Pos (14U)
|
||||
#define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
|
||||
#define EXTI_RTSR2_TR46_Pos (14U)
|
||||
#define EXTI_RTSR2_TR46_Msk (0x1UL << EXTI_RTSR2_TR46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_RTSR2_TR46 EXTI_RTSR2_TR46_Msk /*!< Rising trigger event configuration bit of line 46 */
|
||||
#define EXTI_RTSR2_TR50_Pos (18U)
|
||||
#define EXTI_RTSR2_TR50_Msk (0x1UL << EXTI_RTSR2_TR50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_RTSR2_TR50 EXTI_RTSR2_TR50_Msk /*!< Rising trigger event configuration bit of line 50 */
|
||||
#define EXTI_RTSR2_TR53_Pos (21U)
|
||||
#define EXTI_RTSR2_TR53_Msk (0x1UL << EXTI_RTSR2_TR53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */
|
||||
#define EXTI_RTSR2_RT_Pos (12U)
|
||||
#define EXTI_RTSR2_RT_Msk (0x244UL << EXTI_RTSR2_RT_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */
|
||||
#define EXTI_RTSR2_RT46_Pos (14U)
|
||||
#define EXTI_RTSR2_RT46_Msk (0x1UL << EXTI_RTSR2_RT46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_RTSR2_RT46 EXTI_RTSR2_RT46_Msk /*!< Rising trigger event configuration bit of line 46 */
|
||||
#define EXTI_RTSR2_RT50_Pos (18U)
|
||||
#define EXTI_RTSR2_RT50_Msk (0x1UL << EXTI_RTSR2_RT50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_RTSR2_RT50 EXTI_RTSR2_RT50_Msk /*!< Rising trigger event configuration bit of line 50 */
|
||||
#define EXTI_RTSR2_RT53_Pos (21U)
|
||||
#define EXTI_RTSR2_RT53_Msk (0x1UL << EXTI_RTSR2_RT53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_RTSR2_RT53 EXTI_RTSR2_RT53_Msk /*!< Rising trigger event configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register *******************/
|
||||
#define EXTI_FTSR2_TR_Pos (14U)
|
||||
#define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
|
||||
#define EXTI_FTSR2_TR46_Pos (14U)
|
||||
#define EXTI_FTSR2_TR46_Msk (0x1UL << EXTI_FTSR2_TR46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR2_TR46 EXTI_FTSR2_TR46_Msk /*!< Falling trigger event configuration bit of line 46 */
|
||||
#define EXTI_FTSR2_TR50_Pos (18U)
|
||||
#define EXTI_FTSR2_TR50_Msk (0x1UL << EXTI_FTSR2_TR50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR2_TR50 EXTI_FTSR2_TR50_Msk /*!< Falling trigger event configuration bit of line 50 */
|
||||
#define EXTI_FTSR2_TR53_Pos (21U)
|
||||
#define EXTI_FTSR2_TR53_Msk (0x1UL << EXTI_FTSR2_TR53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_FTSR2_TR53 EXTI_FTSR2_TR53_Msk /*!< Falling trigger event configuration bit of line 53 */
|
||||
#define EXTI_FTSR2_FT_Pos (12U)
|
||||
#define EXTI_FTSR2_FT_Msk (0x244 << EXTI_FTSR2_FT_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */
|
||||
#define EXTI_FTSR2_FT46_Pos (14U)
|
||||
#define EXTI_FTSR2_FT46_Msk (0x1UL << EXTI_FTSR2_FT46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR2_FT46 EXTI_FTSR2_FT46_Msk /*!< Falling trigger event configuration bit of line 46 */
|
||||
#define EXTI_FTSR2_FT50_Pos (18U)
|
||||
#define EXTI_FTSR2_FT50_Msk (0x1UL << EXTI_FTSR2_FT50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR2_FT50 EXTI_FTSR2_FT50_Msk /*!< Falling trigger event configuration bit of line 50 */
|
||||
#define EXTI_FTSR2_FT53_Pos (21U)
|
||||
#define EXTI_FTSR2_FT53_Msk (0x1UL << EXTI_FTSR2_FT53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_FTSR2_FT53 EXTI_FTSR2_FT53_Msk /*!< Falling trigger event configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register ******************/
|
||||
#define EXTI_SWIER2_SWIER46_Pos (14U)
|
||||
|
|
@ -8364,7 +8407,7 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_RPR2 register *******************/
|
||||
#define EXTI_RPR2_RPIF_Pos (14U)
|
||||
#define EXTI_RPR2_RPIF_Pos (12U)
|
||||
#define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */
|
||||
#define EXTI_RPR2_RPIF46_Pos (14U)
|
||||
|
|
@ -8378,7 +8421,7 @@ typedef struct
|
|||
#define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_FPR2 register *******************/
|
||||
#define EXTI_FPR2_FPIF_Pos (14U)
|
||||
#define EXTI_FPR2_FPIF_Pos (12U)
|
||||
#define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */
|
||||
#define EXTI_FPR2_FPIF46_Pos (14U)
|
||||
|
|
@ -8921,6 +8964,9 @@ typedef struct
|
|||
#define EXTI_IMR2_IM44_Pos (12U)
|
||||
#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
|
||||
#define EXTI_IMR2_IM45_Pos (13U)
|
||||
#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
|
||||
#define EXTI_IMR2_IM46_Pos (14U)
|
||||
#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
|
||||
|
|
@ -9002,6 +9048,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM44_Pos (12U)
|
||||
#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
|
||||
#define EXTI_EMR2_EM45_Pos (13U)
|
||||
#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
|
||||
#define EXTI_EMR2_EM46_Pos (14U)
|
||||
#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
|
||||
|
|
@ -9760,7 +9809,7 @@ typedef struct
|
|||
/* FLASH */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */
|
||||
#define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */
|
||||
#define FLASH_SIZE_DEFAULT (0x200000U) /*!< FLASH Size */
|
||||
#define FLASH_SECTOR_NB (128U) /*!< Flash Sector number */
|
||||
|
|
@ -10054,6 +10103,9 @@ typedef struct
|
|||
#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U)
|
||||
#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */
|
||||
#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */
|
||||
#define FLASH_OPTSR2_USBPD_DIS_Pos (8U)
|
||||
#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */
|
||||
#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */
|
||||
#define FLASH_OPTSR2_TZEN_Pos (24U)
|
||||
#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */
|
||||
#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */
|
||||
|
|
@ -10086,7 +10138,7 @@ typedef struct
|
|||
|
||||
/***************** Bits definition for FLASH_EDATA register ********************/
|
||||
#define FLASH_EDATAR_EDATA_STRT_Pos (0U)
|
||||
#define FLASH_EDATAR_EDATA_STRT_Msk (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000003 */
|
||||
#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */
|
||||
#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */
|
||||
#define FLASH_EDATAR_EDATA_EN_Pos (15U)
|
||||
#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -10134,7 +10186,6 @@ typedef struct
|
|||
#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */
|
||||
#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Filter Mathematical ACcelerator unit (FMAC) */
|
||||
|
|
@ -10250,7 +10301,6 @@ typedef struct
|
|||
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
|
||||
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Flexible Memory Controller */
|
||||
|
|
@ -10709,7 +10759,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -12470,27 +12520,27 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1_Pos (0U)
|
||||
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR2 register *******************/
|
||||
#define TIM_CCR2_CCR2_Pos (0U)
|
||||
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR3 register *******************/
|
||||
#define TIM_CCR3_CCR3_Pos (0U)
|
||||
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR4 register *******************/
|
||||
#define TIM_CCR4_CCR4_Pos (0U)
|
||||
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
|
|
@ -12504,7 +12554,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for TIM_CCR6 register *******************/
|
||||
#define TIM_CCR6_CCR6_Pos (0U)
|
||||
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
|
||||
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
|
||||
|
||||
/******************* Bit definition for TIM_BDTR register *******************/
|
||||
|
|
@ -12649,6 +12699,11 @@ typedef struct
|
|||
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<OCREF_CLR source selection */
|
||||
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
|
||||
|
||||
/******************* Bit definition for TIM_OR1 register *********************/
|
||||
#define TIM_OR1_RTCPREEN_Pos (1U)
|
||||
#define TIM_OR1_RTCPREEN_Msk (0x1UL << TIM_OR1_RTCPREEN_Pos) /*!< 0x00000002 */
|
||||
#define TIM_OR1_RTCPREEN TIM_OR1_RTCPREEN_Msk /*!< RTCPRE HSE divider enable */
|
||||
|
||||
/******************* Bit definition for TIM_TISEL register *********************/
|
||||
#define TIM_TISEL_TI1SEL_Pos (0U)
|
||||
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -13999,7 +14054,7 @@ typedef struct
|
|||
#define OCTOSPI_CR_TCIE_Msk XSPI_CR_TCIE_Msk /*!< 0x00020000 */
|
||||
#define OCTOSPI_CR_TCIE XSPI_CR_TCIE /*!< Transfer Complete Interrupt Enable */
|
||||
#define OCTOSPI_CR_FTIE_Pos XSPI_CR_FTIE_Pos
|
||||
#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk) /*!< 0x00040000 */
|
||||
#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk /*!< 0x00040000 */
|
||||
#define OCTOSPI_CR_FTIE XSPI_CR_FTIE /*!< FIFO Threshold Interrupt Enable */
|
||||
#define OCTOSPI_CR_SMIE_Pos XSPI_CR_SMIE_Pos
|
||||
#define OCTOSPI_CR_SMIE_Msk XSPI_CR_SMIE_Msk /*!< 0x00080000 */
|
||||
|
|
@ -14456,9 +14511,9 @@ typedef struct
|
|||
#define PWR_PMCR_AVD_READY_Pos (13U)
|
||||
#define PWR_PMCR_AVD_READY_Msk (0x1UL << PWR_PMCR_AVD_READY_Pos)
|
||||
#define PWR_PMCR_AVD_READY PWR_PMCR_AVD_READY_Msk
|
||||
#define PWR_PMCR_ETHERNETSO_Pos (16U)
|
||||
#define PWR_PMCR_ETHERNETSO_Msk (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
|
||||
#define PWR_PMCR_ETHERNETSO PWR_PMCR_ETHERNETSO_Msk
|
||||
#define PWR_PMCR_ETHERNETSO_Pos (16U)
|
||||
#define PWR_PMCR_ETHERNETSO_Msk (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
|
||||
#define PWR_PMCR_ETHERNETSO PWR_PMCR_ETHERNETSO_Msk
|
||||
#define PWR_PMCR_SRAM3SO_Pos (23U)
|
||||
#define PWR_PMCR_SRAM3SO_Msk (0x1UL << PWR_PMCR_SRAM3SO_Pos)
|
||||
#define PWR_PMCR_SRAM3SO PWR_PMCR_SRAM3SO_Msk
|
||||
|
|
@ -14556,9 +14611,9 @@ typedef struct
|
|||
#define PWR_SCCR_SMPSEN PWR_SCCR_SMPSEN_Msk
|
||||
|
||||
/******************** Bit definition for PWR_VMCR register ******************/
|
||||
#define PWR_VMCR_PVDEN_Pos (0U)
|
||||
#define PWR_VMCR_PVDEN_Msk (0x1UL << PWR_VMCR_PVDEN_Pos)
|
||||
#define PWR_VMCR_PVDEN PWR_VMCR_PVDEN_Msk
|
||||
#define PWR_VMCR_PVDEN_Pos (0U)
|
||||
#define PWR_VMCR_PVDEN_Msk (0x1UL << PWR_VMCR_PVDEN_Pos)
|
||||
#define PWR_VMCR_PVDEN PWR_VMCR_PVDEN_Msk
|
||||
#define PWR_VMCR_PLS_Pos (1U)
|
||||
#define PWR_VMCR_PLS_Msk (0x7UL << PWR_VMCR_PLS_Pos)
|
||||
#define PWR_VMCR_PLS PWR_VMCR_PLS_Msk
|
||||
|
|
@ -14575,12 +14630,12 @@ typedef struct
|
|||
#define PWR_VMCR_ALS_1 (0x2UL << PWR_VMCR_ALS_Pos)
|
||||
|
||||
/******************** Bit definition for PWR_USBSCR register ******************/
|
||||
#define PWR_USBSCR_USB33DEN_Pos (24U)
|
||||
#define PWR_USBSCR_USB33DEN_Msk (0x1UL << PWR_USBSCR_USB33DEN_Pos)
|
||||
#define PWR_USBSCR_USB33DEN PWR_USBSCR_USB33DEN_Msk
|
||||
#define PWR_USBSCR_USB33SV_Pos (25U)
|
||||
#define PWR_USBSCR_USB33SV_Msk (0x1UL << PWR_USBSCR_USB33SV_Pos)
|
||||
#define PWR_USBSCR_USB33SV PWR_USBSCR_USB33SV_Msk
|
||||
#define PWR_USBSCR_USB33DEN_Pos (24U)
|
||||
#define PWR_USBSCR_USB33DEN_Msk (0x1UL << PWR_USBSCR_USB33DEN_Pos)
|
||||
#define PWR_USBSCR_USB33DEN PWR_USBSCR_USB33DEN_Msk
|
||||
#define PWR_USBSCR_USB33SV_Pos (25U)
|
||||
#define PWR_USBSCR_USB33SV_Msk (0x1UL << PWR_USBSCR_USB33SV_Pos)
|
||||
#define PWR_USBSCR_USB33SV PWR_USBSCR_USB33SV_Msk
|
||||
|
||||
/******************** Bit definition for PWR_VMSR register ******************/
|
||||
#define PWR_VMSR_AVDO_Pos (19U)
|
||||
|
|
@ -15786,6 +15841,9 @@ typedef struct
|
|||
#define RCC_AHB2RSTR_RNGRST_Pos (18U)
|
||||
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
|
||||
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
|
||||
#define RCC_AHB2RSTR_PKARST_Pos (19U)
|
||||
#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00080000 */
|
||||
#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk
|
||||
|
||||
/******************** Bit definition for RCC_AHB4RSTR register **************/
|
||||
#define RCC_AHB4RSTR_SDMMC1RST_Pos (11U)
|
||||
|
|
@ -16055,6 +16113,9 @@ typedef struct
|
|||
#define RCC_AHB2ENR_RNGEN_Pos (18U)
|
||||
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
|
||||
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
|
||||
#define RCC_AHB2ENR_PKAEN_Pos (19U)
|
||||
#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00080000 */
|
||||
#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk
|
||||
#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
|
||||
#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
|
||||
#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
|
||||
|
|
@ -19025,9 +19086,6 @@ typedef struct
|
|||
#define SBS_SECCFGR_FPUSEC_Pos (3U)
|
||||
#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */
|
||||
#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN_Pos (31U)
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN_Msk (0x1UL << SBS_SECCFGR_SDCE_SEC_EN_Pos) /*!< 0x80000000 */
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN SBS_SECCFGR_SDCE_SEC_EN_Msk /*!< SMPS SBS security enable */
|
||||
|
||||
/****************** Bit definition for SBS_CNSLCKR register **************/
|
||||
#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U)
|
||||
|
|
@ -19085,7 +19143,7 @@ typedef struct
|
|||
#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
|
||||
|
||||
/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/
|
||||
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/
|
||||
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/
|
||||
|
||||
/*************** Bits definition for register x=1 (TZSC1) *************/
|
||||
#define GTZC_CFGR1_TIM2_Pos (0U)
|
||||
|
|
@ -19153,7 +19211,6 @@ typedef struct
|
|||
#define GTZC_CFGR1_LPTIM2_Pos (31U)
|
||||
#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
|
||||
|
||||
|
||||
/*************** Bits definition for register x=2 (TZSC1) *************/
|
||||
#define GTZC_CFGR2_FDCAN1_Pos (0U)
|
||||
#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos)
|
||||
|
|
@ -19247,6 +19304,7 @@ typedef struct
|
|||
#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos)
|
||||
#define GTZC_CFGR4_FLASH_REG_Pos (3U)
|
||||
#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
|
||||
|
||||
#define GTZC_CFGR4_SBS_Pos (6U)
|
||||
#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos)
|
||||
#define GTZC_CFGR4_RTC_Pos (7U)
|
||||
|
|
@ -19348,14 +19406,13 @@ typedef struct
|
|||
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos
|
||||
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -19433,6 +19490,7 @@ typedef struct
|
|||
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos
|
||||
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/
|
||||
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk
|
||||
|
|
@ -19504,8 +19562,8 @@ typedef struct
|
|||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -19654,8 +19712,8 @@ typedef struct
|
|||
#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZIC1_IER2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_IER2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -19697,7 +19755,6 @@ typedef struct
|
|||
#define GTZC_TZIC1_IER2_LPTIM5_Pos GTZC_CFGR2_LPTIM5_Pos
|
||||
#define GTZC_TZIC1_IER2_LPTIM5_Msk GTZC_CFGR2_LPTIM5_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZIC_IER3 register ***************/
|
||||
#define GTZC_TZIC1_IER3_LPTIM6_Pos GTZC_CFGR3_LPTIM6_Pos
|
||||
#define GTZC_TZIC1_IER3_LPTIM6_Msk GTZC_CFGR3_LPTIM6_Msk
|
||||
|
|
@ -19849,8 +19906,8 @@ typedef struct
|
|||
#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZIC1_SR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_SR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -20043,8 +20100,8 @@ typedef struct
|
|||
#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZIC1_FCR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_FCR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -20614,6 +20671,7 @@ typedef struct
|
|||
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USART_DMAREQUESTS_SW_WA
|
||||
/****************** Bit definition for USART_CR1 register *******************/
|
||||
#define USART_CR1_UE_Pos (0U)
|
||||
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -21938,6 +21996,15 @@ typedef struct
|
|||
#define I3C_BCR_BCR2_Pos (2U)
|
||||
#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */
|
||||
#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */
|
||||
#define I3C_BCR_BCR3_Pos (3U)
|
||||
#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */
|
||||
#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */
|
||||
#define I3C_BCR_BCR4_Pos (4U)
|
||||
#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */
|
||||
#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */
|
||||
#define I3C_BCR_BCR5_Pos (5U)
|
||||
#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */
|
||||
#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */
|
||||
#define I3C_BCR_BCR6_Pos (6U)
|
||||
#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */
|
||||
#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */
|
||||
|
|
@ -22810,6 +22877,327 @@ typedef struct
|
|||
#define USB_PMA_RXBD_ADDMSK (0xFFFF0000UL)
|
||||
#define USB_PMA_RXBD_COUNTMSK (0x03FFFFFFUL)
|
||||
|
||||
/*!< USB PMA SIZE */
|
||||
#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */
|
||||
|
||||
#define USB_DRD_FS_EP_NBR (8U) /*!< Number of USB Device endpoints */
|
||||
#define USB_DRD_FS_CH_NBR (8U) /*!< Number of USB Host channels */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Public Key Accelerator (PKA) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************* Bit definition for PKA_CR register *********************/
|
||||
#define PKA_CR_EN_Pos (0U)
|
||||
#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */
|
||||
#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */
|
||||
#define PKA_CR_START_Pos (1U)
|
||||
#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */
|
||||
#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */
|
||||
#define PKA_CR_MODE_Pos (8U)
|
||||
#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */
|
||||
#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */
|
||||
#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */
|
||||
#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */
|
||||
#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */
|
||||
#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */
|
||||
#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */
|
||||
#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */
|
||||
#define PKA_CR_PROCENDIE_Pos (17U)
|
||||
#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */
|
||||
#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */
|
||||
#define PKA_CR_RAMERRIE_Pos (19U)
|
||||
#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */
|
||||
#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */
|
||||
#define PKA_CR_ADDRERRIE_Pos (20U)
|
||||
#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */
|
||||
#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< Address error interrupt enable */
|
||||
#define PKA_CR_OPERRIE_Pos (21U)
|
||||
#define PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) /*!< 0x00200000 */
|
||||
#define PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk /*!< Operation Error interrupt enable */
|
||||
|
||||
/******************* Bit definition for PKA_SR register *********************/
|
||||
#define PKA_SR_INITOK_Pos (0U)
|
||||
#define PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) /*!< 0x00000001 */
|
||||
#define PKA_SR_INITOK PKA_SR_INITOK_Msk /*!< PKA initialisation flag */
|
||||
#define PKA_SR_BUSY_Pos (16U)
|
||||
#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */
|
||||
#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */
|
||||
#define PKA_SR_PROCENDF_Pos (17U)
|
||||
#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */
|
||||
#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */
|
||||
#define PKA_SR_RAMERRF_Pos (19U)
|
||||
#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */
|
||||
#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */
|
||||
#define PKA_SR_ADDRERRF_Pos (20U)
|
||||
#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */
|
||||
#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */
|
||||
#define PKA_SR_OPERRF_Pos (21U)
|
||||
#define PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) /*!< 0x00200000 */
|
||||
#define PKA_SR_OPERRF PKA_SR_OPERRF_Msk /*!< PKA operation Error flag*/
|
||||
|
||||
/******************* Bit definition for PKA_CLRFR register ******************/
|
||||
#define PKA_CLRFR_PROCENDFC_Pos (17U)
|
||||
#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */
|
||||
#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */
|
||||
#define PKA_CLRFR_RAMERRFC_Pos (19U)
|
||||
#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */
|
||||
#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */
|
||||
#define PKA_CLRFR_ADDRERRFC_Pos (20U)
|
||||
#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */
|
||||
#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */
|
||||
#define PKA_CLRFR_OPERRFC_Pos (21U)
|
||||
#define PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) /*!< 0x00200000 */
|
||||
#define PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk /*!< Clear PKA operation Error flag*/
|
||||
|
||||
/******************* Bits definition for PKA RAM *************************/
|
||||
#define PKA_RAM_OFFSET (0x0400UL) /*!< PKA RAM address offset */
|
||||
|
||||
/* Compute Montgomery parameter input data */
|
||||
#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
|
||||
/* Compute Montgomery parameter output data */
|
||||
#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */
|
||||
|
||||
/* Compute modular exponentiation input data */
|
||||
#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
|
||||
#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
|
||||
#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
|
||||
#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */
|
||||
#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */
|
||||
#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */
|
||||
|
||||
/* Compute modular exponentiation output data */
|
||||
#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */
|
||||
#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */
|
||||
#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */
|
||||
#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */
|
||||
|
||||
/* Compute ECC scalar multiplication input data */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */
|
||||
|
||||
/* Compute ECC scalar multiplication output data */
|
||||
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
|
||||
#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
|
||||
|
||||
/* Point check input data */
|
||||
#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
|
||||
#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
|
||||
|
||||
/* Point check output data */
|
||||
#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
|
||||
|
||||
/* ECDSA signature input data */
|
||||
#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
|
||||
#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
|
||||
#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */
|
||||
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
|
||||
#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */
|
||||
#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
|
||||
|
||||
/* ECDSA signature output data */
|
||||
#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
|
||||
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */
|
||||
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */
|
||||
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */
|
||||
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */
|
||||
|
||||
|
||||
/* ECDSA verification input data */
|
||||
#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
|
||||
#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
|
||||
#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
|
||||
#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */
|
||||
#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */
|
||||
#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */
|
||||
#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
|
||||
#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
|
||||
|
||||
/* ECDSA verification output data */
|
||||
#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* RSA CRT exponentiation input data */
|
||||
#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */
|
||||
#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */
|
||||
#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */
|
||||
#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */
|
||||
#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */
|
||||
#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */
|
||||
#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
|
||||
|
||||
/* RSA CRT exponentiation output data */
|
||||
#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular reduction input data */
|
||||
#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */
|
||||
#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */
|
||||
#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */
|
||||
#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
|
||||
/* Modular reduction output data */
|
||||
#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Arithmetic addition input data */
|
||||
#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Arithmetic addition output data */
|
||||
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Arithmetic subtraction input data */
|
||||
#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Arithmetic subtraction output data */
|
||||
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Arithmetic multiplication input data */
|
||||
#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Arithmetic multiplication output data */
|
||||
#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Comparison input data */
|
||||
#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Comparison output data */
|
||||
#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular addition input data */
|
||||
#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */
|
||||
|
||||
/* Modular addition output data */
|
||||
#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular inversion input data */
|
||||
#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */
|
||||
|
||||
/* Modular inversion output data */
|
||||
#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Modular subtraction input data */
|
||||
#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
|
||||
|
||||
/* Modular subtraction output data */
|
||||
#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Montgomery multiplication input data */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
|
||||
|
||||
/* Montgomery multiplication output data */
|
||||
#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
|
||||
|
||||
/* Generic Arithmetic input data */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
|
||||
|
||||
/* Generic Arithmetic output data */
|
||||
#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */
|
||||
|
||||
/* Compute ECC complete addition input data */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
|
||||
|
||||
/* Compute ECC complete addition output data */
|
||||
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
|
||||
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */
|
||||
|
||||
/* Compute ECC double base ladder input data */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
|
||||
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
|
||||
|
||||
/* Compute ECC double base ladder output data */
|
||||
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */
|
||||
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */
|
||||
#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
|
||||
|
||||
/* Compute ECC projective to affine conversion input data */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
|
||||
|
||||
/* Compute ECC projective to affine conversion output data */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */
|
||||
#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
|
||||
|
||||
|
||||
/** @addtogroup STM32H5xx_Peripheral_Exported_macros
|
||||
* @{
|
||||
|
|
@ -22827,6 +23215,8 @@ typedef struct
|
|||
|
||||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \
|
||||
((INSTANCE) == ADC12_COMMON_S))
|
||||
/******************************* PKA Instances ********************************/
|
||||
#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))
|
||||
|
||||
/******************************* CORDIC Instances *****************************/
|
||||
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
|
||||
|
|
@ -22872,6 +23262,11 @@ typedef struct
|
|||
((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S))
|
||||
|
||||
#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \
|
||||
((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S))
|
||||
|
||||
/****************************** RAMCFG Instances ********************************/
|
||||
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \
|
||||
((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \
|
||||
|
|
@ -23397,6 +23792,9 @@ typedef struct
|
|||
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
|
||||
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
|
||||
|
||||
/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/
|
||||
#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
|
||||
|
||||
/****************** TIM Instances : Advanced timer instances *******************/
|
||||
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
|
||||
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
|
||||
|
|
@ -23594,7 +23992,6 @@ typedef struct
|
|||
/******************************* USB DRD FS PCD Instances *************************/
|
||||
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))
|
||||
|
||||
|
||||
/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
|
||||
|
||||
/** @} */ /* End of group STM32H563xx */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/**
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h573xx.h
|
||||
* @author MCD Application Team
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
* - Peripheral's registers declarations and bits definition
|
||||
* - Macros to access peripheral’s registers hardware
|
||||
* - Macros to access peripheral's registers hardware
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -439,7 +439,7 @@ typedef struct
|
|||
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
|
||||
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
|
||||
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
|
||||
uint32_t RESERVED;
|
||||
__IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */
|
||||
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
|
||||
} RNG_TypeDef;
|
||||
|
||||
|
|
@ -843,6 +843,7 @@ typedef struct
|
|||
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
|
||||
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
|
||||
} FMAC_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief General Purpose I/O
|
||||
*/
|
||||
|
|
@ -989,7 +990,8 @@ typedef struct
|
|||
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
|
||||
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
|
||||
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
|
||||
uint32_t RESERVED0[221];/*!< Reserved, Address offset: 0x68 */
|
||||
__IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */
|
||||
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
|
||||
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
|
||||
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
|
||||
} TIM_TypeDef;
|
||||
|
|
@ -1950,7 +1952,6 @@ typedef struct
|
|||
#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL)
|
||||
#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL)
|
||||
#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL)
|
||||
|
||||
#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL)
|
||||
#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
|
||||
#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
|
||||
|
|
@ -1959,7 +1960,6 @@ typedef struct
|
|||
#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL)
|
||||
#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL)
|
||||
|
||||
|
||||
/*!< APB3 Non secure peripherals */
|
||||
#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL)
|
||||
#define SPI5_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL)
|
||||
|
|
@ -1980,6 +1980,7 @@ typedef struct
|
|||
#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL)
|
||||
#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL)
|
||||
#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL)
|
||||
|
||||
/*!< AHB4 Non secure peripherals */
|
||||
#define OTFDEC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL)
|
||||
#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL)
|
||||
|
|
@ -1990,7 +1991,6 @@ typedef struct
|
|||
#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL)
|
||||
#define SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8C00UL)
|
||||
#define DLYB_SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8800UL)
|
||||
|
||||
#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */
|
||||
#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */
|
||||
#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL)
|
||||
|
|
@ -2003,9 +2003,9 @@ typedef struct
|
|||
|
||||
/* Flash, Peripheral and internal SRAMs base addresses - Secure */
|
||||
#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */
|
||||
#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */
|
||||
#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */
|
||||
#define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */
|
||||
#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (512 KB) secure base address */
|
||||
#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */
|
||||
#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
|
||||
|
||||
/* Peripheral memory map - Secure */
|
||||
|
|
@ -2092,7 +2092,6 @@ typedef struct
|
|||
#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
|
||||
#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL)
|
||||
#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL)
|
||||
|
||||
#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL)
|
||||
#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL)
|
||||
#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL)
|
||||
|
|
@ -2109,7 +2108,6 @@ typedef struct
|
|||
#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL)
|
||||
#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL)
|
||||
#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL)
|
||||
|
||||
#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S)
|
||||
#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL)
|
||||
#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL)
|
||||
|
|
@ -2170,7 +2168,6 @@ typedef struct
|
|||
#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL)
|
||||
#define SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8C00UL)
|
||||
#define DLYB_SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8800UL)
|
||||
|
||||
#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */
|
||||
#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */
|
||||
#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL)
|
||||
|
|
@ -2183,12 +2180,10 @@ typedef struct
|
|||
|
||||
/* Debug MCU registers base address */
|
||||
#define DBGMCU_BASE (0x44024000UL)
|
||||
|
||||
#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */
|
||||
#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
|
||||
#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */
|
||||
|
||||
|
||||
/* Internal Flash OTP Area */
|
||||
#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
|
||||
#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */
|
||||
|
|
@ -2231,9 +2226,6 @@ typedef struct
|
|||
#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */
|
||||
#endif /* CMSE */
|
||||
|
||||
/*!< USB PMA SIZE */
|
||||
#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */
|
||||
|
||||
/*!< Root Secure Service Library */
|
||||
/************ RSSLIB SAU system Flash region definition constants *************/
|
||||
#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL)
|
||||
|
|
@ -4884,11 +4876,36 @@ typedef struct
|
|||
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
|
||||
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
|
||||
|
||||
/******************** Bits definition for RNG_NSCR register *******************/
|
||||
#define RNG_NSCR_EN_OSC1_Pos (0U)
|
||||
#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */
|
||||
#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk
|
||||
#define RNG_NSCR_EN_OSC2_Pos (3U)
|
||||
#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */
|
||||
#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk
|
||||
#define RNG_NSCR_EN_OSC3_Pos (6U)
|
||||
#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */
|
||||
#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk
|
||||
#define RNG_NSCR_EN_OSC4_Pos (9U)
|
||||
#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */
|
||||
#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk
|
||||
#define RNG_NSCR_EN_OSC5_Pos (12U)
|
||||
#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */
|
||||
#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk
|
||||
#define RNG_NSCR_EN_OSC6_Pos (15U)
|
||||
#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */
|
||||
#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk
|
||||
|
||||
/******************** Bits definition for RNG_HTCR register *******************/
|
||||
#define RNG_HTCR_HTCFG_Pos (0U)
|
||||
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
|
||||
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
|
||||
|
||||
/******************** RNG Nist Compliance Values ******************************/
|
||||
#define RNG_CR_NIST_VALUE (0x00F00E00U)
|
||||
#define RNG_HTCR_NIST_VALUE (0x6A91U)
|
||||
#define RNG_NSCR_NIST_VALUE (0x3AF66U)
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Digital to Analog Converter */
|
||||
|
|
@ -8760,32 +8777,32 @@ typedef struct
|
|||
#define EXTI_PRIVENR1_PRIV31 EXTI_PRIVENR1_PRIV31_Msk /*!< Privilege enable on line 31 */
|
||||
|
||||
/****************** Bit definition for EXTI_RTSR2 register *******************/
|
||||
#define EXTI_RTSR2_TR_Pos (14U)
|
||||
#define EXTI_RTSR2_TR_Msk (0x244UL << EXTI_RTSR2_TR_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
|
||||
#define EXTI_RTSR2_TR46_Pos (14U)
|
||||
#define EXTI_RTSR2_TR46_Msk (0x1UL << EXTI_RTSR2_TR46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_RTSR2_TR46 EXTI_RTSR2_TR46_Msk /*!< Rising trigger event configuration bit of line 46 */
|
||||
#define EXTI_RTSR2_TR50_Pos (18U)
|
||||
#define EXTI_RTSR2_TR50_Msk (0x1UL << EXTI_RTSR2_TR50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_RTSR2_TR50 EXTI_RTSR2_TR50_Msk /*!< Rising trigger event configuration bit of line 50 */
|
||||
#define EXTI_RTSR2_TR53_Pos (21U)
|
||||
#define EXTI_RTSR2_TR53_Msk (0x1UL << EXTI_RTSR2_TR53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_RTSR2_TR53 EXTI_RTSR2_TR53_Msk /*!< Rising trigger event configuration bit of line 53 */
|
||||
#define EXTI_RTSR2_RT_Pos (12U)
|
||||
#define EXTI_RTSR2_RT_Msk (0x244UL << EXTI_RTSR2_RT_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */
|
||||
#define EXTI_RTSR2_RT46_Pos (14U)
|
||||
#define EXTI_RTSR2_RT46_Msk (0x1UL << EXTI_RTSR2_RT46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_RTSR2_RT46 EXTI_RTSR2_RT46_Msk /*!< Rising trigger event configuration bit of line 46 */
|
||||
#define EXTI_RTSR2_RT50_Pos (18U)
|
||||
#define EXTI_RTSR2_RT50_Msk (0x1UL << EXTI_RTSR2_RT50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_RTSR2_RT50 EXTI_RTSR2_RT50_Msk /*!< Rising trigger event configuration bit of line 50 */
|
||||
#define EXTI_RTSR2_RT53_Pos (21U)
|
||||
#define EXTI_RTSR2_RT53_Msk (0x1UL << EXTI_RTSR2_RT53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_RTSR2_RT53 EXTI_RTSR2_RT53_Msk /*!< Rising trigger event configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_FTSR2 register *******************/
|
||||
#define EXTI_FTSR2_TR_Pos (14U)
|
||||
#define EXTI_FTSR2_TR_Msk (0x244 << EXTI_FTSR2_TR_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
|
||||
#define EXTI_FTSR2_TR46_Pos (14U)
|
||||
#define EXTI_FTSR2_TR46_Msk (0x1UL << EXTI_FTSR2_TR46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR2_TR46 EXTI_FTSR2_TR46_Msk /*!< Falling trigger event configuration bit of line 46 */
|
||||
#define EXTI_FTSR2_TR50_Pos (18U)
|
||||
#define EXTI_FTSR2_TR50_Msk (0x1UL << EXTI_FTSR2_TR50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR2_TR50 EXTI_FTSR2_TR50_Msk /*!< Falling trigger event configuration bit of line 50 */
|
||||
#define EXTI_FTSR2_TR53_Pos (21U)
|
||||
#define EXTI_FTSR2_TR53_Msk (0x1UL << EXTI_FTSR2_TR53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_FTSR2_TR53 EXTI_FTSR2_TR53_Msk /*!< Falling trigger event configuration bit of line 53 */
|
||||
#define EXTI_FTSR2_FT_Pos (12U)
|
||||
#define EXTI_FTSR2_FT_Msk (0x244 << EXTI_FTSR2_FT_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */
|
||||
#define EXTI_FTSR2_FT46_Pos (14U)
|
||||
#define EXTI_FTSR2_FT46_Msk (0x1UL << EXTI_FTSR2_FT46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_FTSR2_FT46 EXTI_FTSR2_FT46_Msk /*!< Falling trigger event configuration bit of line 46 */
|
||||
#define EXTI_FTSR2_FT50_Pos (18U)
|
||||
#define EXTI_FTSR2_FT50_Msk (0x1UL << EXTI_FTSR2_FT50_Pos) /*!< 0x00040000 */
|
||||
#define EXTI_FTSR2_FT50 EXTI_FTSR2_FT50_Msk /*!< Falling trigger event configuration bit of line 50 */
|
||||
#define EXTI_FTSR2_FT53_Pos (21U)
|
||||
#define EXTI_FTSR2_FT53_Msk (0x1UL << EXTI_FTSR2_FT53_Pos) /*!< 0x00200000 */
|
||||
#define EXTI_FTSR2_FT53 EXTI_FTSR2_FT53_Msk /*!< Falling trigger event configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_SWIER2 register ******************/
|
||||
#define EXTI_SWIER2_SWIER46_Pos (14U)
|
||||
|
|
@ -8799,7 +8816,7 @@ typedef struct
|
|||
#define EXTI_SWIER2_SWIER53 EXTI_SWIER2_SWIER53_Msk /*!< Software Interrupt on line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_RPR2 register *******************/
|
||||
#define EXTI_RPR2_RPIF_Pos (14U)
|
||||
#define EXTI_RPR2_RPIF_Pos (12U)
|
||||
#define EXTI_RPR2_RPIF_Msk (0x244UL << EXTI_RPR2_RPIF_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_RPR2_RPIF EXTI_RPR2_RPIF_Msk /*!< Rising pending edge configuration bits */
|
||||
#define EXTI_RPR2_RPIF46_Pos (14U)
|
||||
|
|
@ -8813,7 +8830,7 @@ typedef struct
|
|||
#define EXTI_RPR2_RPIF53 EXTI_RPR2_RPIF53_Msk /*!< Rising pending edge configuration bit of line 53 */
|
||||
|
||||
/****************** Bit definition for EXTI_FPR2 register *******************/
|
||||
#define EXTI_FPR2_FPIF_Pos (14U)
|
||||
#define EXTI_FPR2_FPIF_Pos (12U)
|
||||
#define EXTI_FPR2_FPIF_Msk (0x244UL << EXTI_FPR2_FPIF_Pos) /*!< 0x00244000 */
|
||||
#define EXTI_FPR2_FPIF EXTI_FPR2_FPIF_Msk /*!< Rising falling edge configuration bits */
|
||||
#define EXTI_FPR2_FPIF46_Pos (14U)
|
||||
|
|
@ -9356,6 +9373,9 @@ typedef struct
|
|||
#define EXTI_IMR2_IM44_Pos (12U)
|
||||
#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
|
||||
#define EXTI_IMR2_IM45_Pos (13U)
|
||||
#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
|
||||
#define EXTI_IMR2_IM46_Pos (14U)
|
||||
#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
|
||||
|
|
@ -9437,6 +9457,9 @@ typedef struct
|
|||
#define EXTI_EMR2_EM44_Pos (12U)
|
||||
#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
|
||||
#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
|
||||
#define EXTI_EMR2_EM45_Pos (13U)
|
||||
#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
|
||||
#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
|
||||
#define EXTI_EMR2_EM46_Pos (14U)
|
||||
#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
|
||||
#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
|
||||
|
|
@ -10195,7 +10218,7 @@ typedef struct
|
|||
/* FLASH */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycle */
|
||||
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycle */
|
||||
#define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-based registers for each Flash bank */
|
||||
#define FLASH_SIZE_DEFAULT (0x200000U) /*!< FLASH Size */
|
||||
#define FLASH_SECTOR_NB (128U) /*!< Flash Sector number */
|
||||
|
|
@ -10489,6 +10512,9 @@ typedef struct
|
|||
#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U)
|
||||
#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */
|
||||
#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */
|
||||
#define FLASH_OPTSR2_USBPD_DIS_Pos (8U)
|
||||
#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */
|
||||
#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */
|
||||
#define FLASH_OPTSR2_TZEN_Pos (24U)
|
||||
#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */
|
||||
#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */
|
||||
|
|
@ -10521,7 +10547,7 @@ typedef struct
|
|||
|
||||
/***************** Bits definition for FLASH_EDATA register ********************/
|
||||
#define FLASH_EDATAR_EDATA_STRT_Pos (0U)
|
||||
#define FLASH_EDATAR_EDATA_STRT_Msk (0x3UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000003 */
|
||||
#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */
|
||||
#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */
|
||||
#define FLASH_EDATAR_EDATA_EN_Pos (15U)
|
||||
#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */
|
||||
|
|
@ -10569,7 +10595,6 @@ typedef struct
|
|||
#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */
|
||||
#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Filter Mathematical ACcelerator unit (FMAC) */
|
||||
|
|
@ -10685,7 +10710,6 @@ typedef struct
|
|||
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
|
||||
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Flexible Memory Controller */
|
||||
|
|
@ -11144,7 +11168,7 @@ typedef struct
|
|||
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
|
||||
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
|
||||
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
|
||||
#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
|
||||
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
|
||||
|
||||
#define FMC_SDCMR_CTB2_Pos (3U)
|
||||
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
|
||||
|
|
@ -12905,27 +12929,27 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for TIM_CCR1 register *******************/
|
||||
#define TIM_CCR1_CCR1_Pos (0U)
|
||||
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR2 register *******************/
|
||||
#define TIM_CCR2_CCR2_Pos (0U)
|
||||
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR3 register *******************/
|
||||
#define TIM_CCR3_CCR3_Pos (0U)
|
||||
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR4 register *******************/
|
||||
#define TIM_CCR4_CCR4_Pos (0U)
|
||||
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
|
||||
|
||||
/******************* Bit definition for TIM_CCR5 register *******************/
|
||||
#define TIM_CCR5_CCR5_Pos (0U)
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
|
||||
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
|
||||
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
|
||||
#define TIM_CCR5_GC5C1_Pos (29U)
|
||||
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
|
||||
|
|
@ -12939,7 +12963,7 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for TIM_CCR6 register *******************/
|
||||
#define TIM_CCR6_CCR6_Pos (0U)
|
||||
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
|
||||
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
|
||||
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
|
||||
|
||||
/******************* Bit definition for TIM_BDTR register *******************/
|
||||
|
|
@ -13084,6 +13108,11 @@ typedef struct
|
|||
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<OCREF_CLR source selection */
|
||||
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
|
||||
|
||||
/******************* Bit definition for TIM_OR1 register *********************/
|
||||
#define TIM_OR1_RTCPREEN_Pos (1U)
|
||||
#define TIM_OR1_RTCPREEN_Msk (0x1UL << TIM_OR1_RTCPREEN_Pos) /*!< 0x00000002 */
|
||||
#define TIM_OR1_RTCPREEN TIM_OR1_RTCPREEN_Msk /*!< RTCPRE HSE divider enable */
|
||||
|
||||
/******************* Bit definition for TIM_TISEL register *********************/
|
||||
#define TIM_TISEL_TI1SEL_Pos (0U)
|
||||
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
|
||||
|
|
@ -14434,7 +14463,7 @@ typedef struct
|
|||
#define OCTOSPI_CR_TCIE_Msk XSPI_CR_TCIE_Msk /*!< 0x00020000 */
|
||||
#define OCTOSPI_CR_TCIE XSPI_CR_TCIE /*!< Transfer Complete Interrupt Enable */
|
||||
#define OCTOSPI_CR_FTIE_Pos XSPI_CR_FTIE_Pos
|
||||
#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk) /*!< 0x00040000 */
|
||||
#define OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk /*!< 0x00040000 */
|
||||
#define OCTOSPI_CR_FTIE XSPI_CR_FTIE /*!< FIFO Threshold Interrupt Enable */
|
||||
#define OCTOSPI_CR_SMIE_Pos XSPI_CR_SMIE_Pos
|
||||
#define OCTOSPI_CR_SMIE_Msk XSPI_CR_SMIE_Msk /*!< 0x00080000 */
|
||||
|
|
@ -15001,9 +15030,9 @@ typedef struct
|
|||
#define PWR_PMCR_AVD_READY_Pos (13U)
|
||||
#define PWR_PMCR_AVD_READY_Msk (0x1UL << PWR_PMCR_AVD_READY_Pos)
|
||||
#define PWR_PMCR_AVD_READY PWR_PMCR_AVD_READY_Msk
|
||||
#define PWR_PMCR_ETHERNETSO_Pos (16U)
|
||||
#define PWR_PMCR_ETHERNETSO_Msk (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
|
||||
#define PWR_PMCR_ETHERNETSO PWR_PMCR_ETHERNETSO_Msk
|
||||
#define PWR_PMCR_ETHERNETSO_Pos (16U)
|
||||
#define PWR_PMCR_ETHERNETSO_Msk (0x1UL << PWR_PMCR_ETHERNETSO_Pos)
|
||||
#define PWR_PMCR_ETHERNETSO PWR_PMCR_ETHERNETSO_Msk
|
||||
#define PWR_PMCR_SRAM3SO_Pos (23U)
|
||||
#define PWR_PMCR_SRAM3SO_Msk (0x1UL << PWR_PMCR_SRAM3SO_Pos)
|
||||
#define PWR_PMCR_SRAM3SO PWR_PMCR_SRAM3SO_Msk
|
||||
|
|
@ -15101,9 +15130,9 @@ typedef struct
|
|||
#define PWR_SCCR_SMPSEN PWR_SCCR_SMPSEN_Msk
|
||||
|
||||
/******************** Bit definition for PWR_VMCR register ******************/
|
||||
#define PWR_VMCR_PVDEN_Pos (0U)
|
||||
#define PWR_VMCR_PVDEN_Msk (0x1UL << PWR_VMCR_PVDEN_Pos)
|
||||
#define PWR_VMCR_PVDEN PWR_VMCR_PVDEN_Msk
|
||||
#define PWR_VMCR_PVDEN_Pos (0U)
|
||||
#define PWR_VMCR_PVDEN_Msk (0x1UL << PWR_VMCR_PVDEN_Pos)
|
||||
#define PWR_VMCR_PVDEN PWR_VMCR_PVDEN_Msk
|
||||
#define PWR_VMCR_PLS_Pos (1U)
|
||||
#define PWR_VMCR_PLS_Msk (0x7UL << PWR_VMCR_PLS_Pos)
|
||||
#define PWR_VMCR_PLS PWR_VMCR_PLS_Msk
|
||||
|
|
@ -15120,12 +15149,12 @@ typedef struct
|
|||
#define PWR_VMCR_ALS_1 (0x2UL << PWR_VMCR_ALS_Pos)
|
||||
|
||||
/******************** Bit definition for PWR_USBSCR register ******************/
|
||||
#define PWR_USBSCR_USB33DEN_Pos (24U)
|
||||
#define PWR_USBSCR_USB33DEN_Msk (0x1UL << PWR_USBSCR_USB33DEN_Pos)
|
||||
#define PWR_USBSCR_USB33DEN PWR_USBSCR_USB33DEN_Msk
|
||||
#define PWR_USBSCR_USB33SV_Pos (25U)
|
||||
#define PWR_USBSCR_USB33SV_Msk (0x1UL << PWR_USBSCR_USB33SV_Pos)
|
||||
#define PWR_USBSCR_USB33SV PWR_USBSCR_USB33SV_Msk
|
||||
#define PWR_USBSCR_USB33DEN_Pos (24U)
|
||||
#define PWR_USBSCR_USB33DEN_Msk (0x1UL << PWR_USBSCR_USB33DEN_Pos)
|
||||
#define PWR_USBSCR_USB33DEN PWR_USBSCR_USB33DEN_Msk
|
||||
#define PWR_USBSCR_USB33SV_Pos (25U)
|
||||
#define PWR_USBSCR_USB33SV_Msk (0x1UL << PWR_USBSCR_USB33SV_Pos)
|
||||
#define PWR_USBSCR_USB33SV PWR_USBSCR_USB33SV_Msk
|
||||
|
||||
/******************** Bit definition for PWR_VMSR register ******************/
|
||||
#define PWR_VMSR_AVDO_Pos (19U)
|
||||
|
|
@ -19606,9 +19635,6 @@ typedef struct
|
|||
#define SBS_SECCFGR_FPUSEC_Pos (3U)
|
||||
#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */
|
||||
#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN_Pos (31U)
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN_Msk (0x1UL << SBS_SECCFGR_SDCE_SEC_EN_Pos) /*!< 0x80000000 */
|
||||
#define SBS_SECCFGR_SDCE_SEC_EN SBS_SECCFGR_SDCE_SEC_EN_Msk /*!< SMPS SBS security enable */
|
||||
|
||||
/****************** Bit definition for SBS_CNSLCKR register **************/
|
||||
#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U)
|
||||
|
|
@ -19666,7 +19692,7 @@ typedef struct
|
|||
#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
|
||||
|
||||
/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/
|
||||
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers ********/
|
||||
/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/
|
||||
|
||||
/*************** Bits definition for register x=1 (TZSC1) *************/
|
||||
#define GTZC_CFGR1_TIM2_Pos (0U)
|
||||
|
|
@ -19734,7 +19760,6 @@ typedef struct
|
|||
#define GTZC_CFGR1_LPTIM2_Pos (31U)
|
||||
#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
|
||||
|
||||
|
||||
/*************** Bits definition for register x=2 (TZSC1) *************/
|
||||
#define GTZC_CFGR2_FDCAN1_Pos (0U)
|
||||
#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos)
|
||||
|
|
@ -19834,6 +19859,7 @@ typedef struct
|
|||
#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos)
|
||||
#define GTZC_CFGR4_FLASH_REG_Pos (3U)
|
||||
#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
|
||||
|
||||
#define GTZC_CFGR4_OTFDEC1_Pos (4U)
|
||||
#define GTZC_CFGR4_OTFDEC1_Msk (0x01UL << GTZC_CFGR4_OTFDEC1_Pos)
|
||||
#define GTZC_CFGR4_SBS_Pos (6U)
|
||||
|
|
@ -19937,14 +19963,13 @@ typedef struct
|
|||
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos
|
||||
#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -20028,6 +20053,7 @@ typedef struct
|
|||
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos
|
||||
#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/
|
||||
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk
|
||||
|
|
@ -20099,8 +20125,8 @@ typedef struct
|
|||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -20255,8 +20281,8 @@ typedef struct
|
|||
#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZIC1_IER2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_IER2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -20298,7 +20324,6 @@ typedef struct
|
|||
#define GTZC_TZIC1_IER2_LPTIM5_Pos GTZC_CFGR2_LPTIM5_Pos
|
||||
#define GTZC_TZIC1_IER2_LPTIM5_Msk GTZC_CFGR2_LPTIM5_Msk
|
||||
|
||||
|
||||
/******************* Bits definition for GTZC_TZIC_IER3 register ***************/
|
||||
#define GTZC_TZIC1_IER3_LPTIM6_Pos GTZC_CFGR3_LPTIM6_Pos
|
||||
#define GTZC_TZIC1_IER3_LPTIM6_Msk GTZC_CFGR3_LPTIM6_Msk
|
||||
|
|
@ -20458,8 +20483,8 @@ typedef struct
|
|||
#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZIC1_SR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_SR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -20660,8 +20685,8 @@ typedef struct
|
|||
#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk
|
||||
#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos
|
||||
#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk
|
||||
#define GTZC_TZIC1_FCR2_UCPD_Pos GTZC_CFGR2_UCPD_Pos
|
||||
#define GTZC_TZIC1_FCR2_UCPD_Msk GTZC_CFGR2_UCPD_Msk
|
||||
#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos
|
||||
#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk
|
||||
#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos
|
||||
#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk
|
||||
#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
|
||||
|
|
@ -21239,6 +21264,7 @@ typedef struct
|
|||
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#define USART_DMAREQUESTS_SW_WA
|
||||
/****************** Bit definition for USART_CR1 register *******************/
|
||||
#define USART_CR1_UE_Pos (0U)
|
||||
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -22563,6 +22589,15 @@ typedef struct
|
|||
#define I3C_BCR_BCR2_Pos (2U)
|
||||
#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */
|
||||
#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */
|
||||
#define I3C_BCR_BCR3_Pos (3U)
|
||||
#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */
|
||||
#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */
|
||||
#define I3C_BCR_BCR4_Pos (4U)
|
||||
#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */
|
||||
#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */
|
||||
#define I3C_BCR_BCR5_Pos (5U)
|
||||
#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */
|
||||
#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */
|
||||
#define I3C_BCR_BCR6_Pos (6U)
|
||||
#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */
|
||||
#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */
|
||||
|
|
@ -23435,6 +23470,12 @@ typedef struct
|
|||
#define USB_PMA_RXBD_ADDMSK (0xFFFF0000UL)
|
||||
#define USB_PMA_RXBD_COUNTMSK (0x03FFFFFFUL)
|
||||
|
||||
/*!< USB PMA SIZE */
|
||||
#define USB_DRD_PMA_SIZE (2048U) /*!< USB PMA Size 2Kbyte */
|
||||
|
||||
#define USB_DRD_FS_EP_NBR (8U) /*!< Number of USB Device endpoints */
|
||||
#define USB_DRD_FS_CH_NBR (8U) /*!< Number of USB Host channels */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
|
|
@ -23773,7 +23814,6 @@ typedef struct
|
|||
/******************************* PKA Instances ********************************/
|
||||
#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))
|
||||
|
||||
|
||||
/******************************* CORDIC Instances *****************************/
|
||||
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
|
||||
|
||||
|
|
@ -23818,6 +23858,11 @@ typedef struct
|
|||
((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S))
|
||||
|
||||
#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \
|
||||
((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \
|
||||
((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S))
|
||||
|
||||
/****************************** OTFDEC Instances ********************************/
|
||||
#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S))
|
||||
|
||||
|
|
@ -24346,6 +24391,9 @@ typedef struct
|
|||
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \
|
||||
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
|
||||
|
||||
/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/
|
||||
#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
|
||||
|
||||
/****************** TIM Instances : Advanced timer instances *******************/
|
||||
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
|
||||
((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S))
|
||||
|
|
@ -24543,7 +24591,6 @@ typedef struct
|
|||
/******************************* USB DRD FS PCD Instances *************************/
|
||||
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))
|
||||
|
||||
|
||||
/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
|
||||
|
||||
/** @} */ /* End of group STM32H573xx */
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@
|
|||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32H5xx device used in the target application
|
||||
* - To use or not the peripheral's drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral's registers
|
||||
* - To use or not the peripheral drivers in application code(i.e.
|
||||
* code will be based on direct access to peripherals' registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
|
|
@ -57,12 +57,15 @@
|
|||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32H573xx) && !defined (STM32H563xx) \
|
||||
&& !defined (STM32H562xx) && !defined (STM32H503xx)
|
||||
/* #define STM32H573xx */ /*!< STM32H5753xx Devices */
|
||||
#if !defined (STM32H573xx) && !defined (STM32H563xx) \
|
||||
&& !defined (STM32H562xx) && !defined (STM32H503xx) \
|
||||
&& !defined (STM32H533xx) && !defined (STM32H523xx)
|
||||
/* #define STM32H573xx */ /*!< STM32H573xx Devices */
|
||||
/* #define STM32H563xx */ /*!< STM32H563xx Devices */
|
||||
/* #define STM32H562xx */ /*!< STM32H562xx Devices */
|
||||
/* #define STM32H503xx */ /*!< STM32H503xx Devices */
|
||||
/* #define STM32H503xx */ /*!< STM32H503xx Devices */
|
||||
/* #define STM32H533xx */ /*!< STM32H533xx Devices */
|
||||
/* #define STM32H523xx */ /*!< STM32H523xx Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
|
|
@ -78,12 +81,12 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number 1.1.0
|
||||
* @brief CMSIS Device version number 1.3.0
|
||||
*/
|
||||
#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H5_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32H5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32H5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
|
||||
#define __STM32H5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32H5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\
|
||||
|(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\
|
||||
|(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\
|
||||
|
|
@ -96,7 +99,6 @@
|
|||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H573xx)
|
||||
#include "stm32h573xx.h"
|
||||
#elif defined(STM32H563xx)
|
||||
|
|
@ -105,6 +107,10 @@
|
|||
#include "stm32h562xx.h"
|
||||
#elif defined(STM32H503xx)
|
||||
#include "stm32h503xx.h"
|
||||
#elif defined(STM32H523xx)
|
||||
#include "stm32h523xx.h"
|
||||
#elif defined(STM32H533xx)
|
||||
#include "stm32h533xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -97,7 +97,6 @@ target_sources(mbed-stm32h5cube-fw
|
|||
STM32H5xx_HAL_Driver/stm32h5xx_ll_fmc.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_gpio.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_i2c.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_i3c.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_icache.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_lptim.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_lpuart.c
|
||||
|
|
@ -114,6 +113,9 @@ target_sources(mbed-stm32h5cube-fw
|
|||
STM32H5xx_HAL_Driver/stm32h5xx_ll_usb.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_ll_utils.c
|
||||
STM32H5xx_HAL_Driver/stm32h5xx_util_i3c.c
|
||||
|
||||
# NOTE: Don't compile stm32h5xx_ll_i3c.c, it does not build if the
|
||||
# HAL driver for i3c is enabled due to a circular include issue.
|
||||
)
|
||||
|
||||
target_include_directories(mbed-stm32h5cube-fw
|
||||
|
|
|
|||
|
|
@ -1,15 +1,12 @@
|
|||
# How to add new STM32 family
|
||||
1. In path mbed-os\targets\TARGET_STM\ add new family folder, in our my case TARGET_STM32H5, and also do not forget add same name into CmakeLists.txt in same folder level.
|
||||
2. In path mbed-os\targets\TARGET_STM\TARGET_STM32H5\ prepare another folders. First is STM32Cube_FW and second CMSIS
|
||||
3. Visit https://github.com/STMicroelectronics. Select package for your family and chose latest tag. Then download it as a zip.
|
||||
For example https://github.com/STMicroelectronics/STM32CubeH5/tree/v1.1.0
|
||||
4. Exctract the STM32CubeH5-1.1.0.zip
|
||||
6. From STM32CubeH5-1.1.0\STM32CubeH5-1.1.0\Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates copy system_stm32h5xx.c into mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\
|
||||
5. From STM32CubeH5-1.1.0\Drivers\CMSIS\Device\ST\STM32H5xx\Include\ copy all .h files into mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\CMSIS\
|
||||
6. From STM32CubeH5-1.1.0\Drivers copy dolder STM32H5xx_HAL_Driver folder into mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\
|
||||
8. In mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\STM32H5xx_HAL_Driver could be deleted everyting exclude folders Include and Source.
|
||||
9. Whole content of folders Include and Source (from previous point) move to from their folder to one level up. Then delete both folders.
|
||||
10. From folder STM32Cube_FW\STM32H5xx_HAL_Driver move file stm32h5xx_hal_conf_template.h to one folder level up.
|
||||
3. Clone or download the [stm32h5xx_hal_driver](https://github.com/STMicroelectronics/stm32h5xx_hal_driver) repository
|
||||
4. Copy `stm32h5xx_hal_driver/*.h` and `stm32h5xx_hal_driver/*.c` (but not the _template files) into `mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\STM32H5xx_HAL_Driver`
|
||||
5. Clone or download [cmsis_device_h5](https://github.com/STMicroelectronics/cmsis_device_h5/tree/main)
|
||||
6. Copy `cmsis_device_h5\Include\*.h` to mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\CMSIS\
|
||||
6. From `cmsis_device_h5\Source\Templates` copy system_stm32h5xx.c into mbed-os\targets\TARGET_STM\TARGET_STM32H5\STM32Cube_FW\
|
||||
10. From `stm32h5xx_hal_driver\Inc` move file stm32h5xx_hal_conf_template.h to one folder level up.
|
||||
- Rest of templates could be deleted.
|
||||
- The moved file stm32h5xx_hal_conf_template.h should be renamed to stm32h5xx_hal_conf.h
|
||||
- inside of stm32h5xx_hal_conf_template.h file should be all macros #define USE_HAL_XXXXXXXXX covered by macro #if !defined(USE_HAL_XXXXXXXXX) statement
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
@ -275,7 +275,7 @@ extern "C" {
|
|||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
||||
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
|
||||
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
|
||||
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||
#endif
|
||||
|
|
@ -548,6 +548,16 @@ extern "C" {
|
|||
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
|
||||
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32U0)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_USER_nBOOT1 OB_USER_NBOOT1
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1239,10 +1249,10 @@ extern "C" {
|
|||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H5)
|
||||
#if defined(STM32H5) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
|
||||
#endif /* STM32H5 */
|
||||
#endif /* STM32H5 || STM32H7RS */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
|
|
@ -1254,10 +1264,10 @@ extern "C" {
|
|||
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
|
||||
#endif /* STM32WBA */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32WBA)
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
|
||||
#endif /* STM32H5 || STM32WBA */
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
|
||||
|
|
@ -1595,6 +1605,8 @@ extern "C" {
|
|||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1805,7 +1817,7 @@ extern "C" {
|
|||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
|
||||
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
|
||||
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
|
|
@ -1987,12 +1999,12 @@ extern "C" {
|
|||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA)
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA */
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -2307,8 +2319,8 @@ extern "C" {
|
|||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#endif
|
||||
#if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
|
|
@ -2341,8 +2353,8 @@ extern "C" {
|
|||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#endif
|
||||
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
|
|
@ -2399,8 +2411,8 @@ extern "C" {
|
|||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#endif
|
||||
#if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
|
|
@ -2417,7 +2429,7 @@ extern "C" {
|
|||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
#endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
|
|
@ -2719,6 +2731,12 @@ extern "C" {
|
|||
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
|
||||
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
|
||||
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
|
||||
#if defined(STM32C0)
|
||||
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
|
||||
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
|
||||
#endif /* STM32C0 */
|
||||
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
|
||||
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
|
||||
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
|
||||
|
|
@ -3642,8 +3660,12 @@ extern "C" {
|
|||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0)
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
|
|
@ -3745,8 +3767,10 @@ extern "C" {
|
|||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
|
|
@ -3892,7 +3916,8 @@ extern "C" {
|
|||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
|
||||
defined (STM32WBA) || defined (STM32H5) || \
|
||||
defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
|
|
@ -3929,7 +3954,8 @@ extern "C" {
|
|||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1)
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
|
|
@ -4214,6 +4240,9 @@ extern "C" {
|
|||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -48,10 +48,10 @@
|
|||
/* Private typedef ---------------------------------------------------------------------------------------------------*/
|
||||
/* Private define ----------------------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief STM32H5xx HAL Driver version number 1.1.0
|
||||
* @brief STM32H5xx HAL Driver version number 1.3.0
|
||||
*/
|
||||
#define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32H5XX_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
|
||||
#define __STM32H5XX_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
|
||||
#define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\
|
||||
|
|
@ -132,8 +132,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
|||
* @note HAL_Init() function is called at the beginning of program after reset and before
|
||||
* the clock configuration.
|
||||
*
|
||||
* @note In the default implementation the System Timer (Systick) is used as source of time base.
|
||||
* The Systick configuration is based on HSI clock, as HSI is the clock
|
||||
* @note In the default implementation the System Timer (SysTick) is used as source of time base.
|
||||
* The SysTick configuration is based on HSI clock, as HSI is the clock
|
||||
* used after a system Reset and the NVIC configuration is set to Priority group 4.
|
||||
* Once done, time base tick starts incrementing: the tick variable counter is incremented
|
||||
* each 1ms in the SysTick_Handler() interrupt handler.
|
||||
|
|
@ -153,6 +153,9 @@ HAL_StatusTypeDef HAL_Init(void)
|
|||
/* Update the SystemCoreClock global variable */
|
||||
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
|
||||
|
||||
/* Select HCLK as SysTick clock source */
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
||||
{
|
||||
|
|
@ -241,28 +244,56 @@ __weak void HAL_MspDeInit(void)
|
|||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
uint32_t ticknumber = 0U;
|
||||
uint32_t systicksel;
|
||||
|
||||
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
|
||||
if ((uint32_t)uwTickFreq == 0UL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check Clock source to calculate the tickNumber */
|
||||
if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk)
|
||||
{
|
||||
/* HCLK selected as SysTick clock source */
|
||||
ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq);
|
||||
}
|
||||
else
|
||||
{
|
||||
systicksel = HAL_SYSTICK_GetCLKSourceConfig();
|
||||
switch (systicksel)
|
||||
{
|
||||
/* HCLK_DIV8 selected as SysTick clock source */
|
||||
case SYSTICK_CLKSOURCE_HCLK_DIV8:
|
||||
/* Calculate tick value */
|
||||
ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq));
|
||||
break;
|
||||
/* LSI selected as SysTick clock source */
|
||||
case SYSTICK_CLKSOURCE_LSI:
|
||||
/* Calculate tick value */
|
||||
ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq));
|
||||
break;
|
||||
/* LSE selected as SysTick clock source */
|
||||
case SYSTICK_CLKSOURCE_LSE:
|
||||
/* Calculate tick value */
|
||||
ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq));
|
||||
break;
|
||||
default:
|
||||
/* Nothing to do */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
|
||||
if (HAL_SYSTICK_Config(ticknumber) > 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
@ -296,7 +327,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in Systick ISR.
|
||||
* in SysTick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
|
|
|
|||
|
|
@ -202,8 +202,8 @@ extern HAL_TickFreqTypeDef uwTickFreq;
|
|||
/** @defgroup SBS_EPOCH_Selection EPOCH Selection
|
||||
* @{
|
||||
*/
|
||||
#define SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */
|
||||
#define SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */
|
||||
#define SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */
|
||||
#define SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */
|
||||
#define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */
|
||||
|
||||
#define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \
|
||||
|
|
@ -231,9 +231,9 @@ extern HAL_TickFreqTypeDef uwTickFreq;
|
|||
* @{
|
||||
*/
|
||||
#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 0 */
|
||||
#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */
|
||||
#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */
|
||||
#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -278,8 +278,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
|
|||
#define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */
|
||||
#define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */
|
||||
#define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */
|
||||
#define SBS_SMPS SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS */
|
||||
#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU | SBS_SMPS) /*!< All */
|
||||
#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU) /*!< All */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -667,7 +666,6 @@ extern HAL_TickFreqTypeDef uwTickFreq;
|
|||
#define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \
|
||||
(((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \
|
||||
(((__ITEM__) & SBS_FPU) == SBS_FPU) || \
|
||||
(((__ITEM__) & SBS_SMPS) == SBS_SMPS) || \
|
||||
(((__ITEM__) & ~(SBS_ALL)) == 0U))
|
||||
|
||||
#define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\
|
||||
|
|
|
|||
|
|
@ -1754,6 +1754,30 @@ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
|
|||
(__ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the voltage (unit: mVolt)
|
||||
* corresponding to a ADC conversion data (unit: digital value)
|
||||
* in differential ended mode.
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
|
||||
* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
|
||||
* (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
|
||||
*/
|
||||
#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
|
||||
__ADC_DATA__,\
|
||||
__ADC_RESOLUTION__) \
|
||||
__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
|
||||
(__ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate analog reference voltage (Vref+)
|
||||
* (unit: mVolt) from ADC conversion data of internal voltage
|
||||
|
|
|
|||
|
|
@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic,
|
|||
static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
|
||||
static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
|
||||
static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1141,7 +1141,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
|
|||
/*Call registered callback*/
|
||||
hcordic->CalculateCpltCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_CalculateCpltCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1282,7 +1282,7 @@ static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
|
|||
/*Call registered callback*/
|
||||
hcordic->CalculateCpltCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_CalculateCpltCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1311,7 +1311,7 @@ static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
|
|||
/*Call registered callback*/
|
||||
hcordic->CalculateCpltCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_CalculateCpltCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
@ -1336,7 +1336,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
|
|||
/*Call registered callback*/
|
||||
hcordic->ErrorCallback(hcordic);
|
||||
#else
|
||||
/*Call legacy weak (surcharged) callback*/
|
||||
/*Call legacy weak callback*/
|
||||
HAL_CORDIC_ErrorCallback(hcordic);
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
|
||||
* @{
|
||||
|
|
@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
|
||||
#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
|
||||
#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
|
||||
|CORDIC_CSR_PRECISION_0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
* @{
|
||||
*/
|
||||
#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
*/
|
||||
#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
|
||||
#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
*/
|
||||
#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
|
||||
#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
* @{
|
||||
*/
|
||||
#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
|
||||
#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
|
||||
#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
(__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
|
||||
|
|
@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
|
|||
/* Peripheral State functions *************************************************/
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
|
||||
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -392,7 +392,23 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
|||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
/* Reload value impossible */
|
||||
return (1UL);
|
||||
}
|
||||
|
||||
/* Set reload register */
|
||||
WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL));
|
||||
|
||||
/* Load the SysTick Counter Value */
|
||||
WRITE_REG(SysTick->VAL, 0UL);
|
||||
|
||||
/* Enable SysTick IRQ and SysTick Timer */
|
||||
SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk));
|
||||
|
||||
/* Function successful */
|
||||
return (0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -436,6 +452,52 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SysTick clock source configuration.
|
||||
* @retval SysTick clock source that can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_GetCLKSourceConfig(void)
|
||||
{
|
||||
uint32_t systick_source;
|
||||
uint32_t systick_rcc_source;
|
||||
|
||||
/* Read SysTick->CTRL register for internal or external clock source */
|
||||
if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U)
|
||||
{
|
||||
/* Internal clock source */
|
||||
systick_source = SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* External clock source, check the selected one in RCC */
|
||||
systick_rcc_source = READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL);
|
||||
|
||||
switch (systick_rcc_source)
|
||||
{
|
||||
case (0x00000000U):
|
||||
systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8;
|
||||
break;
|
||||
|
||||
case (RCC_CCIPR4_SYSTICKSEL_0):
|
||||
systick_source = SYSTICK_CLKSOURCE_LSI;
|
||||
break;
|
||||
|
||||
case (RCC_CCIPR4_SYSTICKSEL_1):
|
||||
systick_source = SYSTICK_CLKSOURCE_LSE;
|
||||
break;
|
||||
|
||||
default:
|
||||
systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return systick_source;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle SYSTICK interrupt request.
|
||||
* @retval None
|
||||
|
|
@ -573,6 +635,82 @@ void HAL_MPU_Disable_NS(void)
|
|||
}
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @brief Enable the MPU Region.
|
||||
* @param RegionNumber Specifies the index of the region to enable.
|
||||
* this parameter can be a value of @ref CORTEX_MPU_Region_Number
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Enable the Region */
|
||||
SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
|
||||
}
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/**
|
||||
* @brief Enable the MPU_NS Region.
|
||||
* @param RegionNumber Specifies the index of the region to enable.
|
||||
* this parameter can be a value of @ref CORTEX_MPU_Region_Number
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER_NS(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU_NS->RNR = RegionNumber;
|
||||
|
||||
/* Enable the Region */
|
||||
SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
|
||||
}
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @brief Disable the MPU Region.
|
||||
* @param RegionNumber Specifies the index of the region to disable.
|
||||
* this parameter can be a value of @ref CORTEX_MPU_Region_Number
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
|
||||
}
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/**
|
||||
* @brief Disable the MPU_NS Region.
|
||||
* @param RegionNumber Specifies the index of the region to disable.
|
||||
* this parameter can be a value of @ref CORTEX_MPU_Region_Number
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER_NS(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU_NS->RNR = RegionNumber;
|
||||
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
|
||||
}
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/**
|
||||
* @brief Initialize and configure the Region and the memory to be protected.
|
||||
* @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
|
|
@ -650,6 +788,9 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const
|
|||
#endif /* __ARM_FEATURE_CMSE */
|
||||
assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
|
||||
|
||||
/* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
|
||||
__DMB();
|
||||
|
|
@ -657,27 +798,17 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const
|
|||
/* Set the Region number */
|
||||
MPUx->RNR = pMPU_RegionInit->Number;
|
||||
|
||||
if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPUx->RLAR, MPU_RLAR_EN_Msk);
|
||||
|
||||
MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
|
||||
((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
|
||||
((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
|
||||
((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
|
||||
MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
|
||||
((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
|
||||
((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
|
||||
((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
|
||||
|
||||
MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
|
||||
((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
|
||||
((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
|
||||
}
|
||||
else
|
||||
{
|
||||
MPUx->RLAR = 0U;
|
||||
MPUx->RBAR = 0U;
|
||||
}
|
||||
MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
|
||||
((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
|
||||
((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */
|
||||
#define MPU_ACCESS_OUTER_SHAREABLE 1U /*!< MPU region outer shareable */
|
||||
#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< MPU region outer shareable */
|
||||
#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -282,6 +282,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
|||
/* SYSTICK functions ***********************************************/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
uint32_t HAL_SYSTICK_GetCLKSourceConfig(void);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
|
|
@ -295,12 +296,16 @@ void HAL_SYSTICK_Callback(void);
|
|||
/* MPU functions ***********************************************/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
|
||||
void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* MPU_NS Control functions ***********************************************/
|
||||
void HAL_MPU_Enable_NS(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable_NS(void);
|
||||
void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
|
||||
void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
|
@ -368,6 +373,15 @@ void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const p
|
|||
((NUMBER) == MPU_REGION_NUMBER9) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER10)|| \
|
||||
((NUMBER) == MPU_REGION_NUMBER11))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER_NS(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
#else
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
|||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Reset IDR register content */
|
||||
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
|
||||
CLEAR_REG(hcrc->Instance->IDR);
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
|
|
|||
|
|
@ -2005,26 +2005,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp
|
|||
*/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
|
||||
{
|
||||
uint32_t itsource = hcryp->Instance->IER;
|
||||
uint32_t itflagsr = hcryp->Instance->SR;
|
||||
uint32_t itflagisr = hcryp->Instance->ISR;
|
||||
|
||||
/* Check if Read or write error occurred */
|
||||
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET)
|
||||
if ((itsource & CRYP_IT_RWEIE) != 0U)
|
||||
{
|
||||
/* If write Error occurred */
|
||||
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET)
|
||||
if ((itflagsr & CRYP_FLAG_WRERR) != 0U)
|
||||
{
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
|
||||
}
|
||||
/* If read Error occurred */
|
||||
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET)
|
||||
if ((itflagsr & CRYP_FLAG_RDERR) != 0U)
|
||||
{
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
|
||||
}
|
||||
}
|
||||
/* Check if Key error occurred */
|
||||
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET)
|
||||
if ((itsource & CRYP_IT_KEIE) != 0U)
|
||||
{
|
||||
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET)
|
||||
if ((itflagisr & CRYP_FLAG_KEIF) != 0U)
|
||||
{
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY;
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF);
|
||||
|
|
@ -2033,9 +2037,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
|
|||
}
|
||||
}
|
||||
|
||||
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
|
||||
if ((itflagisr & CRYP_FLAG_CCF) != 0U)
|
||||
{
|
||||
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
|
||||
if ((itsource & CRYP_IT_CCFIE) != 0U)
|
||||
{
|
||||
/* Clear computation complete flag */
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
|
||||
|
|
|
|||
|
|
@ -943,6 +943,22 @@ uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_HandleTypeDef *hdcach
|
|||
return hdcache->Instance->WMMONR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCACHE_Exported_Functions_Group3
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DCACHE IRQ Handler and Callback functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to treat ISR and provide user callback
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle the Data Cache interrupt request.
|
||||
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
|
||||
|
|
@ -1321,7 +1337,7 @@ __weak void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCACHE_Exported_Functions_Group3
|
||||
/** @addtogroup DCACHE_Exported_Functions_Group4
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
|
|
@ -1359,6 +1375,10 @@ uint32_t HAL_DCACHE_GetError(const DCACHE_HandleTypeDef *hdcache)
|
|||
return hdcache->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
**********************************************************************************************************************
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### How to use this driver ###############
|
||||
##### How to use this driver #####
|
||||
======================================================================================================================
|
||||
|
||||
|
||||
|
|
@ -96,8 +96,9 @@
|
|||
(++) can be a value of DMA_Transfer_Event_Mode
|
||||
|
||||
(+) Mode : Specifies the transfer mode for the DMA channel
|
||||
(++) can be a value of DMA_Transfer_Mode
|
||||
|
||||
(++) can be one of the following modes :
|
||||
(+++) DMA_NORMAL : Normal Mode
|
||||
(+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
|
|
@ -218,7 +219,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma);
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Initialization and de-initialization functions ###############
|
||||
##### Initialization and de-initialization functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode.
|
||||
|
|
@ -252,7 +253,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
|
|||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
if ((hdma->Init.Direction == DMA_MEMORY_TO_PERIPH) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
|
||||
if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
assert_param(IS_DMA_REQUEST(hdma->Init.Request));
|
||||
}
|
||||
|
|
@ -264,6 +265,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
|
|||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
if (hdma->Init.Mode == DMA_PFCTRL)
|
||||
{
|
||||
assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance));
|
||||
}
|
||||
/* Check DMA channel instance */
|
||||
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
|
||||
{
|
||||
|
|
@ -379,7 +384,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
|
|||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Clear secure attribute */
|
||||
CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
|
||||
|
|
@ -423,7 +428,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### IO operation functions ###############
|
||||
##### IO operation functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -892,14 +897,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
|
|||
uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag);
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag);
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/* Global Interrupt Flag management *********************************************************************************/
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U))
|
||||
#else
|
||||
if (global_active_flag_ns == 0U)
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
{
|
||||
return; /* the global interrupt flag for the current channel is down , nothing to do */
|
||||
}
|
||||
|
|
@ -996,16 +1001,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
|
|||
/* Reset the channel internal state and reset the FIFO */
|
||||
hdma->Instance->CCR |= DMA_CCR_RESET;
|
||||
|
||||
if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
|
||||
{
|
||||
/* Update the DMA channel state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the DMA channel state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
/* Update the DMA channel state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Check DMA channel transfer mode */
|
||||
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
|
||||
|
|
@ -1097,16 +1094,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
|
|||
/* Reset the channel internal state and reset the FIFO */
|
||||
hdma->Instance->CCR |= DMA_CCR_RESET;
|
||||
|
||||
if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
|
||||
{
|
||||
/* Update the DMA channel state */
|
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the DMA channel state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
/* Update the DMA channel state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Check DMA channel transfer mode */
|
||||
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
|
||||
|
|
@ -1303,7 +1292,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### State and Errors functions ###############
|
||||
##### State and Errors functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -1349,7 +1338,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma)
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### DMA Attributes functions ###############
|
||||
##### DMA Attributes functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -1456,7 +1445,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma,
|
|||
hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC);
|
||||
}
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -1490,7 +1479,7 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co
|
|||
/* Get DMA channel privilege attribute */
|
||||
attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV;
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#if defined (DMA_SECCFGR_SEC0)
|
||||
/* Get DMA channel security attribute */
|
||||
attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC;
|
||||
|
||||
|
|
@ -1499,8 +1488,8 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co
|
|||
|
||||
/* Get DMA channel destination security attribute */
|
||||
attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC;
|
||||
#endif /* DMA_SECCFGR_SEC0 */
|
||||
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
/* return value */
|
||||
*pChannelAttributes = attributes;
|
||||
|
||||
|
|
@ -1538,7 +1527,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h
|
|||
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/**
|
||||
* @brief Get the security and privilege attribute lock state of a DMA channel.
|
||||
|
|
@ -1571,7 +1560,7 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
|
|||
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif /* defined (DMA_RCFGLOCKR_LOCK0) */
|
||||
#endif /* DMA_RCFGLOCKR_LOCK0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1647,7 +1636,7 @@ static void DMA_Init(DMA_HandleTypeDef const *const hdma)
|
|||
MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg);
|
||||
#else
|
||||
WRITE_REG(hdma->Instance->CTR1, tmpreg);
|
||||
#endif /* defined (DMA_CTR1_SSEC) */
|
||||
#endif /* DMA_CTR1_SSEC */
|
||||
|
||||
/* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/
|
||||
tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode;
|
||||
|
|
|
|||
|
|
@ -663,7 +663,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
#endif /* I3C2 */
|
||||
|
||||
/* Software request */
|
||||
#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */
|
||||
#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -807,7 +807,6 @@ typedef struct __DMA_HandleTypeDef
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1017,11 +1016,11 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co
|
|||
#if defined (DMA_RCFGLOCKR_LOCK0)
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma);
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma,
|
||||
uint32_t *const pLockState);
|
||||
|
||||
#endif /* defined (DMA_RCFGLOCKR_LOCK0) */
|
||||
#endif /* DMA_RCFGLOCKR_LOCK0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1137,12 +1136,12 @@ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *cons
|
|||
#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \
|
||||
(((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \
|
||||
((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \
|
||||
(((INSTANCE)->SMISR & (GLOBAL_FLAG)))
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \
|
||||
(((INSTANCE)->MISR & (GLOBAL_FLAG)))
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
**********************************************************************************************************************
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### How to use this driver ###############
|
||||
##### How to use this driver #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as
|
||||
|
|
@ -581,7 +581,7 @@ static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList);
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Linked-List Initialization and De-Initialization Functions ###############
|
||||
##### Linked-List Initialization and De-Initialization Functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode.
|
||||
|
|
@ -676,7 +676,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
|
|||
/* Get DMA instance */
|
||||
DMA_TypeDef *p_dma_instance;
|
||||
|
||||
|
||||
/* Get tick number */
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
|
|
@ -693,7 +692,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
|
|||
/* Get DMA instance */
|
||||
p_dma_instance = GET_DMA_INSTANCE(hdma);
|
||||
|
||||
|
||||
/* Disable the selected DMA Channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
|
|
@ -738,7 +736,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
|
|||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
/* Clear secure attribute */
|
||||
CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
|
||||
|
|
@ -790,7 +788,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Linked-List IO Operation Functions ###############
|
||||
##### Linked-List IO Operation Functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -956,7 +954,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma)
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Linked-List Management Functions ###############
|
||||
##### Linked-List Management Functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -1103,7 +1101,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod
|
|||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure));
|
||||
assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure));
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/* Build the DMA channel node */
|
||||
DMA_List_BuildNode(pNodeConfig, pNode);
|
||||
|
|
@ -3223,7 +3221,7 @@ HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma)
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Data handling, repeated block and trigger configuration functions ###############
|
||||
##### Data handling, repeated block and trigger configuration functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -3449,7 +3447,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Suspend and resume operation functions ###############
|
||||
##### Suspend and resume operation functions #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides functions allowing to :
|
||||
|
|
@ -3612,7 +3610,7 @@ HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma)
|
|||
*
|
||||
@verbatim
|
||||
======================================================================================================================
|
||||
############### Fifo status function ###############
|
||||
##### Fifo status function #####
|
||||
======================================================================================================================
|
||||
[..]
|
||||
This section provides function allowing to get DMA channel FIFO level.
|
||||
|
|
@ -3734,7 +3732,7 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
|
|||
{
|
||||
pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC;
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
/* Add parameters related to DMA configuration */
|
||||
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
|
||||
|
|
@ -3972,7 +3970,7 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
|
|||
{
|
||||
pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC;
|
||||
}
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
/*********************************************************************************** CTR1 fields values are updated */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ typedef struct
|
|||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
uint32_t SrcSecure; /*!< Specifies the source security attribute */
|
||||
uint32_t DestSecure; /*!< Specifies the destination security attribute */
|
||||
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
} DMA_NodeConfTypeDef;
|
||||
|
||||
|
|
@ -235,11 +235,9 @@ typedef struct __DMA_QListTypeDef
|
|||
=> Left Aligned Right Truncated down to the
|
||||
destination data width */
|
||||
#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
|
||||
=> Packed at the destination data width
|
||||
(Available only for GPDMA) */
|
||||
=> Packed at the destination data width */
|
||||
#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
|
||||
=> Unpacked at the destination data width
|
||||
(Available only for GPDMA) */
|
||||
=> Unpacked at the destination data width */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -345,9 +343,9 @@ typedef struct __DMA_QListTypeDef
|
|||
#if defined (COMP1)
|
||||
#define GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* COMP1 */
|
||||
#if defined (STM32H503xx)
|
||||
#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx)
|
||||
#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */
|
||||
#endif /* STM32H503xx || STM32H523xx || STM32H533xx */
|
||||
|
||||
/* GPDMA2 triggers */
|
||||
#define GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */
|
||||
|
|
@ -409,9 +407,9 @@ typedef struct __DMA_QListTypeDef
|
|||
#if defined (COMP1)
|
||||
#define GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* COMP1 */
|
||||
#if defined (STM32H503xx)
|
||||
#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx)
|
||||
#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */
|
||||
#endif /* STM32H503xx || STM32H523xx || STM32H533xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -250,12 +250,13 @@
|
|||
/** @defgroup ETH_Private_Functions ETH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
|
||||
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
|
||||
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
|
||||
static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
|
||||
static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
|
||||
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
|
||||
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
|
||||
uint32_t ItMode);
|
||||
static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
|
|
@ -336,7 +337,6 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
|
|||
|
||||
__HAL_RCC_SBS_CLK_ENABLE();
|
||||
|
||||
|
||||
if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
|
||||
{
|
||||
HAL_SBS_ETHInterfaceSelect(SBS_ETH_MII);
|
||||
|
|
@ -411,6 +411,14 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
|
|||
heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
|
||||
((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
|
||||
|
||||
/* Disable Rx MMC Interrupts */
|
||||
SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
|
||||
ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
|
||||
|
||||
/* Disable Tx MMC Interrupts */
|
||||
SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
|
||||
ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
|
||||
|
||||
heth->ErrorCode = HAL_ETH_ERROR_NONE;
|
||||
heth->gState = HAL_ETH_STATE_READY;
|
||||
|
||||
|
|
@ -712,7 +720,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
|
|||
{
|
||||
heth->gState = HAL_ETH_STATE_BUSY;
|
||||
|
||||
/* Set nombre of descriptors to build */
|
||||
/* Set number of descriptors to build */
|
||||
heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
|
||||
|
||||
/* Build all descriptors */
|
||||
|
|
@ -760,29 +768,13 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
|
|||
|
||||
/* save IT mode to ETH Handle */
|
||||
heth->RxDescList.ItMode = 1U;
|
||||
/* Disable Rx MMC Interrupts */
|
||||
SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
|
||||
ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
|
||||
|
||||
/* Disable Tx MMC Interrupts */
|
||||
SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
|
||||
ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
|
||||
|
||||
/* Set nombre of descriptors to build */
|
||||
/* Set number of descriptors to build */
|
||||
heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
|
||||
|
||||
/* Build all descriptors */
|
||||
ETH_UpdateDescriptor(heth);
|
||||
|
||||
/* Enable the MAC transmission */
|
||||
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
|
||||
|
||||
/* Enable the MAC reception */
|
||||
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
|
||||
|
||||
/* Set the Flush Transmit FIFO bit */
|
||||
SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
|
||||
|
||||
/* Enable the DMA transmission */
|
||||
SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
|
||||
|
||||
|
|
@ -791,6 +783,16 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
|
|||
|
||||
/* Clear Tx and Rx process stopped flags */
|
||||
heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
|
||||
|
||||
/* Set the Flush Transmit FIFO bit */
|
||||
SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
|
||||
|
||||
/* Enable the MAC transmission */
|
||||
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
|
||||
|
||||
/* Enable the MAC reception */
|
||||
SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
|
||||
|
||||
/* Enable ETH DMA interrupts:
|
||||
- Tx complete interrupt
|
||||
- Rx complete interrupt
|
||||
|
|
@ -914,7 +916,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
|
|||
* @param Timeout: timeout value
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
ETH_DMADescTypeDef *dmatxdesc;
|
||||
|
|
@ -989,7 +991,7 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
|
|||
* @param pTxConfig: Hold the configuration of packet to be transmitted
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
|
||||
{
|
||||
if (pTxConfig == NULL)
|
||||
{
|
||||
|
|
@ -1079,12 +1081,12 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
|
|||
heth->RxDescList.RxDataLength = 0;
|
||||
}
|
||||
|
||||
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
||||
bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
|
||||
|
||||
/* Check if last descriptor */
|
||||
bufflength = heth->Init.RxBuffLen;
|
||||
if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
|
||||
{
|
||||
bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
|
||||
|
||||
/* Save Last descriptor index */
|
||||
heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
|
||||
|
||||
|
|
@ -1150,6 +1152,7 @@ HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
|
|||
static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
uint32_t descidx;
|
||||
uint32_t tailidx;
|
||||
uint32_t desccount;
|
||||
ETH_DMADescTypeDef *dmarxdesc;
|
||||
uint8_t *buff = NULL;
|
||||
|
|
@ -1185,8 +1188,6 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
|
|||
|
||||
if (allocStatus != 0U)
|
||||
{
|
||||
/* Ensure rest of descriptor is written to RAM before the OWN bit */
|
||||
__DMB();
|
||||
|
||||
if (heth->RxDescList.ItMode != 0U)
|
||||
{
|
||||
|
|
@ -1207,8 +1208,14 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
|
|||
|
||||
if (heth->RxDescList.RxBuildDescCnt != desccount)
|
||||
{
|
||||
/* Set the tail pointer index */
|
||||
tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
|
||||
|
||||
/* DMB instruction to avoid race condition */
|
||||
__DMB();
|
||||
|
||||
/* Set the Tail pointer address */
|
||||
WRITE_REG(heth->Instance->DMACRDTPR, 0U);
|
||||
WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (tailidx))));
|
||||
|
||||
heth->RxDescList.RxBuildDescIdx = descidx;
|
||||
heth->RxDescList.RxBuildDescCnt = desccount;
|
||||
|
|
@ -1327,7 +1334,7 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
|
|||
* @param pErrorCode: pointer to uint32_t to hold the error code
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
|
||||
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
|
||||
{
|
||||
/* Get error bits. */
|
||||
*pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
|
||||
|
|
@ -1410,7 +1417,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
|
|||
if (dmatxdesclist->PacketAddress[idx] == NULL)
|
||||
{
|
||||
/* No packet in use, skip to next. */
|
||||
idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
|
||||
INCR_TX_DESC_INDEX(idx, 1U);
|
||||
pktInUse = 0U;
|
||||
}
|
||||
|
||||
|
|
@ -1420,20 +1427,32 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
|
|||
if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
|
||||
{
|
||||
#ifdef HAL_ETH_USE_PTP
|
||||
|
||||
/* Disable Ptp transmission */
|
||||
CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U));
|
||||
|
||||
/* Get timestamp low */
|
||||
timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
|
||||
/* Get timestamp high */
|
||||
timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
|
||||
if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD)
|
||||
&& (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
|
||||
{
|
||||
/* Get timestamp low */
|
||||
timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
|
||||
/* Get timestamp high */
|
||||
timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
|
||||
}
|
||||
else
|
||||
{
|
||||
timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
|
||||
}
|
||||
#endif /* HAL_ETH_USE_PTP */
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered callbacks*/
|
||||
#ifdef HAL_ETH_USE_PTP
|
||||
/* Handle Ptp */
|
||||
heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
|
||||
if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
|
||||
{
|
||||
heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
|
||||
}
|
||||
#endif /* HAL_ETH_USE_PTP */
|
||||
/* Release the packet. */
|
||||
heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
|
||||
|
|
@ -1441,7 +1460,10 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
|
|||
/* Call callbacks */
|
||||
#ifdef HAL_ETH_USE_PTP
|
||||
/* Handle Ptp */
|
||||
HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
|
||||
if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
|
||||
{
|
||||
HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
|
||||
}
|
||||
#endif /* HAL_ETH_USE_PTP */
|
||||
/* Release the packet. */
|
||||
HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
|
||||
|
|
@ -1451,7 +1473,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
|
|||
dmatxdesclist->PacketAddress[idx] = NULL;
|
||||
|
||||
/* Update the transmit relesae index and number of buffers in use. */
|
||||
idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
|
||||
INCR_TX_DESC_INDEX(idx, 1U);
|
||||
dmatxdesclist->BuffersInUse = numOfBuf;
|
||||
dmatxdesclist->releaseIndex = idx;
|
||||
}
|
||||
|
|
@ -1511,25 +1533,24 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
|
|||
if (ptpconfig->TimestampAddendUpdate == ENABLE)
|
||||
{
|
||||
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
|
||||
while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {}
|
||||
}
|
||||
while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0)
|
||||
{
|
||||
|
||||
/* Enable Update mode */
|
||||
if (ptpconfig->TimestampUpdateMode == ENABLE)
|
||||
{
|
||||
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT);
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize Time */
|
||||
time.Seconds = 0;
|
||||
time.NanoSeconds = 0;
|
||||
HAL_ETH_PTP_SetTime(heth, &time);
|
||||
|
||||
/* Ptp Init */
|
||||
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
|
||||
|
||||
/* Set PTP Configuration done */
|
||||
heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED;
|
||||
heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
|
||||
|
||||
/* Set Seconds */
|
||||
time.Seconds = heth->Instance->MACSTSR;
|
||||
/* Set NanoSeconds */
|
||||
time.NanoSeconds = heth->Instance->MACSTNR;
|
||||
|
||||
HAL_ETH_PTP_SetTime(heth, &time);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
@ -1589,13 +1610,13 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigT
|
|||
* @brief Set Seconds and Nanoseconds for the Ethernet PTP registers.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param heth: pointer to a ETH_TimeTypeDef structure that contains
|
||||
* @param time: pointer to a ETH_TimeTypeDef structure that contains
|
||||
* time to set
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
|
||||
{
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Set Seconds */
|
||||
heth->Instance->MACSTSUR = time->Seconds;
|
||||
|
|
@ -1603,6 +1624,9 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
|
|||
/* Set NanoSeconds */
|
||||
heth->Instance->MACSTNUR = time->NanoSeconds;
|
||||
|
||||
/* the system time is updated */
|
||||
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -1617,19 +1641,18 @@ HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
|
|||
* @brief Get Seconds and Nanoseconds for the Ethernet PTP registers.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param heth: pointer to a ETH_TimeTypeDef structure that contains
|
||||
* @param time: pointer to a ETH_TimeTypeDef structure that contains
|
||||
* time to get
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
|
||||
{
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Get Seconds */
|
||||
time->Seconds = heth->Instance->MACSTSUR;
|
||||
|
||||
time->Seconds = heth->Instance->MACSTSR;
|
||||
/* Get NanoSeconds */
|
||||
time->NanoSeconds = heth->Instance->MACSTNUR;
|
||||
time->NanoSeconds = heth->Instance->MACSTNR;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
|
|
@ -1645,14 +1668,14 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *
|
|||
* @brief Update time for the Ethernet PTP registers.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains
|
||||
* @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
|
||||
* the time update information
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
|
||||
ETH_TimeTypeDef *timeoffset)
|
||||
{
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE)
|
||||
{
|
||||
|
|
@ -1678,6 +1701,8 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
|
|||
heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
|
||||
}
|
||||
|
||||
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -1692,7 +1717,6 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda
|
|||
* @brief Insert Timestamp in transmission.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
* the configuration information for ETHERNET module
|
||||
* @param txtimestampconf: Enable or Disable timestamp in transmission
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
|
||||
|
|
@ -1701,7 +1725,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
|
|||
uint32_t descidx = dmatxdesclist->CurTxDesc;
|
||||
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
|
||||
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Enable Time Stamp transmission */
|
||||
SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
|
||||
|
|
@ -1730,7 +1754,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt
|
|||
uint32_t idx = dmatxdesclist->releaseIndex;
|
||||
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
|
||||
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Get timestamp low */
|
||||
timestamp->TimeStampLow = dmatxdesc->DESC0;
|
||||
|
|
@ -1757,7 +1781,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeSt
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
|
||||
{
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
|
||||
if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
|
||||
{
|
||||
/* Get timestamp low */
|
||||
timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
|
||||
|
|
@ -1811,6 +1835,8 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
|
|||
/**
|
||||
* @brief Tx Ptp callback.
|
||||
* @param buff: pointer to application buffer
|
||||
* @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains
|
||||
* transmission timestamp
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
|
||||
|
|
@ -1831,87 +1857,79 @@ __weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestam
|
|||
*/
|
||||
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
uint32_t macirqenable;
|
||||
uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
|
||||
uint32_t dma_flag = READ_REG(heth->Instance->DMACSR);
|
||||
uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER);
|
||||
uint32_t exti_flag = READ_REG(EXTI->RPR2);
|
||||
|
||||
/* Packet received */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
|
||||
if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U))
|
||||
{
|
||||
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
|
||||
{
|
||||
/* Clear the Eth DMA Rx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
|
||||
/* Clear the Eth DMA Rx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Receive complete callback*/
|
||||
heth->RxCpltCallback(heth);
|
||||
/*Call registered Receive complete callback*/
|
||||
heth->RxCpltCallback(heth);
|
||||
#else
|
||||
/* Receive complete callback */
|
||||
HAL_ETH_RxCpltCallback(heth);
|
||||
/* Receive complete callback */
|
||||
HAL_ETH_RxCpltCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
/* Packet transmitted */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
|
||||
if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U))
|
||||
{
|
||||
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
|
||||
{
|
||||
/* Clear the Eth DMA Tx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
|
||||
/* Clear the Eth DMA Tx IT pending bits */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
|
||||
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/*Call registered Transmit complete callback*/
|
||||
heth->TxCpltCallback(heth);
|
||||
/*Call registered Transmit complete callback*/
|
||||
heth->TxCpltCallback(heth);
|
||||
#else
|
||||
/* Transfer complete callback */
|
||||
HAL_ETH_TxCpltCallback(heth);
|
||||
/* Transfer complete callback */
|
||||
HAL_ETH_TxCpltCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
/* ETH DMA Error */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
|
||||
if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U))
|
||||
{
|
||||
if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
|
||||
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
|
||||
/* if fatal bus error occurred */
|
||||
if ((dma_flag & ETH_DMACSR_FBE) != 0U)
|
||||
{
|
||||
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
|
||||
/* if fatal bus error occurred */
|
||||
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
|
||||
{
|
||||
/* Get DMA error code */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
|
||||
/* Get DMA error code */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
|
||||
|
||||
/* Disable all interrupts */
|
||||
__HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
|
||||
|
||||
/* Set HAL state to ERROR */
|
||||
heth->gState = HAL_ETH_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA error status */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
|
||||
/* Clear the interrupt summary flag */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
}
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered Error callback*/
|
||||
heth->ErrorCallback(heth);
|
||||
#else
|
||||
/* Ethernet DMA Error callback */
|
||||
HAL_ETH_ErrorCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
/* Disable all interrupts */
|
||||
__HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
|
||||
|
||||
/* Set HAL state to ERROR */
|
||||
heth->gState = HAL_ETH_STATE_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA error status */
|
||||
heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
|
||||
/* Clear the interrupt summary flag */
|
||||
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
|
||||
ETH_DMACSR_RBU | ETH_DMACSR_AIS));
|
||||
}
|
||||
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered Error callback*/
|
||||
heth->ErrorCallback(heth);
|
||||
#else
|
||||
/* Ethernet DMA Error callback */
|
||||
HAL_ETH_ErrorCallback(heth);
|
||||
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* ETH MAC Error IT */
|
||||
macirqenable = heth->Instance->MACIER;
|
||||
if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
|
||||
((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
|
||||
if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
|
||||
((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
|
||||
{
|
||||
heth->ErrorCode |= HAL_ETH_ERROR_MAC;
|
||||
|
||||
|
|
@ -1931,7 +1949,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
|||
}
|
||||
|
||||
/* ETH PMT IT */
|
||||
if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
|
||||
if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
|
||||
{
|
||||
/* Get MAC Wake-up source and clear the status register pending bit */
|
||||
heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
|
||||
|
|
@ -1948,7 +1966,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
|||
}
|
||||
|
||||
/* ETH EEE IT */
|
||||
if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
|
||||
if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
|
||||
{
|
||||
/* Get MAC LPI interrupt source and clear the status register pending bit */
|
||||
heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
|
||||
|
|
@ -1965,7 +1983,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
|||
}
|
||||
|
||||
/* check ETH WAKEUP exti flag */
|
||||
if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
|
||||
if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
|
||||
{
|
||||
/* Clear ETH WAKEUP Exti pending bit */
|
||||
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
|
||||
|
|
@ -2124,7 +2142,6 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Writes to a PHY register.
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
|
|
@ -2206,7 +2223,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32
|
|||
* the configuration of the MAC.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
|
||||
{
|
||||
if (macconf == NULL)
|
||||
{
|
||||
|
|
@ -2278,7 +2295,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
|
|||
* the configuration of the ETH DMA.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
|
||||
{
|
||||
if (dmaconf == NULL)
|
||||
{
|
||||
|
|
@ -2301,7 +2318,6 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
|
|||
dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
|
||||
dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
|
||||
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -2380,34 +2396,34 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
|
|||
hclk = HAL_RCC_GetHCLKFreq();
|
||||
|
||||
/* Set CR bits depending on hclk value */
|
||||
if ((hclk >= 20000000U) && (hclk < 35000000U))
|
||||
if (hclk < 35000000U)
|
||||
{
|
||||
/* CSR Clock Range between 20-35 MHz */
|
||||
/* CSR Clock Range between 0-35 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
|
||||
}
|
||||
else if ((hclk >= 35000000U) && (hclk < 60000000U))
|
||||
else if (hclk < 60000000U)
|
||||
{
|
||||
/* CSR Clock Range between 35-60 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
|
||||
}
|
||||
else if ((hclk >= 60000000U) && (hclk < 100000000U))
|
||||
else if (hclk < 100000000U)
|
||||
{
|
||||
/* CSR Clock Range between 60-100 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
|
||||
}
|
||||
else if ((hclk >= 100000000U) && (hclk < 150000000U))
|
||||
else if (hclk < 150000000U)
|
||||
{
|
||||
/* CSR Clock Range between 100-150 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
|
||||
}
|
||||
else if ((hclk >= 150000000U) && (hclk <= 250000000U))
|
||||
else if (hclk < 250000000U)
|
||||
{
|
||||
/* CSR Clock Range between 150-200 MHz */
|
||||
/* CSR Clock Range between 150-250 MHz */
|
||||
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
|
||||
}
|
||||
else /*(hclk >= 250000000U) && (hclk <= 300000000U)*/
|
||||
else /* (hclk >= 250000000U) */
|
||||
{
|
||||
/* CSR Clock Range between 250-300 MHz */
|
||||
/* CSR Clock >= 250 MHz */
|
||||
tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124);
|
||||
}
|
||||
|
||||
|
|
@ -2457,7 +2473,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_
|
|||
* the configuration of the ETH MAC filters.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
|
||||
{
|
||||
if (pFilterConfig == NULL)
|
||||
{
|
||||
|
|
@ -2730,8 +2746,7 @@ uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
|
||||
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
|
||||
{
|
||||
uint32_t macregval;
|
||||
|
||||
|
|
@ -2778,7 +2793,6 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac
|
|||
/* Write to MACWTR */
|
||||
MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
|
||||
|
||||
|
||||
/*------------------------ MACTFCR Configuration --------------------*/
|
||||
macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
|
||||
macconf->PauseLowThreshold |
|
||||
|
|
@ -2809,7 +2823,7 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac
|
|||
MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
|
||||
}
|
||||
|
||||
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
|
||||
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
|
||||
{
|
||||
uint32_t dmaregval;
|
||||
|
||||
|
|
@ -2916,7 +2930,6 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
|
|||
ETH_SetDMAConfig(heth, &dmaDefaultConf);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMA Tx descriptors.
|
||||
* called by HAL_ETH_Init() API.
|
||||
|
|
@ -2978,7 +2991,6 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
|
|||
WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
|
||||
WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
|
||||
|
||||
|
||||
/* Set Rx descritors addresses */
|
||||
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
|
||||
|
||||
|
|
@ -3009,7 +3021,8 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
|
|||
* @param ItMode: Enable or disable Tx EOT interrept
|
||||
* @retval Status
|
||||
*/
|
||||
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
|
||||
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
|
||||
uint32_t ItMode)
|
||||
{
|
||||
ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
|
||||
uint32_t descidx = dmatxdesclist->CurTxDesc;
|
||||
|
|
@ -3020,6 +3033,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
|
|||
|
||||
ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
|
||||
uint32_t bd_count = 0;
|
||||
uint32_t primask_bit;
|
||||
|
||||
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
|
||||
if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
|
||||
|
|
@ -3277,14 +3291,15 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
|
|||
dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
|
||||
|
||||
dmatxdesclist->CurTxDesc = descidx;
|
||||
/* disable the interrupt */
|
||||
__disable_irq();
|
||||
|
||||
/* Enter critical section */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__set_PRIMASK(1);
|
||||
|
||||
dmatxdesclist->BuffersInUse += bd_count + 1U;
|
||||
|
||||
/* Enable interrupts back */
|
||||
__enable_irq();
|
||||
|
||||
/* Exit critical section: restore previous priority mask */
|
||||
__set_PRIMASK(primask_bit);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_ETH_ERROR_NONE;
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
||||
|
|
@ -160,7 +159,7 @@ typedef struct
|
|||
|
||||
void *pData; /*!< Specifies Application packet pointer to save */
|
||||
|
||||
} ETH_TxPacketConfig;
|
||||
} ETH_TxPacketConfigTypeDef;
|
||||
/**
|
||||
*
|
||||
*/
|
||||
|
|
@ -792,7 +791,6 @@ typedef struct
|
|||
#define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */
|
||||
#define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */
|
||||
|
||||
|
||||
/*
|
||||
DMA Tx Context Descriptor
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
|
@ -843,7 +841,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -942,7 +939,6 @@ typedef struct
|
|||
#define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */
|
||||
#define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Bit definition of Rx normal descriptor register 3 write back format
|
||||
*/
|
||||
|
|
@ -1487,11 +1483,12 @@ typedef struct
|
|||
/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */
|
||||
#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */
|
||||
#define HAL_ETH_PTP_NOT_CONFIGURED 0x00000000U /*!< ETH PTP Configuration not done */
|
||||
#define HAL_ETH_PTP_CONFIGURED 0x00000001U /*!< ETH PTP Configuration done */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1632,7 +1629,6 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->RPR2 = (__EXTI_LINE__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief enable rising edge interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
|
||||
|
|
@ -1719,7 +1715,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
|
|||
HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
|
||||
HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
|
||||
HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
|
||||
HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
|
||||
HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
|
||||
|
|
@ -1738,8 +1734,8 @@ HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_tx
|
|||
HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
|
||||
#endif /* HAL_ETH_USE_PTP */
|
||||
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
|
||||
uint32_t RegValue);
|
||||
|
|
@ -1766,8 +1762,8 @@ void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *ti
|
|||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/* MAC & DMA Configuration APIs **********************************************/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
|
||||
HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
|
||||
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
|
||||
|
|
@ -1777,7 +1773,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t
|
|||
uint32_t VLANIdentifier);
|
||||
|
||||
/* MAC L2 Packet Filtering APIs **********************************************/
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
|
||||
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
|
||||
|
|
|
|||
|
|
@ -56,6 +56,9 @@
|
|||
|
||||
#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
|
||||
ETH_MACVIR_VLP | ETH_MACVIR_VLC)
|
||||
|
||||
#define ETH_MAC_L4_SRSP_MASK 0x0000FFFFU
|
||||
#define ETH_MAC_L4_DSTP_MASK 0xFFFF0000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -133,25 +136,34 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
{
|
||||
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
|
||||
|
||||
if (pL4FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write configuration to (MACL3L4C0R + filter )register */
|
||||
MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
if (Filter == ETH_L4_FILTER_0)
|
||||
{
|
||||
/* Write configuration to MACL3L4C0R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
|
||||
configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
|
||||
/* Write configuration to MACL4A0R register */
|
||||
WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
|
||||
|
||||
/* Write configuration to (MACL4A0R + filter )register */
|
||||
MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort |
|
||||
(pL4FilterConfig->DestinationPort << 16)));
|
||||
}
|
||||
else /* Filter == ETH_L4_FILTER_1 */
|
||||
{
|
||||
/* Write configuration to MACL3L4C1R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
|
||||
pL4FilterConfig->SrcPortFilterMatch |
|
||||
pL4FilterConfig->DestPortFilterMatch));
|
||||
|
||||
/* Write configuration to MACL4A1R register */
|
||||
WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
|
||||
}
|
||||
|
||||
/* Enable L4 filter */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
|
|
@ -172,7 +184,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
* that contains L4 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig)
|
||||
{
|
||||
if (pL4FilterConfig == NULL)
|
||||
|
|
@ -180,18 +192,32 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get configuration to (MACL3L4C0R + filter )register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
if (Filter == ETH_L4_FILTER_0)
|
||||
{
|
||||
/* Get configuration from MACL3L4C0R register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
|
||||
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
|
||||
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
|
||||
/* Get configuration to (MACL3L4C0R + filter )register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)),
|
||||
ETH_MACL4AR_L4DP) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
|
||||
/* Get configuration from MACL4A0R register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
|
||||
}
|
||||
else /* Filter == ETH_L4_FILTER_1 */
|
||||
{
|
||||
/* Get configuration from MACL3L4C1R register */
|
||||
pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN);
|
||||
pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
|
||||
(ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
|
||||
pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
|
||||
(ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
|
||||
|
||||
/* Get configuration from MACL4A1R register */
|
||||
pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
|
||||
pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -210,43 +236,83 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
{
|
||||
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
|
||||
|
||||
if (pL3FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Write configuration to (MACL3L4C0R + filter )register */
|
||||
MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
if (Filter == ETH_L3_FILTER_0)
|
||||
{
|
||||
/* Write configuration to MACL3L4C0R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
}
|
||||
else /* Filter == ETH_L3_FILTER_1 */
|
||||
{
|
||||
/* Write configuration to MACL3L4C1R register */
|
||||
MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
|
||||
pL3FilterConfig->SrcAddrFilterMatch |
|
||||
pL3FilterConfig->DestAddrFilterMatch |
|
||||
(pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
|
||||
(pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
|
||||
}
|
||||
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
if (Filter == ETH_L3_FILTER_0)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
|
||||
/* Set the IPv4 destination address match */
|
||||
WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
|
||||
}
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
else /* Filter == ETH_L3_FILTER_1 */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
|
||||
/* Set the IPv4 destination address match */
|
||||
*((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
|
||||
/* Check if IPv6 protocol is selected */
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
/* Set the IPv6 address match */
|
||||
/* Set Bits[31:0] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]);
|
||||
/* Set Bits[63:32] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]);
|
||||
/* update Bits[95:64] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]);
|
||||
/* update Bits[127:96] of 128-bit IP addr */
|
||||
WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]);
|
||||
}
|
||||
else /* IPv4 protocol is selected */
|
||||
{
|
||||
/* Set the IPv4 source address match */
|
||||
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr);
|
||||
/* Set the IPv4 destination address match */
|
||||
WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable L3 filter */
|
||||
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -263,14 +329,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
* that will contain the L3 filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig)
|
||||
{
|
||||
if (pL3FilterConfig == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
ETH_MACL3L4CR_L3PEN);
|
||||
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
|
|
@ -282,17 +347,35 @@ HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
|
|||
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
|
||||
ETH_MACL3L4CR_L3HDBM) >> 11);
|
||||
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
if (Filter == ETH_L3_FILTER_0)
|
||||
{
|
||||
pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
|
||||
pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
|
||||
WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
|
||||
}
|
||||
}
|
||||
else
|
||||
else /* ETH_L3_FILTER_1 */
|
||||
{
|
||||
pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
|
||||
pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
|
||||
if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R);
|
||||
WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R);
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -330,7 +413,7 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
|
|||
* that will contain the VLAN filter configuration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if (pVlanConfig == NULL)
|
||||
{
|
||||
|
|
@ -340,12 +423,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
|
|||
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
|
||||
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
|
||||
ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
|
||||
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
|
||||
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
|
||||
(ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
|
||||
|
|
@ -407,7 +492,7 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
|
|||
* that will contain the Tx VLAN filter configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if (pVlanConfig == NULL)
|
||||
|
|
@ -443,7 +528,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
|
|||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
const ETH_TxVLANConfigTypeDef *pVlanConfig)
|
||||
{
|
||||
if (VLANTag == ETH_INNER_TX_VLANTAG)
|
||||
{
|
||||
|
|
@ -544,7 +629,6 @@ void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
|
|||
__HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns the ETH MAC LPI event
|
||||
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
|
||||
|
|
|
|||
|
|
@ -314,25 +314,25 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t
|
|||
/* MAC L3 L4 Filtering APIs ***************************************************/
|
||||
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
|
||||
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
|
||||
|
||||
/* MAC VLAN Processing APIs ************************************************/
|
||||
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
|
||||
ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
const ETH_TxVLANConfigTypeDef *pVlanConfig);
|
||||
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
|
||||
|
||||
/* Energy Efficient Ethernet APIs *********************************************/
|
||||
|
|
@ -364,5 +364,3 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_ETH_EX_H */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -105,49 +105,91 @@ typedef struct
|
|||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U)
|
||||
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U)
|
||||
#if defined(EXTI_IMR1_IM18)
|
||||
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U)
|
||||
#endif /* EXTI_IMR1_IM18 */
|
||||
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U)
|
||||
#if defined(EXTI_IMR1_IM20)
|
||||
#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U)
|
||||
#endif /* EXTI_IMR1_IM20 */
|
||||
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15U)
|
||||
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16U)
|
||||
#if defined(EXTI_IMR1_IM23)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17U)
|
||||
#endif /* EXTI_IMR1_IM23 */
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18U)
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19U)
|
||||
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1AU)
|
||||
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1BU)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1CU)
|
||||
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1DU)
|
||||
#if defined(EXTI_IMR1_IM30)
|
||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1EU)
|
||||
#endif /* EXTI_IMR1_IM30 */
|
||||
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1FU)
|
||||
#if defined(EXTI_IMR2_IM32)
|
||||
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00U)
|
||||
#endif /* EXTI_IMR2_IM32 */
|
||||
#if defined(EXTI_IMR2_IM33)
|
||||
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01U)
|
||||
#endif /* EXTI_IMR2_IM33 */
|
||||
#if defined(EXTI_IMR2_IM34)
|
||||
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02U)
|
||||
#endif /* EXTI_IMR2_IM34 */
|
||||
#if defined(EXTI_IMR2_IM35)
|
||||
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03U)
|
||||
#endif /* EXTI_IMR2_IM35 */
|
||||
#if defined(EXTI_IMR2_IM36)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04U)
|
||||
#endif /* EXTI_IMR2_IM36 */
|
||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05U)
|
||||
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06U)
|
||||
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07U)
|
||||
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08U)
|
||||
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09U)
|
||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0AU)
|
||||
#if defined(EXTI_IMR2_IM43)
|
||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0BU)
|
||||
#endif /* EXTI_IMR2_IM43 */
|
||||
#if defined(EXTI_IMR2_IM44)
|
||||
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0CU)
|
||||
#endif /* EXTI_IMR2_IM44 */
|
||||
#if defined(EXTI_IMR2_IM45)
|
||||
#endif /* EXTI_IMR2_IM45 */
|
||||
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0DU)
|
||||
#if defined(ETH)
|
||||
#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | 0x0EU)
|
||||
#endif /* ETH */
|
||||
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0FU)
|
||||
#if defined(EXTI_IMR2_IM48)
|
||||
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10U)
|
||||
#endif /* EXTI_IMR2_IM48 */
|
||||
#define EXTI_LINE_49 (EXTI_DIRECT | EXTI_REG2 | 0x11U)
|
||||
#define EXTI_LINE_50 (EXTI_CONFIG | EXTI_REG2 | 0x12U)
|
||||
#if defined(EXTI_IMR2_IM51)
|
||||
#define EXTI_LINE_51 (EXTI_DIRECT | EXTI_REG2 | 0x13U)
|
||||
#endif /* EXTI_IMR2_IM51 */
|
||||
#if defined(EXTI_IMR2_IM52)
|
||||
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14U)
|
||||
#endif /* EXTI_IMR2_IM52 */
|
||||
#define EXTI_LINE_53 (EXTI_CONFIG | EXTI_REG2 | 0x15U)
|
||||
#if defined(EXTI_IMR2_IM54)
|
||||
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16U)
|
||||
#endif /* EXTI_IMR2_IM54 */
|
||||
#if defined(EXTI_IMR2_IM55)
|
||||
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17U)
|
||||
#endif /* EXTI_IMR2_IM55 */
|
||||
#if defined(EXTI_IMR2_IM56)
|
||||
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18U)
|
||||
#endif /* EXTI_IMR2_IM56 */
|
||||
#if defined(EXTI_IMR2_IM57)
|
||||
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19U)
|
||||
|
||||
#endif /* EXTI_IMR2_IM57 */
|
||||
#if defined(EXTI_IMR2_IM58)
|
||||
#if defined(I3C2)
|
||||
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1AU)
|
||||
#endif /* I3C2 */
|
||||
#endif /* EXTI_IMR2_IM58 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -181,11 +223,19 @@ typedef struct
|
|||
#define EXTI_GPIOB 0x00000001U
|
||||
#define EXTI_GPIOC 0x00000002U
|
||||
#define EXTI_GPIOD 0x00000003U
|
||||
#if defined(GPIOE)
|
||||
#define EXTI_GPIOE 0x00000004U
|
||||
#endif /* GPIOE */
|
||||
#if defined(GPIOF)
|
||||
#define EXTI_GPIOF 0x00000005U
|
||||
#endif /* GPIOF */
|
||||
#if defined(GPIOG)
|
||||
#define EXTI_GPIOG 0x00000006U
|
||||
#endif /* GPIOG */
|
||||
#define EXTI_GPIOH 0x00000007U
|
||||
#if defined(GPIOI)
|
||||
#define EXTI_GPIOI 0x00000008U
|
||||
#endif /* GPIOI */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -271,7 +321,13 @@ typedef struct
|
|||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#if defined(EXTI_IMR2_IM58)
|
||||
#define EXTI_LINE_NB 59U
|
||||
#elif defined(EXTI_IMR2_IM57)
|
||||
#define EXTI_LINE_NB 58U
|
||||
#else
|
||||
#define EXTI_LINE_NB 54U
|
||||
#endif /* EXTI_IMR2_IM58 */
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for secure & privilege attributes
|
||||
|
|
@ -304,6 +360,7 @@ typedef struct
|
|||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
|
||||
|
||||
#if defined(GPIOI)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
|
|
@ -313,6 +370,22 @@ typedef struct
|
|||
((__PORT__) == EXTI_GPIOG) || \
|
||||
((__PORT__) == EXTI_GPIOH) || \
|
||||
((__PORT__) == EXTI_GPIOI))
|
||||
#elif defined(GPIOE)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG) || \
|
||||
((__PORT__) == EXTI_GPIOH))
|
||||
#else
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOH))
|
||||
#endif /* GPIOI */
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
|
||||
|
||||
|
|
|
|||
|
|
@ -253,7 +253,7 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24,
|
|||
* @{
|
||||
*/
|
||||
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
|
||||
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData, uint32_t BufferIndex);
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -3474,7 +3474,7 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
|
|||
* @param BufferIndex index of the buffer to be configured.
|
||||
* @retval none
|
||||
*/
|
||||
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData, uint32_t BufferIndex)
|
||||
{
|
||||
uint32_t TxElementW1;
|
||||
|
|
|
|||
|
|
@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan,
|
|||
#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
|
||||
#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
|
||||
#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
|
||||
#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */
|
||||
#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
|
||||
#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
|
||||
#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
|
||||
|
|
|
|||
|
|
@ -362,6 +362,7 @@ void HAL_FLASH_IRQHandler(void)
|
|||
__IO uint32_t *reg_cr;
|
||||
__IO uint32_t *reg_ccr;
|
||||
const __IO uint32_t *reg_sr;
|
||||
const __IO uint32_t *reg_ecccorr;
|
||||
|
||||
/* Access to CR, CCR and SR registers depends on operation type */
|
||||
#if defined (FLASH_OPTSR2_TZEN)
|
||||
|
|
@ -373,6 +374,7 @@ void HAL_FLASH_IRQHandler(void)
|
|||
reg_ccr = &(FLASH_NS->NSCCR);
|
||||
reg_sr = &(FLASH_NS->NSSR);
|
||||
#endif /* FLASH_OPTSR2_TZEN */
|
||||
reg_ecccorr = &(FLASH->ECCCORR);
|
||||
|
||||
/* Save Flash errors */
|
||||
errorflag = (*reg_sr) & FLASH_FLAG_SR_ERRORS;
|
||||
|
|
@ -460,6 +462,16 @@ void HAL_FLASH_IRQHandler(void)
|
|||
HAL_FLASH_EndOfOperationCallback(param);
|
||||
}
|
||||
|
||||
/* Check FLASH ECC correction flag */
|
||||
if ((*reg_ecccorr & FLASH_ECCR_ECCC) != 0U)
|
||||
{
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccCorrectionCallback();
|
||||
|
||||
/* Clear ECC correction flag in order to allow new ECC error record */
|
||||
FLASH->ECCCORR |= FLASH_ECCR_ECCC;
|
||||
}
|
||||
|
||||
if (pFlash.ProcedureOnGoing == 0U)
|
||||
{
|
||||
/* Disable Flash Operation and Error source interrupt */
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ typedef struct
|
|||
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
|
||||
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
|
||||
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
|
||||
#if (FLASH_SECTOR_NB == 128)
|
||||
#if (FLASH_SECTOR_NB >= 32)
|
||||
#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
|
||||
#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
|
||||
#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
|
||||
|
|
@ -276,6 +276,8 @@ typedef struct
|
|||
#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */
|
||||
#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */
|
||||
#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */
|
||||
#endif /* (FLASH_SECTOR_NB >= 32) */
|
||||
#if (FLASH_SECTOR_NB >= 128)
|
||||
#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */
|
||||
#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */
|
||||
#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */
|
||||
|
|
@ -372,7 +374,7 @@ typedef struct
|
|||
#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */
|
||||
#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */
|
||||
#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */
|
||||
#endif /* (FLASH_SECTOR_NB == 128) */
|
||||
#endif /* (FLASH_SECTOR_NB >= 128) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1380,6 +1380,18 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig1, uint32_
|
|||
}
|
||||
#endif /* FLASH_OPTSR2_SRAM1_ECC */
|
||||
|
||||
#if defined (FLASH_OPTSR2_USBPD_DIS)
|
||||
if ((UserType & OB_USER_USBPD_DIS) != 0U)
|
||||
{
|
||||
/* USBPD_DIS option byte should be modified */
|
||||
assert_param(IS_OB_USER_USBPD_DIS(UserConfig2 & FLASH_OPTSR2_USBPD_DIS));
|
||||
|
||||
/* Set value and mask for USBPD_DIS option byte */
|
||||
optr_reg2_val |= (UserConfig2 & FLASH_OPTSR2_USBPD_DIS);
|
||||
optr_reg2_mask |= FLASH_OPTSR2_USBPD_DIS;
|
||||
}
|
||||
#endif /* FLASH_OPTSR2_USBPD_DIS */
|
||||
|
||||
#if defined (FLASH_OPTSR2_TZEN)
|
||||
if ((UserType & OB_USER_TZEN) != 0U)
|
||||
{
|
||||
|
|
@ -1714,6 +1726,15 @@ static void FLASH_OB_GetHDP(uint32_t Bank, uint32_t *HDPStartSector, uint32_t *H
|
|||
*
|
||||
* @param EDATASize specifies the size (in sectors) of the Flash high-cycle data area
|
||||
* This parameter can be sectors number between 0 and 8
|
||||
* 0: Disable all EDATA sectors.
|
||||
* 1: The last sector is reserved for flash high-cycle data.
|
||||
* 2: The two last sectors are reserved for flash high-cycle data.
|
||||
* 3: The three last sectors are reserved for flash high-cycle data
|
||||
* 4: The four last sectors is reserved for flash high-cycle data.
|
||||
* 5: The five last sectors are reserved for flash high-cycle data.
|
||||
* 6: The six last sectors are reserved for flash high-cycle data.
|
||||
* 7: The seven last sectors are reserved for flash high-cycle data.
|
||||
* 8: The eight last sectors are reserved for flash high-cycle data.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -1743,13 +1764,13 @@ static void FLASH_OB_EDATAConfig(uint32_t Banks, uint32_t EDATASize)
|
|||
/* Write EDATA registers */
|
||||
if ((Banks & FLASH_BANK_1) == FLASH_BANK_1)
|
||||
{
|
||||
/* de-activate Flash high-cycle data for bank 1 */
|
||||
/* Disable Flash high-cycle data for bank 1 */
|
||||
FLASH->EDATA1R_PRG = 0U;
|
||||
}
|
||||
|
||||
if ((Banks & FLASH_BANK_2) == FLASH_BANK_2)
|
||||
{
|
||||
/* de-activate Flash high-cycle data for bank 2 */
|
||||
/* Disable Flash high-cycle data for bank 2 */
|
||||
FLASH->EDATA2R_PRG = 0U;
|
||||
}
|
||||
}
|
||||
|
|
@ -1783,7 +1804,17 @@ static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize)
|
|||
}
|
||||
|
||||
/* Get configuration of secure area */
|
||||
*EDATASize = (regvalue & FLASH_EDATAR_EDATA_STRT);
|
||||
if ((regvalue & FLASH_EDATAR_EDATA_EN) != 0U)
|
||||
{
|
||||
/* Encoding of Edata Area size is register value + 1 */
|
||||
*EDATASize = (regvalue & FLASH_EDATAR_EDATA_STRT) + 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No defined Edata area */
|
||||
*EDATASize = 0U;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
|
||||
|
|
@ -1791,6 +1822,193 @@ static void FLASH_OB_GetEDATA(uint32_t Bank, uint32_t *EDATASize)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions
|
||||
* @brief Extended ECC operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended ECC operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the Extended FLASH
|
||||
ECC Operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable ECC correction interrupt
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_ECCC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_ECCC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the ECC error information.
|
||||
* @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
|
||||
* ECC error information.
|
||||
* @note This function should be called before ECC bit is cleared
|
||||
* (in callback function)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
|
||||
{
|
||||
uint32_t correction_reg = FLASH->ECCCORR;
|
||||
uint32_t detection_reg = FLASH->ECCDETR;
|
||||
uint32_t data_reg = FLASH->ECCDR;
|
||||
uint32_t addr_reg = 0xFFFFFFFFU;
|
||||
|
||||
/* Check if the operation is a correction or a detection*/
|
||||
if ((correction_reg & FLASH_ECCR_ECCC) != 0U)
|
||||
{
|
||||
/* Get area and offset address values from ECCCORR register*/
|
||||
pData->Area = correction_reg & (~(FLASH_ECCR_ECCIE | FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCC));
|
||||
addr_reg = (correction_reg & FLASH_ECCR_ADDR_ECC);
|
||||
}
|
||||
else if ((detection_reg & FLASH_ECCR_ECCD) != 0U)
|
||||
{
|
||||
/* Get area and offset address values from ECCDETR register */
|
||||
pData->Area = detection_reg & (~(FLASH_ECCR_ADDR_ECC | FLASH_ECCR_ECCD));
|
||||
addr_reg = (detection_reg & FLASH_ECCR_ADDR_ECC);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
/* Check that an ECC single or double error has occurred to continue the calculation of area address */
|
||||
if (addr_reg != 0xFFFFFFFFU)
|
||||
{
|
||||
/* Get address value according to area value*/
|
||||
switch (pData->Area)
|
||||
{
|
||||
case FLASH_ECC_AREA_USER_BANK1:
|
||||
/*
|
||||
* One error detection/correction or two error detections per 128-bit flash word
|
||||
* Therefore, the address returned by ECC registers in bank1 represents 128-bit flash word,
|
||||
* to get the correct address value, we must do a shift by 4 bits
|
||||
*/
|
||||
addr_reg = addr_reg << 4U;
|
||||
pData->Address = FLASH_BASE + addr_reg;
|
||||
break;
|
||||
case FLASH_ECC_AREA_USER_BANK2:
|
||||
/*
|
||||
* One error detection/correction or two error detections per 128-bit flash word
|
||||
* Therefore, the address returned by ECC registers in bank2 represents 128-bit flash word,
|
||||
* to get the correct address value, we must do a shift by 4 bits
|
||||
*/
|
||||
addr_reg = addr_reg << 4U;
|
||||
pData->Address = FLASH_BASE + FLASH_BANK_SIZE + addr_reg;
|
||||
break;
|
||||
case FLASH_ECC_AREA_SYSTEM:
|
||||
/* check system flash bank */
|
||||
if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC)
|
||||
{
|
||||
pData->Address = FLASH_SYSTEM_BASE + FLASH_SYSTEM_SIZE + addr_reg;
|
||||
}
|
||||
else
|
||||
{
|
||||
pData->Address = FLASH_SYSTEM_BASE + addr_reg;
|
||||
}
|
||||
break;
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
case FLASH_ECC_AREA_OBK:
|
||||
pData->Address = FLASH_OBK_BASE + addr_reg;
|
||||
break;
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
case FLASH_ECC_AREA_EDATA:
|
||||
/* check flash high-cycle data bank */
|
||||
if ((correction_reg & FLASH_ECCR_BK_ECC) == FLASH_ECCR_BK_ECC)
|
||||
{
|
||||
/*
|
||||
* addr_reg is the address returned by the ECC register along with an offset value depends on area
|
||||
* To calculate the exact address set by user while an ECC occurred, we must subtract the offset value,
|
||||
* In addition, the address returned by ECC registers represents 128-bit flash word (multiply by 4),
|
||||
*/
|
||||
pData->Address = FLASH_EDATA_BASE + FLASH_BANK_SIZE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pData->Address = FLASH_EDATA_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_EDATA) * 4U);
|
||||
}
|
||||
break;
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
case FLASH_ECC_AREA_OTP:
|
||||
/* Address returned by the ECC is an halfword, multiply by 4 to get the exact address*/
|
||||
pData->Address = FLASH_OTP_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_OTP) * 4U);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Do nothing */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pData->Data = data_reg & FLASH_ECCR_ADDR_ECC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle Flash ECC Detection interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_ECCD_IRQHandler(void)
|
||||
{
|
||||
/* Check if the ECC double error occurred*/
|
||||
if (READ_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD) != 0U)
|
||||
{
|
||||
/* FLASH ECC detection user callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear ECCD flag
|
||||
note : this step will clear all the information related to the flash ecc detection
|
||||
*/
|
||||
SET_BIT(FLASH->ECCDETR, FLASH_ECCR_ECCD);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC Correction interrupt callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC Detection interrupt callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ typedef struct
|
|||
@ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC,
|
||||
@ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC,
|
||||
@ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC,
|
||||
@ref FLASH_OB_USER_TZEN */
|
||||
@ref FLASH_OB_USER_USBPD_DIS, @ref FLASH_OB_USER_TZEN */
|
||||
|
||||
uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration.
|
||||
This parameter must be a value of @ref FLASH_Banks */
|
||||
|
|
@ -171,6 +171,19 @@ typedef struct
|
|||
This parameter can be a value between 1 and max number of sectors in the bank */
|
||||
} FLASH_HDPExtensionTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ECC Info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Area; /*!< Area from which an ECC was detected.
|
||||
This parameter can be a value of @ref FLASHEx_ECC_Area */
|
||||
|
||||
uint32_t Address; /*!< ECC error address */
|
||||
|
||||
uint32_t Data; /*!< ECC failing data */
|
||||
} FLASH_EccInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -206,6 +219,25 @@ typedef struct
|
|||
activation */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
/** @defgroup FLASH_ECC_Area FLASH ECC Area
|
||||
* @brief FLASH ECC Area
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
|
||||
#define FLASH_ECC_AREA_USER_BANK2 FLASH_ECCR_BK_ECC /*!< FLASH bank 2 area */
|
||||
#define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */
|
||||
#if defined (FLASH_SR_OBKERR)
|
||||
#define FLASH_ECC_AREA_OBK FLASH_ECCR_OBK_ECC /*!< FLASH OBK area */
|
||||
#endif /* FLASH_SR_OBKERR */
|
||||
#define FLASH_ECC_AREA_OTP FLASH_ECCR_OTP_ECC /*!< FLASH OTP area */
|
||||
#if defined (FLASH_EDATAR_EDATA_EN)
|
||||
#define FLASH_ECC_AREA_EDATA FLASH_ECCR_DATA_ECC /*!< FLASH high-cycle data area */
|
||||
#endif /* FLASH_EDATAR_EDATA_EN */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -276,24 +308,28 @@ byte configuration */
|
|||
#define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */
|
||||
#define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */
|
||||
#define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */
|
||||
#if defined (FLASH_OPTSR2_USBPD_DIS)
|
||||
#define OB_USER_USBPD_DIS 0x00040000U /*!< USB power delivery configuration enable */
|
||||
#endif /*FLASH_OPTSR2_USBPD_DIS*/
|
||||
#if defined (FLASH_OPTSR2_TZEN)
|
||||
#define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */
|
||||
#endif /* FLASH_OPTSR2_TZEN */
|
||||
|
||||
#if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE)
|
||||
#if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) && defined (FLASH_OPTSR2_USBPD_DIS)
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\
|
||||
OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\
|
||||
OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\
|
||||
OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\
|
||||
OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\
|
||||
OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_TZEN)
|
||||
OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_USBPD_DIS |\
|
||||
OB_USER_TZEN)
|
||||
#else
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\
|
||||
OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\
|
||||
OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\
|
||||
OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\
|
||||
OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\
|
||||
OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC)
|
||||
OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC)
|
||||
#endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -302,9 +338,9 @@ byte configuration */
|
|||
/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL_1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 1 threshold */
|
||||
#define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 2 threshold */
|
||||
#define OB_BOR_LEVEL_3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level 3 threshold */
|
||||
#define OB_BOR_LEVEL_1 0U /*!< Reset level 1 threshold */
|
||||
#define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 2 threshold */
|
||||
#define OB_BOR_LEVEL_3 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 3 threshold */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -500,6 +536,16 @@ byte configuration */
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OB_USER_USBPD_DIS FLASH Option Bytes USB power delivery configuration
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTSR2_USBPD_DIS)
|
||||
#define OB_USBPD_DIS_ENABLE 0x00000000U /*!< USB power delivery check enable */
|
||||
#define OB_USBPD_DIS_DISABLE FLASH_OPTSR2_USBPD_DIS /*!< USB power delivery check disable */
|
||||
#endif /* FLASH_OPTSR2_USBPD_DIS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -558,6 +604,16 @@ byte configuration */
|
|||
#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */
|
||||
#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */
|
||||
#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */
|
||||
#elif (FLASH_SECTOR_NB == 32)
|
||||
#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */
|
||||
#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */
|
||||
#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */
|
||||
#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */
|
||||
#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */
|
||||
#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */
|
||||
#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */
|
||||
#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */
|
||||
#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */
|
||||
#else
|
||||
#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
|
||||
|
|
@ -576,13 +632,12 @@ byte configuration */
|
|||
/** @defgroup FLASH_Programming_Delay FLASH Programming Delay
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or
|
||||
#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 84 MHz or
|
||||
below */
|
||||
#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz
|
||||
and 185 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz
|
||||
and 225 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */
|
||||
#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 84 MHz
|
||||
and 168 MHz */
|
||||
#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 168 MHz
|
||||
and 250 MHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -835,6 +890,19 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef
|
|||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
|
||||
void HAL_FLASHEx_ECCD_IRQHandler(void);
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void);
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -845,6 +913,8 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef
|
|||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */
|
||||
#define FLASH_ADDRESS_OFFSET_OTP (0x00000600U) /*!< Flash address offset of OTP area */
|
||||
#define FLASH_ADDRESS_OFFSET_EDATA (0x0000F000U) /*!< Flash address offset of EDATA area */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -937,6 +1007,9 @@ HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(const FLASH_HDPExtensionTypeDef
|
|||
|
||||
#define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE))
|
||||
|
||||
#if defined(FLASH_OPTSR2_USBPD_DIS)
|
||||
#define IS_OB_USER_USBPD_DIS(VALUE) (((VALUE) == OB_USBPD_DIS_ENABLE) || ((VALUE) == OB_USBPD_DIS_DISABLE))
|
||||
#endif /* FLASH_OPTSR2_USBPD_DIS */
|
||||
#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE))
|
||||
|
||||
#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
|
||||
|
|
|
|||
|
|
@ -166,7 +166,7 @@
|
|||
|
||||
[..]
|
||||
Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
weak function.
|
||||
HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
|
|
@ -182,10 +182,10 @@
|
|||
|
||||
[..]
|
||||
By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
|
||||
all callbacks are set to the corresponding weak (surcharged) functions:
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples GetDataCallback(), OutputDataReadyCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init()
|
||||
reset to the legacy weak functions in the HAL_FMAC_Init()
|
||||
and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
|
@ -202,8 +202,7 @@
|
|||
[..]
|
||||
When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
|
||||
and weak callbacks are used.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
|
|
@ -229,7 +228,6 @@
|
|||
/** @defgroup FMAC_Private_Constants FMAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
|
||||
#define MAX_PRELOAD_INDEX 0xFFU
|
||||
#define PRELOAD_ACCESS_DMA 0x00U
|
||||
|
|
@ -322,7 +320,6 @@
|
|||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Global variables ----------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
|
||||
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
|
||||
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
|
||||
|
|
@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
|
|||
static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/* Functions Definition ------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -2576,7 +2572,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
|
|||
#else
|
||||
HAL_FMAC_ErrorCallback(hfmac);
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2708,11 +2703,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma)
|
|||
HAL_FMAC_ErrorCallback(hfmac);
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -243,10 +243,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -357,7 +354,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_variables FMAC Exported variables
|
||||
* @{
|
||||
|
|
@ -499,7 +495,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros-----------------------------------------------------------*/
|
||||
/* Private Macros-------------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -578,9 +574,9 @@ typedef struct
|
|||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
|
||||
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter R.
|
||||
|
|
|
|||
|
|
@ -206,15 +206,15 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
|
|||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
tmp = GPIOx->AFR[position >> 3U];
|
||||
tmp &= ~(0x0FUL << ((position & 0x07U) * 4U));
|
||||
tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U));
|
||||
tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
|
||||
tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
|
||||
GPIOx->AFR[position >> 3U] = tmp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
tmp = GPIOx->MODER;
|
||||
tmp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
||||
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
||||
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
|
||||
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
|
||||
GPIOx->MODER = tmp;
|
||||
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
|
|
@ -226,8 +226,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
|
|||
|
||||
/* Configure the IO Speed */
|
||||
tmp = GPIOx->OSPEEDR;
|
||||
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
||||
tmp |= (pGPIO_Init->Speed << (position * 2U));
|
||||
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
|
||||
tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
|
||||
GPIOx->OSPEEDR = tmp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
|
|
@ -244,8 +244,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
|
|||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
tmp = GPIOx->PUPDR;
|
||||
tmp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
tmp |= ((pGPIO_Init->Pull) << (position * 2U));
|
||||
tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
|
||||
tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
|
||||
GPIOx->PUPDR = tmp;
|
||||
}
|
||||
|
||||
|
|
@ -254,8 +254,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
|
|||
if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
tmp = EXTI->EXTICR[position >> 2U];
|
||||
tmp &= ~((0x0FUL) << (8U * (position & 0x03U)));
|
||||
tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
|
||||
tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
||||
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
||||
EXTI->EXTICR[position >> 2U] = tmp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
|
|
@ -327,8 +327,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
tmp = EXTI->EXTICR[position >> 2U];
|
||||
tmp &= ((0x0FUL) << (8U * (position & 0x03U)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))
|
||||
tmp &= ((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR1 &= ~(iocurrent);
|
||||
|
|
@ -338,25 +338,25 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
EXTI->RTSR1 &= ~(iocurrent);
|
||||
EXTI->FTSR1 &= ~(iocurrent);
|
||||
|
||||
tmp = (0x0FUL) << (8U * (position & 0x03U));
|
||||
tmp = (0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos);
|
||||
EXTI->EXTICR[position >> 2U] &= ~tmp;
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO in Analog Mode */
|
||||
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
|
||||
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * 4U));
|
||||
GPIOx->AFR[position >> 3U] &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position);
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
|
||||
}
|
||||
|
||||
position++;
|
||||
|
|
@ -704,7 +704,7 @@ HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uin
|
|||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_ALL));
|
||||
assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin));
|
||||
|
||||
/* Get secure attribute of the port pin */
|
||||
while ((GPIO_Pin >> position) != 0U)
|
||||
|
|
|
|||
|
|
@ -278,6 +278,23 @@ typedef enum
|
|||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\
|
||||
((__PIN__) == GPIO_PIN_1) ||\
|
||||
((__PIN__) == GPIO_PIN_2) ||\
|
||||
((__PIN__) == GPIO_PIN_3) ||\
|
||||
((__PIN__) == GPIO_PIN_4) ||\
|
||||
((__PIN__) == GPIO_PIN_5) ||\
|
||||
((__PIN__) == GPIO_PIN_6) ||\
|
||||
((__PIN__) == GPIO_PIN_7) ||\
|
||||
((__PIN__) == GPIO_PIN_8) ||\
|
||||
((__PIN__) == GPIO_PIN_9) ||\
|
||||
((__PIN__) == GPIO_PIN_10) ||\
|
||||
((__PIN__) == GPIO_PIN_11) ||\
|
||||
((__PIN__) == GPIO_PIN_12) ||\
|
||||
((__PIN__) == GPIO_PIN_13) ||\
|
||||
((__PIN__) == GPIO_PIN_14) ||\
|
||||
((__PIN__) == GPIO_PIN_15))
|
||||
|
||||
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
|
||||
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
|
||||
|
||||
|
|
|
|||
|
|
@ -56,6 +56,12 @@ extern "C" {
|
|||
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
|
||||
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
|
||||
#if defined(DMA2D)
|
||||
#define GPIO_AF0_DMA2D ((uint8_t)0x00) /* DMA2D Alternate Function mapping */
|
||||
#endif /* DMA2D */
|
||||
#if defined(GFXTIM)
|
||||
#define GPIO_AF0_GFXTIM ((uint8_t)0x00) /* GFXTIM Alternate Function mapping */
|
||||
#endif /* GFXTIM */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
|
|
@ -68,9 +74,12 @@ extern "C" {
|
|||
#if defined(TIM17)
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#endif /* TIM17 */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#if !defined(STM32H503xx)
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(ADF1)
|
||||
#define GPIO_AF1_ADF1 ((uint8_t)0x01) /* ADF1 Alternate Function mapping */
|
||||
#endif /* ADF1 */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
|
|
@ -91,12 +100,20 @@ extern "C" {
|
|||
#if defined(TIM5)
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#endif /* TIM5 */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(TIM12)
|
||||
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
|
||||
#endif /* TIM12 */
|
||||
#if defined(TIM15)
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#endif /* TIM15 */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
|
|
@ -112,12 +129,22 @@ extern "C" {
|
|||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#if !defined(STM32H503xx)
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(TIM8)
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#endif /* TIM8 */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF3_COMP1 ((uint8_t)0x03) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF3_COMP2 ((uint8_t)0x03) /* COMP2 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
#if defined(ADF1)
|
||||
#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */
|
||||
#endif /* ADF1 */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
|
|
@ -125,10 +152,14 @@ extern "C" {
|
|||
#if defined(CEC)
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#endif /* CEC */
|
||||
#if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx)
|
||||
#if defined(DCMI)
|
||||
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
|
||||
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
|
||||
#endif /* DCMI */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
#if defined(PSSI)
|
||||
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
|
||||
#endif /* PSSI */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#if defined(I2C3)
|
||||
|
|
@ -140,6 +171,9 @@ extern "C" {
|
|||
#define GPIO_AF4_LPTIM1 ((uint8_t)0x04) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF4_SPI3 ((uint8_t)0x04) /* SPI3 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(TIM15)
|
||||
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
|
||||
#endif /* TIM15 */
|
||||
|
|
@ -147,6 +181,15 @@ extern "C" {
|
|||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF4_SAI1 ((uint8_t)0x04) /* SAI1 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
#if defined(MDF1)
|
||||
#define GPIO_AF4_MDF1 ((uint8_t)0x04) /* MDF1 Alternate Function mapping */
|
||||
#endif /* MDF1 */
|
||||
#if defined(ADF1)
|
||||
#define GPIO_AF4_ADF1 ((uint8_t)0x04) /* ADF1 Alternate Function mapping */
|
||||
#endif /* ADF1 */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
|
|
@ -154,10 +197,10 @@ extern "C" {
|
|||
#if defined(CEC)
|
||||
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
|
||||
#endif /* CEC */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#if !defined(STM32H503xx)
|
||||
#define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#endif /* STM32H503xx */
|
||||
#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
|
||||
|
|
@ -170,6 +213,14 @@ extern "C" {
|
|||
#if defined(SPI6)
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
#endif /* SPI6 */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF5_I3C2 ((uint8_t)0x05) /* I3C2 Alternate Function mapping */
|
||||
#if defined(GFXTIM)
|
||||
#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */
|
||||
#endif /* GFXTIM */
|
||||
#define GPIO_AF5_AUDIOCLK ((uint8_t)0x05) /* AUDIOCLK Alternate Function mapping */
|
||||
#define GPIO_AF5_USART2 ((uint8_t)0x05) /* USART2 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
|
|
@ -183,10 +234,10 @@ extern "C" {
|
|||
#if defined(SAI1)
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#endif /* SAI1 */
|
||||
#if defined(STM32H503xx)
|
||||
#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#endif /* STM32H503xx || STM32H533xx || STM32H523xx */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
|
||||
#if defined(SPI4)
|
||||
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */
|
||||
|
|
@ -194,6 +245,9 @@ extern "C" {
|
|||
#if defined(UART4)
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
|
||||
#endif /* UART4 */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF6_USART6 ((uint8_t)0x06) /* USART6 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(UART12)
|
||||
#define GPIO_AF6_UART12 ((uint8_t)0x06) /* UART12 Alternate Function mapping */
|
||||
#endif /* UART12 */
|
||||
|
|
@ -203,6 +257,12 @@ extern "C" {
|
|||
#if defined(UCPD1)
|
||||
#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /* UCPD1 Alternate Function mapping */
|
||||
#endif /* UCPD1 */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF6_ETH ((uint8_t)0x06) /* ETH Alternate Function mapping */
|
||||
#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF6_USART12 ((uint8_t)0x06) /* USART12 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
|
|
@ -221,9 +281,11 @@ extern "C" {
|
|||
#if defined(UART8)
|
||||
#define GPIO_AF7_UART8 ((uint8_t)0x07) /* UART8 Alternate Function mapping */
|
||||
#endif /* UART8 */
|
||||
#if !defined(STM32H5F5xx) || !defined(STM32H5F4xx) || !defined(STM32H5E5xx) || !defined(STM32H5E4xx)
|
||||
#if defined(UART12)
|
||||
#define GPIO_AF7_UART12 ((uint8_t)0x07) /* UART12 Alternate Function mapping */
|
||||
#endif /* UART12 */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
|
|
@ -236,7 +298,9 @@ extern "C" {
|
|||
#if defined(USART11)
|
||||
#define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */
|
||||
#endif /* USART11 */
|
||||
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF7_ETH ((uint8_t)0x07) /* ETH Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
|
|
@ -264,6 +328,18 @@ extern "C" {
|
|||
#if defined(UART8)
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#endif /* UART8 */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF8_ETH ((uint8_t)0x08) /* ETH Alternate Function mapping */
|
||||
#define GPIO_AF8_FMC ((uint8_t)0x08) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF8_I3C2 ((uint8_t)0x08) /* I3C2 Alternate Function mapping */
|
||||
#define GPIO_AF8_OCTOSPI1 ((uint8_t)0x08) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
#if defined(OCTOSPI2)
|
||||
#define GPIO_AF8_OCTOSPI2 ((uint8_t)0x08) /* OCTOSPI2 Alternate Function mapping */
|
||||
#endif /* OCTOSPI2 */
|
||||
#if defined(MDF1)
|
||||
#define GPIO_AF8_MDF1 ((uint8_t)0x08) /* MDF1 Alternate Function mapping */
|
||||
#endif /* MDF1 */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
|
|
@ -291,6 +367,16 @@ extern "C" {
|
|||
#define GPIO_AF9_USART2 ((uint8_t)0x09) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF9_USART3 ((uint8_t)0x09) /* USART3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF9_I3C2 ((uint8_t)0x09) /* I3C2 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(OCTOSPI2)
|
||||
#define GPIO_AF9_OCTOSPI2 ((uint8_t)0x09) /* OCTOSPI2 Alternate Function mapping */
|
||||
#endif /* OCTOSPI2 */
|
||||
#if defined(FDCAN3)
|
||||
#define GPIO_AF9_FDCAN3 ((uint8_t)0x09) /* FDCAN3 Alternate Function mapping */
|
||||
#endif /* FDCAN3 */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
|
|
@ -298,9 +384,11 @@ extern "C" {
|
|||
#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
|
||||
#if defined(STM32H503xx)
|
||||
#define GPIO_AF10_I3C1 ((uint8_t)0x0A) /* I3C1 Alternate Function mapping */
|
||||
#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SPI3 ((uint8_t)0x0A) /* SPI3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx || STM32H533xx || STM32H523xx */
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
|
|
@ -310,13 +398,33 @@ extern "C" {
|
|||
#if defined(SAI2)
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
|
||||
#endif /* SAI2 */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF10_SDMMC1 ((uint8_t)0x0A) /* SDMMC1 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(SDMMC2)
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
|
||||
#endif /* SDMMC2 */
|
||||
#if defined(TIM8)
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
|
||||
#endif /* TIM8 */
|
||||
#if defined(USB_DRD_FS)
|
||||
#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
|
||||
#endif /* USB_DRD_FS */
|
||||
#if defined(LCD)
|
||||
#define GPIO_AF10_LCD ((uint8_t)0x0A) /* LCD Alternate Function mapping */
|
||||
#endif /* LCD */
|
||||
#if defined(ETH)
|
||||
#define GPIO_AF10_ETH ((uint8_t)0x0A) /* ETH Alternate Function mapping */
|
||||
#endif /* ETH */
|
||||
#if defined(OCTOSPI2)
|
||||
#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */
|
||||
#endif /* OCTOSPI2 */
|
||||
#if defined(USB_OTG_FS)
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* USB OTG FS Alternate Function mapping */
|
||||
#endif /* USB_OTG_FS */
|
||||
#if defined(USB_OTG_HS)
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* USB OTG HS Alternate Function mapping */
|
||||
#endif /* USB_OTG_HS */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
|
|
@ -330,6 +438,9 @@ extern "C" {
|
|||
#if defined(OCTOSPI1)
|
||||
#define GPIO_AF11_OCTOSPI1 ((uint8_t)0x0B) /* OCTOSPI1 Alternate Function mapping */
|
||||
#endif /* OCTOSPI1 */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /* SDMMC1 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(SDMMC2)
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
|
||||
#endif /* SDMMC2 */
|
||||
|
|
@ -348,6 +459,9 @@ extern "C" {
|
|||
#define GPIO_AF11_SPI2 ((uint8_t)0x0B) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF11_USART2 ((uint8_t)0x0B) /* USART2 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(LCD)
|
||||
#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */
|
||||
#endif /* LCD */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
|
|
@ -362,6 +476,9 @@ extern "C" {
|
|||
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_SPI1 ((uint8_t)0x0C) /* SPI1 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF12_ETH ((uint8_t)0x0C) /* ETH Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
|
|
@ -380,6 +497,12 @@ extern "C" {
|
|||
#define GPIO_AF13_USART2 ((uint8_t)0x0D) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF13_USART3 ((uint8_t)0x0D) /* USART3 Alternate Function mapping */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(STM32H5F5xx) || defined(STM32H5F4xx) || defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_AF13_LPTIM6 ((uint8_t)0x0D) /* LPTIM6 Alternate Function mapping */
|
||||
#endif /* STM32H5F5xx || STM32H5F4xx || STM32H5E5xx || STM32H5E4xx */
|
||||
#if defined(LCD)
|
||||
#define GPIO_AF13_LCD ((uint8_t)0x0D) /* LCD Alternate Function mapping */
|
||||
#endif /* LCD */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
|
|
@ -403,12 +526,22 @@ extern "C" {
|
|||
#if defined(LPTIM6)
|
||||
#define GPIO_AF14_LPTIM6 ((uint8_t)0x0E) /* LPTIM6 Alternate Function mapping */
|
||||
#endif /* LPTIM6 */
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
|
||||
#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx)
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
|
||||
#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */
|
||||
#if defined(UART5)
|
||||
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
|
||||
#endif /* UART5 */
|
||||
#if (defined(STM32H533xx) || defined(STM32H523xx))
|
||||
#define GPIO_AF14_USART6 ((uint8_t)0x0E) /* USART6 Alternate Function mapping */
|
||||
#endif /* STM32H533xx || STM32H523xx */
|
||||
#if defined(LCD)
|
||||
#define GPIO_AF14_LCD ((uint8_t)0x0E) /* LCD Alternate Function mapping */
|
||||
#endif /* LCD */
|
||||
#if defined(PLAY1)
|
||||
#define GPIO_AF14_PLAY1_IN ((uint8_t)0x0E) /* PLAY1_IN Alternate Function mapping */
|
||||
#define GPIO_AF14_PLAY1_OUT ((uint8_t)0x0E) /* PLAY1_OUT Alternate Function mapping */
|
||||
#endif /* PLAY1 */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
|
|
@ -438,11 +571,13 @@ extern "C" {
|
|||
|
||||
/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */
|
||||
|
||||
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H503xx))
|
||||
#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \
|
||||
defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \
|
||||
defined(STM32H5E5xx) || defined(STM32H5E4xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
|
||||
#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H503xx)) */
|
||||
|
||||
|
||||
#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \
|
||||
defined(STM32H523xx) || defined(STM32H503xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) || \
|
||||
defined(STM32H5E5xx) || defined(STM32H5E4xx)*/
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -134,33 +134,42 @@
|
|||
#define GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE 0x10000000U /* 256MB max size */
|
||||
#endif /* defined(FMC_SDRAM_BANK_2) */
|
||||
|
||||
/* Definitions for GTZC TZSC & TZIC ALL register values */
|
||||
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define TZSC1_SECCFGR1_ALL (0xFFFFFFFFUL)
|
||||
#define TZSC1_SECCFGR2_ALL (0xFF0FFF07UL)
|
||||
#define TZSC1_SECCFGR3_ALL (0x05FFFF03UL)
|
||||
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define TZSC1_PRIVCFGR1_ALL (0xFFFFFFFFUL)
|
||||
#define TZSC1_PRIVCFGR2_ALL (0xFF0FFF07UL)
|
||||
#define TZSC1_PRIVCFGR3_ALL (0x05FFFF03UL)
|
||||
/* Definitions for GTZC TZSC & TZIC Crypto peripherals */
|
||||
#if defined(STM32H573xx) || defined(STM32H533xx)
|
||||
#define GTZC_CRYP_CFG3_MSK 0x00190000U
|
||||
#define GTZC_CRYP_CFG4_MSK 0x00000010U
|
||||
#else
|
||||
#define TZSC1_PRIVCFGR1_ALL (0xC21E7E33UL)
|
||||
#define TZSC1_PRIVCFGR2_ALL (0x12080B19UL)
|
||||
#define TZSC1_PRIVCFGR3_ALL (0x04065106UL)
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
#define GTZC_CRYP_CFG3_MSK 0U
|
||||
#define GTZC_CRYP_CFG4_MSK 0U
|
||||
#endif /* defined(STM32H573xx) || defined(STM32H533xx) */
|
||||
|
||||
/* Definitions for GTZC TZSC & TZIC ALL register values */
|
||||
#if defined(STM32H573xx) || defined(STM32H563xx)
|
||||
#define GTZC_CFGR1_MSK 0xFFFFFFFFU
|
||||
#define GTZC_CFGR2_MSK 0xFF0FFF07U
|
||||
#define GTZC_CFGR3_MSK (0x05E6FF03U | GTZC_CRYP_CFG3_MSK)
|
||||
#define GTZC_CFGR4_MSK (0x3F1F0FDFU | GTZC_CRYP_CFG4_MSK)
|
||||
#elif defined(STM32H533xx) || defined(STM32H523xx)
|
||||
#define GTZC_CFGR1_MSK 0xC33FFE7FU
|
||||
#define GTZC_CFGR2_MSK 0x16089F07U
|
||||
#define GTZC_CFGR3_MSK (0x05A6F106U | GTZC_CRYP_CFG3_MSK)
|
||||
#define GTZC_CFGR4_MSK (0x3F1F0FDFU | GTZC_CRYP_CFG4_MSK)
|
||||
#elif defined(STM32H562xx)
|
||||
#define GTZC_CFGR1_MSK 0xFFFFFFFFU
|
||||
#define GTZC_CFGR2_MSK 0xFF0FFF05U
|
||||
#define GTZC_CFGR3_MSK 0x05A6FF03U
|
||||
#define GTZC_CFGR4_MSK 0x3F1F0FDFU
|
||||
#elif defined(STM32H503xx)
|
||||
#define GTZC_CFGR1_MSK 0xC21E7E33U
|
||||
#define GTZC_CFGR2_MSK 0x12080B19U
|
||||
#define GTZC_CFGR3_MSK 0x04065104U
|
||||
#define GTZC_CFGR4_MSK 0x00000000U
|
||||
#endif /* (STM32H533xx) || defined(STM32H523xx) */
|
||||
|
||||
#if defined (GTZC_TZIC1)
|
||||
#define TZIC1_IER1_ALL (0xFFFFFFFFUL)
|
||||
#define TZIC1_IER2_ALL (0xFF0FFF07UL)
|
||||
#define TZIC1_IER3_ALL (0x05FFFF03UL)
|
||||
#define TZIC1_IER4_ALL (0x3F3F0FFFUL)
|
||||
|
||||
#define TZIC1_FCR1_ALL (0xFFFFFFFFUL)
|
||||
#define TZIC1_FCR2_ALL (0xFF0FFF07UL)
|
||||
#define TZIC1_FCR3_ALL (0x05FFFF03UL)
|
||||
#define TZIC1_FCR4_ALL (0x3F3F0FFFUL)
|
||||
#define GTZC_SEC_PRIV_MSK (GTZC_TZSC_PERIPH_PRIV | GTZC_TZSC_PERIPH_SEC)
|
||||
#else
|
||||
#define GTZC_SEC_PRIV_MSK GTZC_TZSC_PERIPH_PRIV
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -189,6 +198,15 @@
|
|||
#define GTZC_BASE_ADDRESS(mem)\
|
||||
( mem ## _BASE )
|
||||
|
||||
#if defined(GTZC_MPCBB_CR_INVSECSTATE_Pos)
|
||||
#define MPCBB_PARAMETERS_CHECK() \
|
||||
((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) \
|
||||
&& (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) \
|
||||
|| ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) \
|
||||
&& (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))
|
||||
#else
|
||||
#define MPCBB_PARAMETERS_CHECK() (0U == 1U)
|
||||
#endif /* defined(GTZC_MPCBB_CR_INVSECSTATE_Pos) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -235,17 +253,10 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
|
|||
uint32_t register_address;
|
||||
|
||||
/* check entry parameters */
|
||||
#if defined (GTZC_TZIC1)
|
||||
if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
|
||||
if (((PeriphAttributes & ~(GTZC_SEC_PRIV_MSK)) != 0U)
|
||||
|| (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
|
||||
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
|
||||
&& (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
|
||||
#else
|
||||
if ((PeriphAttributes > GTZC_TZSC_PERIPH_PRIV)
|
||||
|| (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
|
||||
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
|
||||
&& (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
|
@ -258,15 +269,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
|
|||
/* secure configuration */
|
||||
if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
|
||||
{
|
||||
SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
|
||||
SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
|
||||
SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
|
||||
SET_BIT(GTZC_TZSC1->SECCFGR1, GTZC_CFGR1_MSK);
|
||||
SET_BIT(GTZC_TZSC1->SECCFGR2, GTZC_CFGR2_MSK);
|
||||
SET_BIT(GTZC_TZSC1->SECCFGR3, GTZC_CFGR3_MSK);
|
||||
}
|
||||
else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
|
||||
{
|
||||
CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
|
||||
CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
|
||||
CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
|
||||
CLEAR_BIT(GTZC_TZSC1->SECCFGR1, GTZC_CFGR1_MSK);
|
||||
CLEAR_BIT(GTZC_TZSC1->SECCFGR2, GTZC_CFGR2_MSK);
|
||||
CLEAR_BIT(GTZC_TZSC1->SECCFGR3, GTZC_CFGR3_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -277,15 +288,15 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
|
|||
/* privilege configuration */
|
||||
if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
|
||||
{
|
||||
SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
|
||||
SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
|
||||
SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
|
||||
SET_BIT(GTZC_TZSC1->PRIVCFGR1, GTZC_CFGR1_MSK);
|
||||
SET_BIT(GTZC_TZSC1->PRIVCFGR2, GTZC_CFGR2_MSK);
|
||||
SET_BIT(GTZC_TZSC1->PRIVCFGR3, GTZC_CFGR3_MSK);
|
||||
}
|
||||
else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
|
||||
{
|
||||
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
|
||||
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
|
||||
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
|
||||
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, GTZC_CFGR1_MSK);
|
||||
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, GTZC_CFGR2_MSK);
|
||||
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, GTZC_CFGR3_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -363,6 +374,47 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
|
|||
|
||||
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
|
||||
{
|
||||
/* get privilege configuration: read each register and deploy each bit value
|
||||
* of corresponding index in the destination array
|
||||
*/
|
||||
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
|
||||
for (i = 0U; i < 32U; i++)
|
||||
{
|
||||
if (((reg_value & (1UL << i)) >> i) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
|
||||
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
|
||||
for (i = 32U; i < 64U; i++)
|
||||
{
|
||||
if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
|
||||
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
|
||||
for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
|
||||
{
|
||||
if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
#if defined (GTZC_TZIC1)
|
||||
/* get secure configuration: read each register and deploy each bit value
|
||||
* of corresponding index in the destination array
|
||||
|
|
@ -372,11 +424,11 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
|
|||
{
|
||||
if (((reg_value & (1UL << i)) >> i) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -385,11 +437,11 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
|
|||
{
|
||||
if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -398,60 +450,34 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
|
|||
{
|
||||
if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_SEC;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NSEC;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
|
||||
/* get privilege configuration: read each register and deploy each bit value
|
||||
* of corresponding index in the destination array
|
||||
*/
|
||||
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
|
||||
for (i = 0U; i < 32U; i++)
|
||||
{
|
||||
if (((reg_value & (1UL << i)) >> i) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
|
||||
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
|
||||
for (i = 32U; i < 64U; i++)
|
||||
{
|
||||
if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
|
||||
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
|
||||
for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
|
||||
{
|
||||
if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
|
||||
{
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* common case where only one peripheral is configured */
|
||||
/* privilege configuration */
|
||||
register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1)
|
||||
+ (4U * GTZC_GET_REG_INDEX(PeriphId));
|
||||
|
||||
if (((READ_BIT(*(__IO uint32_t *)register_address,
|
||||
1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
|
||||
!= 0U)
|
||||
{
|
||||
*PeriphAttributes = GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
*PeriphAttributes = GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
|
||||
/* common case where only one peripheral is configured */
|
||||
#if defined (GTZC_TZIC1)
|
||||
/* secure configuration */
|
||||
register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1)
|
||||
|
|
@ -461,28 +487,13 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
|
|||
1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
|
||||
!= 0U)
|
||||
{
|
||||
*PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
|
||||
*PeriphAttributes |= GTZC_TZSC_PERIPH_SEC;
|
||||
}
|
||||
else
|
||||
{
|
||||
*PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
|
||||
*PeriphAttributes |= GTZC_TZSC_PERIPH_NSEC;
|
||||
}
|
||||
#endif /* defined (GTZC_TZIC1) */
|
||||
|
||||
/* privilege configuration */
|
||||
register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1)
|
||||
+ (4U * GTZC_GET_REG_INDEX(PeriphId));
|
||||
|
||||
if (((READ_BIT(*(__IO uint32_t *)register_address,
|
||||
1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
|
||||
!= 0U)
|
||||
{
|
||||
*PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
|
||||
}
|
||||
else
|
||||
{
|
||||
*PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -834,17 +845,11 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
|
|||
if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
|
||||
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
|
||||
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
|
||||
|| ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
|
||||
&& (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
|
||||
|| ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
|
||||
&& (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
|
||||
|| MPCBB_PARAMETERS_CHECK())
|
||||
#else
|
||||
if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
|
||||
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
|
||||
|| ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
|
||||
&& (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
|
||||
|| ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
|
||||
&& (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
|
||||
|| MPCBB_PARAMETERS_CHECK())
|
||||
#endif /* defined (GTZC_MPCBB3) */
|
||||
{
|
||||
return HAL_ERROR;
|
||||
|
|
@ -1569,10 +1574,10 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
|
|||
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
|
||||
{
|
||||
/* same configuration is applied to all peripherals */
|
||||
WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->IER1, GTZC_CFGR1_MSK);
|
||||
WRITE_REG(GTZC_TZIC1->IER2, GTZC_CFGR2_MSK);
|
||||
WRITE_REG(GTZC_TZIC1->IER3, GTZC_CFGR3_MSK);
|
||||
WRITE_REG(GTZC_TZIC1->IER4, GTZC_CFGR4_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1634,7 +1639,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
|
|||
}
|
||||
|
||||
reg_value = READ_REG(GTZC_TZIC1->SR4);
|
||||
for (i = 96U; i < 128U; i++)
|
||||
for (i = 96U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
|
||||
{
|
||||
pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
|
||||
}
|
||||
|
|
@ -1673,10 +1678,10 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
|
|||
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
|
||||
{
|
||||
/* same configuration is applied to all peripherals */
|
||||
WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
|
||||
WRITE_REG(GTZC_TZIC1->FCR1, GTZC_CFGR1_MSK);
|
||||
WRITE_REG(GTZC_TZIC1->FCR2, GTZC_CFGR2_MSK);
|
||||
WRITE_REG(GTZC_TZIC1->FCR3, GTZC_CFGR3_MSK);
|
||||
WRITE_REG(GTZC_TZIC1->FCR4, GTZC_CFGR4_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1849,4 +1854,3 @@ __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -147,10 +147,10 @@ typedef struct
|
|||
/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(GTZC_MPCBB_CR_SRWILADIS_Pos)
|
||||
#define GTZC_MPCBB_SRWILADIS_ENABLE (0U)
|
||||
#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk)
|
||||
|
||||
#endif /* GTZC_MPCBB_CR_SRWILADIS_Pos */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -158,10 +158,10 @@ typedef struct
|
|||
/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(GTZC_MPCBB_CR_INVSECSTATE_Pos)
|
||||
#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U)
|
||||
#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk)
|
||||
|
||||
#endif /* GTZC_MPCBB_CR_INVSECSTATE_Pos */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -693,4 +693,3 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
|
|||
#endif
|
||||
|
||||
#endif /* STM32H5xx_HAL_GTZC_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -2530,15 +2530,58 @@ static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer,
|
|||
{
|
||||
uint32_t buffercounter;
|
||||
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
|
||||
uint8_t tmp1;
|
||||
uint8_t tmp2;
|
||||
uint8_t tmp3;
|
||||
|
||||
|
||||
for (buffercounter = 0U; buffercounter < Size ; buffercounter += 4U)
|
||||
for (buffercounter = 0U; buffercounter < (Size / 4U) ; buffercounter++)
|
||||
{
|
||||
/* Write input data 4 bytes at a time */
|
||||
hhash->Instance->DIN = *(uint32_t *)inputaddr;
|
||||
inputaddr += 4U;
|
||||
hhash->HashInCount += 4U;
|
||||
}
|
||||
|
||||
if ((Size % 4U) != 0U)
|
||||
{
|
||||
if (hhash->Init.DataType == HASH_HALFWORD_SWAP)
|
||||
{
|
||||
/* Write remaining input data */
|
||||
if ((Size % 4U) <= 2U)
|
||||
{
|
||||
hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr;
|
||||
}
|
||||
if ((Size % 4U) == 3U)
|
||||
{
|
||||
hhash->Instance->DIN = *(uint32_t *)inputaddr;
|
||||
}
|
||||
}
|
||||
else if ((hhash->Init.DataType == HASH_BYTE_SWAP)
|
||||
|| (hhash->Init.DataType == HASH_BIT_SWAP)) /* byte swap or bit swap or */
|
||||
{
|
||||
/* Write remaining input data */
|
||||
if ((Size % 4U) == 1U)
|
||||
{
|
||||
hhash->Instance->DIN = (uint32_t) * (uint8_t *)inputaddr;
|
||||
}
|
||||
if ((Size % 4U) == 2U)
|
||||
{
|
||||
hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr;
|
||||
}
|
||||
if ((Size % 4U) == 3U)
|
||||
{
|
||||
tmp1 = *(uint8_t *)inputaddr;
|
||||
tmp2 = *(((uint8_t *)inputaddr) + 1U);
|
||||
tmp3 = *(((uint8_t *)inputaddr) + 2U);
|
||||
hhash->Instance->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hhash->Instance->DIN = *(uint32_t *)inputaddr;
|
||||
}
|
||||
hhash->HashInCount += 4U;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -3073,43 +3116,20 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash,
|
|||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until flag is set */
|
||||
if (Status == RESET)
|
||||
while (__HAL_HASH_GET_FLAG(hhash, Flag) == Status)
|
||||
{
|
||||
while (__HAL_HASH_GET_FLAG(hhash, Flag) == RESET)
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Set State to Ready to be able to restart later on */
|
||||
hhash->State = HAL_HASH_STATE_READY;
|
||||
hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hhash);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while (__HAL_HASH_GET_FLAG(hhash, Flag) != RESET)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Set State to Ready to be able to restart later on */
|
||||
hhash->State = HAL_HASH_STATE_READY;
|
||||
hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hhash);
|
||||
/* Set State to Ready to be able to restart later on */
|
||||
hhash->State = HAL_HASH_STATE_READY;
|
||||
hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hhash);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -298,11 +298,13 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer
|
|||
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
|
||||
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
|
||||
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \
|
||||
(((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
(((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) )
|
||||
#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \
|
||||
((((__HANDLE__)->Instance->CR & (__FLAG__)) == \
|
||||
(__FLAG__)) ? SET : RESET) : \
|
||||
((((__HANDLE__)->Instance->SR & (__FLAG__)) == \
|
||||
(__FLAG__)) ? SET : RESET) )
|
||||
|
||||
/** @brief Clear the specified HASH flag.
|
||||
* @param __HANDLE__ specifies the HASH handle.
|
||||
|
|
|
|||
|
|
@ -88,7 +88,8 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t p
|
|||
|
||||
static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps);
|
||||
static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps);
|
||||
static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue);
|
||||
// Mbed: moved inline ahead of void
|
||||
static inline void HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -169,9 +170,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
|||
/* Init Host */
|
||||
(void)USB_HostInit(hhcd->Instance, hhcd->Init);
|
||||
|
||||
/* Deactivate the power down */
|
||||
hhcd->Instance->CNTR &= ~USB_CNTR_PDWN;
|
||||
|
||||
hhcd->State = HAL_HCD_STATE_READY;
|
||||
|
||||
/* Host Port State */
|
||||
|
|
@ -219,6 +217,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
__HAL_LOCK(hhcd);
|
||||
|
||||
if (ch_num > 16U)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U))
|
||||
{
|
||||
hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress;
|
||||
hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0;
|
||||
hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[0U].pmaaddr1;
|
||||
|
||||
hhcd->phy_chin_state[0U] = (((uint16_t)ch_num + 1U) << 4U) |
|
||||
((uint16_t)ep_type + 1U) |
|
||||
(((uint16_t)epnum & 0x0FU) << 8U);
|
||||
|
||||
hhcd->phy_chout_state[0U] = (((uint16_t)ch_num + 1U) << 4U) |
|
||||
((uint16_t)ep_type + 1U) |
|
||||
(((uint16_t)epnum & 0x0FU) << 8U);
|
||||
}
|
||||
|
||||
/* Check if the logical channel are already allocated */
|
||||
used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num);
|
||||
|
||||
|
|
@ -231,6 +250,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
/* No free Channel available, return error */
|
||||
if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -267,6 +287,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
if (status == HAL_ERROR)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -285,6 +306,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
if (status == HAL_ERROR)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -302,22 +324,28 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
if (status == HAL_ERROR)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* This is a dual EP0 PMA allocation */
|
||||
hhcd->ep0_PmaAllocState |= (0x1U << 12);
|
||||
|
||||
/* PMA Dynamic Allocation for EP0 OUT direction */
|
||||
hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR;
|
||||
status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U);
|
||||
|
||||
if (status == HAL_ERROR)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -327,6 +355,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
if (status == HAL_ERROR)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -352,6 +381,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
if (status == HAL_ERROR)
|
||||
{
|
||||
__HAL_UNLOCK(hhcd);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -730,8 +760,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
|
|||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
uint8_t phy_chnum;
|
||||
uint8_t chnum;
|
||||
uint32_t epch_reg;
|
||||
uint8_t ch_dir;
|
||||
uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance);
|
||||
|
||||
/* Port Change Detected (Connection/Disconnection) */
|
||||
|
|
@ -749,50 +778,21 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
/* Correct Transaction Detected -------*/
|
||||
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
|
||||
{
|
||||
/* Handle Host channel Interrupt */
|
||||
for (phy_chnum = 0U; phy_chnum < hhcd->Init.Host_channels; phy_chnum++)
|
||||
/* Get Physical channel */
|
||||
phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd);
|
||||
|
||||
/* Get channel direction */
|
||||
ch_dir = (uint8_t)__HAL_HCD_GET_CHDIR(hhcd);
|
||||
|
||||
if (ch_dir == CH_OUT_DIR)
|
||||
{
|
||||
if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTRX) != 0U)
|
||||
{
|
||||
/* Get Logical channel to check if the channel is already opened */
|
||||
chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U);
|
||||
|
||||
if (chnum != HCD_LOGICAL_CH_NOT_OPENED)
|
||||
{
|
||||
/* Call Channel_IN_IRQ() */
|
||||
HCD_HC_IN_IRQHandler(hhcd, chnum);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Channel was not closed correctly still have interrupt */
|
||||
epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum);
|
||||
epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRRX) & (~USB_CH_VTRX))) |
|
||||
(USB_CH_VTTX | USB_CH_ERRTX);
|
||||
|
||||
HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg);
|
||||
}
|
||||
}
|
||||
|
||||
if ((HCD_GET_CHANNEL(hhcd->Instance, phy_chnum) & USB_CH_VTTX) != 0U)
|
||||
{
|
||||
/* Get Logical channel to check if the channel is already opened */
|
||||
chnum = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U);
|
||||
|
||||
if (chnum != HCD_LOGICAL_CH_NOT_OPENED)
|
||||
{
|
||||
/*Call Channel_OUT_IRQ()*/
|
||||
HCD_HC_OUT_IRQHandler(hhcd, chnum);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear Error & unwanted VTTX or Channel was not closed correctly */
|
||||
epch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum);
|
||||
epch_reg = (epch_reg & (USB_CHEP_REG_MASK & (~USB_CH_ERRTX) & (~USB_CH_VTTX))) |
|
||||
(USB_CH_VTRX | USB_CH_ERRRX);
|
||||
|
||||
HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, epch_reg);
|
||||
}
|
||||
}
|
||||
/* Call Channel_OUT_IRQ() */
|
||||
HCD_HC_OUT_IRQHandler(hhcd, phy_chnum);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Call Channel_IN_IRQ() */
|
||||
HCD_HC_IN_IRQHandler(hhcd, phy_chnum);
|
||||
}
|
||||
|
||||
return;
|
||||
|
|
@ -1292,17 +1292,22 @@ transfers.
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
__IO uint32_t count = HCD_PDWN_EXIT_CNT;
|
||||
|
||||
__HAL_LOCK(hhcd);
|
||||
|
||||
/*Set the PullDown on the PHY */
|
||||
hhcd->Instance->BCDR |= USB_BCDR_DPPD;
|
||||
|
||||
/* Clear Reset */
|
||||
hhcd->Instance->CNTR &= ~USB_CNTR_USBRST;
|
||||
|
||||
/*Remove PowerDown */
|
||||
/* Remove PowerDown */
|
||||
hhcd->Instance->CNTR &= ~USB_CNTR_PDWN;
|
||||
|
||||
/* Few cycles to ensure exit from powerdown */
|
||||
while (count > 0U)
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
/* Clear Reset */
|
||||
hhcd->Instance->CNTR &= ~USB_CNTR_USBRST;
|
||||
|
||||
__HAL_UNLOCK(hhcd);
|
||||
|
||||
return HAL_OK;
|
||||
|
|
@ -1347,7 +1352,7 @@ HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd)
|
|||
/* wait for Suspend Ready */
|
||||
while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U)
|
||||
{
|
||||
if (++count > 0xFFFFFFU)
|
||||
if (++count > HAL_USB_TIMEOUT)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
|
@ -1581,7 +1586,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U)
|
||||
{
|
||||
/* manage multiple Xfer */
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
|
||||
/* check if we need to free user buffer */
|
||||
if ((regvalue & USB_CH_DTOG_RX) != 0U)
|
||||
|
|
@ -1620,7 +1625,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
else
|
||||
{
|
||||
/* Transfer complete state */
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
|
||||
|
|
@ -1642,7 +1647,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U)
|
||||
{
|
||||
/* manage multiple Xfer */
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
|
||||
/* check if we need to free user buffer */
|
||||
if ((regvalue & USB_CH_DTOG_RX) == 0U)
|
||||
|
|
@ -1683,7 +1688,7 @@ static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
else
|
||||
{
|
||||
/* Transfer complete state */
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
|
||||
|
|
@ -1793,7 +1798,8 @@ static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd,
|
|||
* @param regvalue contain Snapshot of the EPCHn register when ISR is detected
|
||||
* @retval none
|
||||
*/
|
||||
static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
// Mbed: moved inline ahead of void
|
||||
static inline void HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
||||
uint8_t phy_chnum, uint32_t regvalue)
|
||||
{
|
||||
/* Check if Double buffer isochronous */
|
||||
|
|
@ -1857,16 +1863,17 @@ static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
/**
|
||||
* @brief Handle Host Channel IN interrupt requests.
|
||||
* @param hhcd HCD handle
|
||||
* @param ch_num Channel number
|
||||
* This parameter can be a value from 1 to 15
|
||||
* @param chnum Channel number
|
||||
* This parameter can be a value from 1 to 8
|
||||
* @retval none
|
||||
*/
|
||||
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
|
||||
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
||||
{
|
||||
uint16_t received_bytes;
|
||||
uint8_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd);
|
||||
uint8_t phy_chnum = chnum;
|
||||
uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U);
|
||||
|
||||
/*Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */
|
||||
/* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */
|
||||
uint32_t ch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum);
|
||||
|
||||
/* Manage Correct Transaction */
|
||||
|
|
@ -1908,8 +1915,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
|
|||
if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) ||
|
||||
((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet)))
|
||||
{
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1922,18 +1929,24 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
|
|||
if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) ||
|
||||
(hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR))
|
||||
{
|
||||
hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
|
||||
hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U;
|
||||
}
|
||||
}
|
||||
/* manage NACK Response */
|
||||
/* Manage NACK Response */
|
||||
else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK)
|
||||
&& (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE))
|
||||
{
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY;
|
||||
hhcd->hc[ch_num & 0xFU].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_NAK;
|
||||
|
||||
if (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)
|
||||
{
|
||||
/* Close the channel */
|
||||
HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS);
|
||||
}
|
||||
}
|
||||
/* manage STALL Response */
|
||||
/* Manage STALL Response */
|
||||
else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL)
|
||||
{
|
||||
(void)HAL_HCD_HC_Halt(hhcd, ch_num);
|
||||
|
|
@ -2001,16 +2014,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
|
|||
* @brief Handle Host Channel OUT interrupt requests.
|
||||
* @param hhcd HCD handle
|
||||
* @param chnum Channel number
|
||||
* This parameter can be a value from 1 to 15
|
||||
* This parameter can be a value from 1 to 8
|
||||
* @retval none
|
||||
*/
|
||||
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
||||
{
|
||||
uint16_t data_xfr;
|
||||
__IO uint32_t WregCh;
|
||||
uint16_t data_xfr;
|
||||
uint8_t phy_chnum = chnum;
|
||||
|
||||
/* Get Physical Channel number */
|
||||
uint32_t phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd);
|
||||
/* Get Virtual Channel number */
|
||||
uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U);
|
||||
|
||||
/* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */
|
||||
uint32_t ch_reg = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum);
|
||||
|
|
@ -2021,7 +2035,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
/* Handle Isochronous channel */
|
||||
if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS)
|
||||
{
|
||||
/* correct transaction */
|
||||
/* Correct transaction */
|
||||
if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U)
|
||||
{
|
||||
/* Double buffer isochronous out */
|
||||
|
|
@ -2030,7 +2044,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U);
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
else /* double buffer isochronous out */
|
||||
else /* Double buffer isochronous out */
|
||||
{
|
||||
/* Odd Transaction */
|
||||
if ((ch_reg & USB_CH_DTOG_TX) != 0U)
|
||||
|
|
@ -2048,8 +2062,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
/* Transfer complete state */
|
||||
hhcd->hc[chnum & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[chnum & 0xFU].urb_state = URB_DONE;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
|
||||
}
|
||||
|
||||
/*Clear Correct Transfer */
|
||||
|
|
@ -2057,9 +2071,9 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
|
||||
/*TX COMPLETE*/
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#else
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
|
||||
}
|
||||
|
|
@ -2070,37 +2084,37 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
{
|
||||
data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U);
|
||||
|
||||
if (hhcd->hc[chnum & 0xFU].xfer_len >= data_xfr)
|
||||
if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr)
|
||||
{
|
||||
hhcd->hc[chnum & 0xFU].xfer_len -= data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr;
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[chnum & 0xFU].xfer_len = 0U;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_len = 0U;
|
||||
}
|
||||
|
||||
if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) ||
|
||||
(hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR))
|
||||
{
|
||||
hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U;
|
||||
}
|
||||
|
||||
/* Transfer no yet finished only one packet of mps is transferred and ACKed from device */
|
||||
if (hhcd->hc[chnum & 0xFU].xfer_len != 0U)
|
||||
if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U)
|
||||
{
|
||||
/* manage multiple Xfer */
|
||||
hhcd->hc[chnum & 0xFU].xfer_buff += data_xfr;
|
||||
hhcd->hc[chnum & 0xFU].xfer_count += data_xfr;
|
||||
/* Manage multiple Xfer */
|
||||
hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
|
||||
/* start a new transfer */
|
||||
(void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[chnum & 0xFU]);
|
||||
/* Start a new transfer */
|
||||
(void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Transfer complete */
|
||||
hhcd->hc[chnum & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[chnum & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[chnum & 0xFU].urb_state = URB_DONE;
|
||||
|
||||
if ((hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_BULK) ||
|
||||
(hhcd->hc[chnum & 0xFU].ep_type == EP_TYPE_INTR))
|
||||
{
|
||||
hhcd->hc[chnum & 0xFU].toggle_out ^= 1U;
|
||||
}
|
||||
hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XFRC;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE;
|
||||
}
|
||||
}
|
||||
/* Check NACK Response */
|
||||
|
|
@ -2108,41 +2122,41 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK))
|
||||
{
|
||||
/* Update Channel status */
|
||||
hhcd->hc[chnum & 0xFU].state = HC_NAK;
|
||||
hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY;
|
||||
hhcd->hc[chnum & 0xFU].ErrCnt = 0U;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_NAK;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY;
|
||||
hhcd->hc[ch_num & 0xFU].ErrCnt = 0U;
|
||||
|
||||
/* Get Channel register value */
|
||||
WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum);
|
||||
|
||||
/*clear NAK status*/
|
||||
/* Clear NAK status */
|
||||
WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK;
|
||||
|
||||
/* Update channel register Value */
|
||||
HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh);
|
||||
|
||||
if (hhcd->hc[chnum & 0xFU].doublebuffer == 0U)
|
||||
if (hhcd->hc[ch_num & 0xFU].doublebuffer == 0U)
|
||||
{
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#else
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
/* Check STALL Response */
|
||||
else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL)
|
||||
{
|
||||
(void) HAL_HCD_HC_Halt(hhcd, (uint8_t)chnum);
|
||||
hhcd->hc[chnum & 0xFU].state = HC_STALL;
|
||||
hhcd->hc[chnum & 0xFU].urb_state = URB_STALL;
|
||||
(void) HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num);
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_STALL;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL;
|
||||
}
|
||||
#if (USE_USB_DOUBLE_BUFFER == 1U)
|
||||
/* Check double buffer ACK in case of bulk transaction */
|
||||
else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF)
|
||||
{
|
||||
/* Double buffer management Bulk Out */
|
||||
(void) HCD_HC_OUT_BulkDb(hhcd, chnum, (uint8_t)phy_chnum, ch_reg);
|
||||
(void) HCD_HC_OUT_BulkDb(hhcd, ch_num, (uint8_t)phy_chnum, ch_reg);
|
||||
}
|
||||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
else
|
||||
|
|
@ -2153,38 +2167,38 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|||
if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK)
|
||||
{
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#else
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum);
|
||||
} /* end no isochronous */
|
||||
} /* End no isochronous */
|
||||
}
|
||||
/*------ Manage Transaction Error------*/
|
||||
else
|
||||
{
|
||||
hhcd->hc[chnum & 0xFU].ErrCnt++;
|
||||
if (hhcd->hc[chnum & 0xFU].ErrCnt > 3U)
|
||||
hhcd->hc[ch_num & 0xFU].ErrCnt++;
|
||||
if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U)
|
||||
{
|
||||
HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS);
|
||||
hhcd->hc[chnum & 0xFU].urb_state = URB_ERROR;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
hhcd->hc[chnum & 0xFU].urb_state = URB_NOTREADY;
|
||||
hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY;
|
||||
}
|
||||
|
||||
hhcd->hc[chnum & 0xFU].state = HC_XACTERR;
|
||||
hhcd->hc[ch_num & 0xFU].state = HC_XACTERR;
|
||||
|
||||
/*Clear ERR_TX*/
|
||||
/* Clear ERR_TX */
|
||||
HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum);
|
||||
|
||||
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#else
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)chnum, hhcd->hc[chnum & 0xFU].urb_state);
|
||||
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state);
|
||||
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
|
@ -2206,13 +2220,13 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|||
/* Host Port State */
|
||||
hhcd->HostState = HCD_HCD_STATE_DISCONNECTED;
|
||||
|
||||
/* clear all allocated virtual channel */
|
||||
/* Clear all allocated virtual channel */
|
||||
HAL_HCD_ClearPhyChannel(hhcd);
|
||||
|
||||
/* Reset the PMA current pointer */
|
||||
(void)HAL_HCD_PMAReset(hhcd);
|
||||
|
||||
/* reset Ep0 Pma allocation state */
|
||||
/* Reset Ep0 Pma allocation state */
|
||||
hhcd->ep0_PmaAllocState = 0U;
|
||||
|
||||
/* Disconnection Callback */
|
||||
|
|
@ -2620,7 +2634,7 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
/* Get a FreePMA Address */
|
||||
pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps);
|
||||
|
||||
/* if there is no free space to allocate */
|
||||
/* If there is no free space to allocate */
|
||||
if (pma_addr0 == 0xFFFFU)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
|
|
@ -2635,7 +2649,8 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
|
|||
|
||||
if (hc->ep_num == 0U)
|
||||
{
|
||||
hhcd->ep0_PmaAllocState = ch_num;
|
||||
hhcd->ep0_PmaAllocState &= 0xFFF0U;
|
||||
hhcd->ep0_PmaAllocState |= ch_num;
|
||||
hhcd->ep0_PmaAllocState |= (1U << 8);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -359,12 +359,15 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
|
|||
/** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SNG_BUF 0U
|
||||
#define HCD_DBL_BUF 1U
|
||||
#define HCD_SNG_BUF 0U
|
||||
#define HCD_DBL_BUF 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Powerdown exit count */
|
||||
#define HCD_PDWN_EXIT_CNT 0x100U
|
||||
|
||||
/* Set Channel */
|
||||
#define HCD_SET_CHANNEL USB_DRD_SET_CHEP
|
||||
|
||||
|
|
@ -495,15 +498,16 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
|
|||
__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
|
||||
{
|
||||
uint32_t HostCoreSpeed;
|
||||
uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum);
|
||||
__IO uint32_t count = 10U;
|
||||
|
||||
/* Get Host core Speed */
|
||||
HostCoreSpeed = USB_GetHostSpeed(Instance);
|
||||
|
||||
/* Count depends on device LS */
|
||||
if (HostCoreSpeed == USB_DRD_SPEED_LS)
|
||||
if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP))
|
||||
{
|
||||
count = (63U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U;
|
||||
count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U;
|
||||
}
|
||||
|
||||
if (count > 15U)
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@
|
|||
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
|
||||
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
|
||||
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
|
||||
|
|
@ -156,7 +156,7 @@
|
|||
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
|
||||
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
|
||||
(++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
|
||||
|
|
@ -214,7 +214,7 @@
|
|||
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
|
||||
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
|
||||
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
|
||||
|
|
@ -1363,6 +1363,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
|||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint16_t tmpXferCount;
|
||||
HAL_StatusTypeDef error;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
|
|
@ -1389,14 +1391,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
|||
/* Enable Address Acknowledge */
|
||||
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
|
||||
|
||||
/* Wait until ADDR flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Preload TX data if no stretch enable */
|
||||
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
|
||||
{
|
||||
|
|
@ -1410,6 +1404,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
|||
hi2c->XferCount--;
|
||||
}
|
||||
|
||||
/* Wait until ADDR flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear ADDR flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
|
||||
|
||||
|
|
@ -1421,6 +1427,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
|||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -1433,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
|||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -1456,31 +1470,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
|||
}
|
||||
|
||||
/* Wait until AF flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
|
||||
|
||||
if (error != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0 */
|
||||
|
||||
tmpXferCount = hi2c->XferCount;
|
||||
if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
|
||||
{
|
||||
/* Reset ErrorCode to NONE */
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Clear AF flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Wait until STOP flag is set */
|
||||
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
||||
else
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
/* Clear AF flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Wait until STOP flag is set */
|
||||
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear STOP flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Clear STOP flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
|
||||
/* Wait until BUSY flag is reset */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
|
|
@ -4785,7 +4816,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
|
||||
* @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
|
|
@ -4794,7 +4825,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
|
||||
{
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
|
||||
HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
|
||||
|
||||
if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
|
@ -5460,9 +5493,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
|||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
|
|
@ -5891,9 +5923,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
|||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, ITFlags);
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
|
|
@ -6495,6 +6526,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
{
|
||||
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
||||
uint32_t tmpITFlags = ITFlags;
|
||||
uint32_t tmpoptions = hi2c->XferOptions;
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
|
|
@ -6584,6 +6616,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
|||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0*/
|
||||
/* So clear Flag NACKF only */
|
||||
if (hi2c->XferCount == 0U)
|
||||
{
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
||||
Warning[Pa134]: left and right operands are identical */
|
||||
{
|
||||
/* Call I2C Listen complete process */
|
||||
I2C_ITListenCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Last Byte is Transmitted */
|
||||
/* Call I2C Slave Sequential complete process */
|
||||
I2C_ITSlaveSeqCplt(hi2c);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
|
||||
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
||||
{
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
I2C_ITError(hi2c, hi2c->ErrorCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
|
|
@ -7172,6 +7255,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
|
|||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
|
|
@ -7283,16 +7372,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
|||
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
||||
uint32_t Tickstart)
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check if a STOPF is detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
|
||||
{
|
||||
/* Check if an RXNE is pending */
|
||||
/* Store Last receive data if any */
|
||||
|
|
@ -7300,19 +7391,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
|||
{
|
||||
/* Return HAL_OK */
|
||||
/* The Reading of data from RXDR will be done in caller function */
|
||||
return HAL_OK;
|
||||
status = HAL_OK;
|
||||
}
|
||||
else
|
||||
|
||||
/* Check a no-acknowledge have been detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
{
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
{
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
|
|
@ -7326,12 +7412,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
|||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
|
||||
{
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
|
||||
{
|
||||
|
|
@ -7341,11 +7431,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
|||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -118,8 +118,6 @@ typedef enum
|
|||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@
|
|||
|
||||
When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak callbacks are used.
|
||||
|
||||
|
||||
@endverbatim
|
||||
|
|
@ -540,6 +540,8 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
|
|||
* the configuration information for the specified I2S.
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @note The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
|
||||
* to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
|
|
@ -554,8 +556,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
|
|||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hi2s);
|
||||
|
||||
if (HAL_I2S_STATE_READY == hi2s->State)
|
||||
{
|
||||
|
|
@ -637,8 +637,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
|
|||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -648,15 +646,14 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
|
|||
* @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2S.
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* @note The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
|
||||
* to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hi2s);
|
||||
|
||||
if (HAL_I2S_STATE_READY == hi2s->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
|
|
@ -736,8 +733,6 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
|
|||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hi2s);
|
||||
return status;
|
||||
}
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -24,7 +24,6 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(DEVICE_I3C)
|
||||
|
||||
/* Includes ----------------------------------------------------------------------------------------------------------*/
|
||||
#include "stm32h5xx_hal_def.h"
|
||||
|
|
@ -339,6 +338,56 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3C_BCRTypeDef_Structure_definition I3C BCRTypeDef Structure definition
|
||||
* @brief I3C BCRTypeDef Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState MaxDataSpeedLimitation; /*!< Max data speed limitation */
|
||||
FunctionalState IBIRequestCapable; /*!< IBI request capable */
|
||||
FunctionalState IBIPayload; /*!< IBI payload data */
|
||||
FunctionalState OfflineCapable; /*!< Offline capable */
|
||||
FunctionalState VirtualTargetSupport; /*!< Virtual target support */
|
||||
FunctionalState AdvancedCapabilities; /*!< Advanced capabilities */
|
||||
FunctionalState DeviceRole; /*!< Device role */
|
||||
|
||||
} I3C_BCRTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3C_PIDTypeDef_Structure_definition I3C PIDTypeDef Structure definition
|
||||
* @brief I3C_PIDTypeDef Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t MIPIMID; /*!< MIPI Manufacturer ID */
|
||||
uint8_t IDTSEL; /*!< Provisioned ID Type Selector */
|
||||
uint16_t PartID; /*!< Part ID device vendor to define */
|
||||
uint8_t MIPIID; /*!< Instance ID */
|
||||
|
||||
} I3C_PIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3C_ENTDAAPayloadTypeDef_Structure_definition I3C ENTDAAPayloadTypeDef Structure definition
|
||||
* @brief I3C ENTDAAPayloadTypeDef Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I3C_BCRTypeDef BCR; /*!< Bus Characteristics Register */
|
||||
uint32_t DCR; /*!< Device Characteristics Register */
|
||||
I3C_PIDTypeDef PID; /*!< Provisioned ID */
|
||||
|
||||
} I3C_ENTDAAPayloadTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3C_PrivateTypeDef_Structure_definition I3C PrivateTypeDef Structure definition
|
||||
* @brief I3C PrivateTypeDef Structure definition
|
||||
* @{
|
||||
|
|
@ -420,8 +469,7 @@ typedef struct __I3C_HandleTypeDef
|
|||
__IO uint32_t ErrorCode; /*!< I3C Error code */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I3C_HandleTypeDef *hi3c,
|
||||
uint32_t itFlags,
|
||||
uint32_t itSources); /*!< I3C transfer IRQ handler function pointer */
|
||||
uint32_t itMasks); /*!< I3C transfer IRQ handler function pointer */
|
||||
|
||||
void(*ptrTxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C transmit function pointer */
|
||||
|
||||
|
|
@ -915,7 +963,27 @@ typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c,
|
|||
/** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */
|
||||
#define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3C_PATTERN_CONFIGURATION I3C PATTERN CONFIGURATION
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I3C_TARGET_RESET_PATTERN 0x00000001U /*!< Target reset pattern */
|
||||
#define HAL_I3C_HDR_EXIT_PATTERN 0x00000002U /*!< HDR exit pattern */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3C_RESET_PATTERN RESET PATTERN
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I3C_RESET_PATTERN_DISABLE 0x00000000U
|
||||
/*!< Standard STOP condition emitted at the end of a frame */
|
||||
#define HAL_I3C_RESET_PATTERN_ENABLE I3C_CFGR_RSTPTRN
|
||||
/*!< Reset pattern is inserted before the STOP condition of any emitted frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1081,6 +1149,8 @@ HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c,
|
|||
I3C_XferTypeDef *pXferData,
|
||||
uint8_t nbFrame,
|
||||
uint32_t option);
|
||||
HAL_StatusTypeDef HAL_I3C_Ctrl_SetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t resetPattern);
|
||||
HAL_StatusTypeDef HAL_I3C_Ctrl_GetConfigResetPattern(I3C_HandleTypeDef *hi3c, uint32_t *pResetPattern);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1160,6 +1230,9 @@ HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c,
|
|||
uint8_t devAddress,
|
||||
uint32_t trials,
|
||||
uint32_t timeout);
|
||||
/* Controller arbitration APIs */
|
||||
HAL_StatusTypeDef HAL_I3C_Ctrl_GenerateArbitration(I3C_HandleTypeDef *hi3c, uint32_t timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1194,6 +1267,9 @@ uint32_t HAL_I3C_GetError(const I3C_HandleTypeDef *hi3c);
|
|||
HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c,
|
||||
uint32_t notifyId,
|
||||
I3C_CCCInfoTypeDef *pCCCInfo);
|
||||
HAL_StatusTypeDef HAL_I3C_Get_ENTDAA_Payload_Info(I3C_HandleTypeDef *hi3c,
|
||||
uint64_t ENTDAA_payload,
|
||||
I3C_ENTDAAPayloadTypeDef *pENTDAA_payload);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1291,7 +1367,8 @@ HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c,
|
|||
#define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD)
|
||||
|
||||
#define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
|
||||
|
||||
#define IS_I3C_RESET_PATTERN(__RSTPTRN__) (((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_ENABLE) || \
|
||||
((__RSTPTRN__) == HAL_I3C_RESET_PATTERN_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1312,7 +1389,6 @@ HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c,
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* DEVICE_I3C */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,6 +51,11 @@
|
|||
(#) Enable and disable the Instruction Cache with respectively
|
||||
HAL_ICACHE_Enable() and HAL_ICACHE_Disable().
|
||||
Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
|
||||
To ensure a deterministic cache behavior after power on, system reset or after
|
||||
a call to @ref HAL_ICACHE_Disable(), the application must call
|
||||
@ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset
|
||||
or cache disable, an automatic cache invalidation procedure is launched and the
|
||||
cache is bypassed until the operation completes.
|
||||
|
||||
(#) Initiate the cache maintenance invalidation procedure with either
|
||||
HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT()
|
||||
|
|
@ -185,34 +190,34 @@ HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
|
|||
|
||||
/**
|
||||
* @brief DeInitialize the Instruction Cache.
|
||||
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
|
||||
* @retval HAL status (HAL_OK)
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Disable cache with reset value for 2-ways set associative mode */
|
||||
WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
|
||||
|
||||
/* Stop monitor and reset monitor values */
|
||||
(void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS);
|
||||
(void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS);
|
||||
|
||||
#if defined(ICACHE_CRRx_REN)
|
||||
/* No remapped regions */
|
||||
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0);
|
||||
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1);
|
||||
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2);
|
||||
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3);
|
||||
#endif /* ICACHE_CRRx_REN */
|
||||
|
||||
/* Wait for end of invalidate cache procedure */
|
||||
status = HAL_ICACHE_WaitForInvalidateComplete();
|
||||
/* Reset interrupt enable value */
|
||||
WRITE_REG(ICACHE->IER, 0U);
|
||||
|
||||
/* Clear any pending flags */
|
||||
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
|
||||
|
||||
return status;
|
||||
/* Disable cache then set default associative mode value */
|
||||
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
|
||||
WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
|
||||
|
||||
/* Stop monitor and reset monitor values */
|
||||
CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);
|
||||
SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
|
||||
CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));
|
||||
|
||||
#if defined(ICACHE_CRRx_REN)
|
||||
/* Reset regions configuration values */
|
||||
WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
|
||||
WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
|
||||
WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
|
||||
WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);
|
||||
#endif /* ICACHE_CRRx_REN */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -285,22 +290,15 @@ HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
|
|||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check no ongoing operation */
|
||||
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
|
||||
/* Check if no ongoing operation */
|
||||
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Make sure BSYENDF is reset before to start cache invalidation */
|
||||
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
|
||||
|
||||
/* Launch cache invalidation */
|
||||
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
|
||||
|
||||
status = HAL_ICACHE_WaitForInvalidateComplete();
|
||||
}
|
||||
|
||||
status = HAL_ICACHE_WaitForInvalidateComplete();
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -401,6 +401,176 @@ extern "C" {
|
|||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif (defined(STM32H523xx) || defined(STM32H533xx))
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
|
|
|
|||
|
|
@ -1125,7 +1125,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_LPTIM1_CH2))))
|
||||
#else
|
||||
#elif defined(LPTIM3) && defined(LPTIM4) && defined(LPTIM5) && defined(LPTIM6)
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2) || \
|
||||
|
|
@ -1134,6 +1134,11 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
((__INSTANCE__) == LPTIM5) || \
|
||||
((__INSTANCE__) == LPTIM6)) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)))
|
||||
#else
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2)) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)))
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
#if defined(STM32H503xx)
|
||||
|
|
@ -1141,7 +1146,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2)) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
|
||||
#else
|
||||
#elif defined(LPTIM3) && defined(LPTIM5) && defined(LPTIM6)
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2) || \
|
||||
|
|
@ -1149,6 +1154,11 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
((__INSTANCE__) == LPTIM5) || \
|
||||
((__INSTANCE__) == LPTIM6)) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
|
||||
#else
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2)) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
#if defined(STM32H503xx)
|
||||
|
|
@ -1177,7 +1187,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
((__SOURCE__) == LPTIM_IC2SOURCE_HSI_1024) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_CSI_128) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_HSI_8))))
|
||||
#else
|
||||
#elif defined(LPTIM3) && defined(LPTIM5) && defined(LPTIM6)
|
||||
#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2) || \
|
||||
|
|
@ -1206,6 +1216,23 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
|| \
|
||||
(((__INSTANCE__) == LPTIM6) && \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_GPIO)))
|
||||
#else
|
||||
#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) || \
|
||||
((__INSTANCE__) == LPTIM2)) && \
|
||||
(((__SOURCE__) == LPTIM_IC1SOURCE_GPIO)))
|
||||
|
||||
#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_LSI) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_LSE))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
(((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_HSI_1024) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_CSI_128) || \
|
||||
((__SOURCE__) == LPTIM_IC2SOURCE_HSI_8))))
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
#define LPTIM_CHANNEL_STATE_GET(__INSTANCE__, __CHANNEL__)\
|
||||
|
|
@ -1232,7 +1259,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
(((__INSTANCE__) == LPTIM2_NS) && \
|
||||
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == LPTIM_CHANNEL_2))))
|
||||
#else
|
||||
#elif defined(LPTIM3) && defined(LPTIM4) && defined(LPTIM5) && defined(LPTIM6)
|
||||
#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
|
||||
(((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \
|
||||
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
|
||||
|
|
@ -1256,6 +1283,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
|||
((((__INSTANCE__) == LPTIM6_NS) || ((__INSTANCE__) == LPTIM6_S)) && \
|
||||
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == LPTIM_CHANNEL_2))))
|
||||
#else
|
||||
#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
|
||||
(((((__INSTANCE__) == LPTIM1_NS) || ((__INSTANCE__) == LPTIM1_S)) && \
|
||||
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == LPTIM_CHANNEL_2))) \
|
||||
|| \
|
||||
((((__INSTANCE__) == LPTIM2_NS) || ((__INSTANCE__) == LPTIM2_S)) && \
|
||||
(((__CHANNEL__) == LPTIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == LPTIM_CHANNEL_2))))
|
||||
#endif /* STM32H503xx */
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@
|
|||
|
||||
(#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
|
||||
|
||||
|
||||
*** MMC Card Initialization and configuration ***
|
||||
================================================
|
||||
[..]
|
||||
|
|
@ -549,7 +548,6 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the MMC MSP.
|
||||
* @param hmmc: Pointer to MMC handle
|
||||
|
|
@ -3537,7 +3535,6 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the mmc card.
|
||||
* @param hmmc: Pointer to MMC handle
|
||||
|
|
@ -3621,7 +3618,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
|
|||
hmmc->ErrorCode |= errorstate;
|
||||
}
|
||||
|
||||
|
||||
/* Get Extended CSD parameters */
|
||||
if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
|
||||
{
|
||||
|
|
@ -3871,7 +3867,6 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
|
|||
|
||||
tmp = hmmc->pRxBuffPtr;
|
||||
|
||||
|
||||
if (hmmc->RxXferSize >= SDMMC_FIFO_SIZE)
|
||||
{
|
||||
/* Read data from SDMMC Rx FIFO */
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
|
|||
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
|
||||
{
|
||||
hnand->Config.PageSize = pDeviceConfig->PageSize;
|
||||
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
|
|||
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
|
|||
|
|
@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
|
|||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
||||
uint16_t ep_mps, uint8_t ep_type)
|
||||
{
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
PCD_EPTypeDef *ep;
|
||||
|
||||
if ((ep_addr & 0x80U) == 0x80U)
|
||||
|
|
@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|||
}
|
||||
|
||||
ep->num = ep_addr & EP_ADDR_MSK;
|
||||
ep->maxpacket = ep_mps;
|
||||
ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
|
||||
ep->type = ep_type;
|
||||
|
||||
/* Set initial data PID. */
|
||||
|
|
@ -1619,11 +1619,20 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
* @param ep_addr endpoint address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(ep_addr);
|
||||
__HAL_LOCK(hpcd);
|
||||
|
||||
if ((ep_addr & 0x80U) == 0x80U)
|
||||
{
|
||||
(void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)USB_FlushRxFifo(hpcd->Instance);
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -2218,13 +2227,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
|
|||
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB_DRD_FS) */
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -330,7 +330,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
|
|||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
|
|
|
|||
|
|
@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Activate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
|
|
@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Send LPM message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ extern "C" {
|
|||
*/
|
||||
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress);
|
||||
|
||||
|
|
|
|||
|
|
@ -309,6 +309,7 @@ HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode);
|
|||
void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
|
||||
void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
|
||||
void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in);
|
||||
void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in);
|
||||
void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
|
||||
void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
|
||||
void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
|
||||
|
|
@ -727,6 +728,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca
|
|||
(++) HAL_PKA_ECCMulFastMode()
|
||||
(++) HAL_PKA_ECCMul_GetResult();
|
||||
|
||||
(++) HAL_PKA_ECCMulEx()
|
||||
(++) HAL_PKA_ECCDoubleBaseLadder()
|
||||
(++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
|
||||
(++) HAL_PKA_ECCProjective2Affine()
|
||||
|
|
@ -771,6 +773,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca
|
|||
(++) HAL_PKA_ECCMulFastMode_IT();
|
||||
(++) HAL_PKA_ECCMul_GetResult();
|
||||
|
||||
(++) HAL_PKA_ECCMulEx_IT();
|
||||
(++) HAL_PKA_ECCDoubleBaseLadder_IT()
|
||||
(++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
|
||||
(++) HAL_PKA_ECCProjective2Affine_IT()
|
||||
|
|
@ -808,9 +811,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *i
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ModExp_Set(hpka, in);
|
||||
|
||||
opsize = in->OpSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
|
||||
}
|
||||
|
|
@ -825,9 +826,7 @@ HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ModExp_Set(hpka, in);
|
||||
|
||||
opsize = in->OpSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
|
||||
}
|
||||
|
|
@ -843,9 +842,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFast
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ModExpFastMode_Set(hpka, in);
|
||||
|
||||
opsize = in->OpSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
|
||||
}
|
||||
|
|
@ -860,9 +857,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ModExpFastMode_Set(hpka, in);
|
||||
|
||||
opsize = in->OpSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
|
||||
}
|
||||
|
|
@ -880,9 +875,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpP
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ModExpProtectMode_Set(hpka, in);
|
||||
|
||||
opsize = in->OpSize;
|
||||
|
||||
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout);
|
||||
}
|
||||
|
||||
|
|
@ -897,12 +890,11 @@ HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModE
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ModExpProtectMode_Set(hpka, in);
|
||||
|
||||
opsize = in->OpSize;
|
||||
|
||||
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Retrieve operation result.
|
||||
* @param hpka PKA handle
|
||||
|
|
@ -931,9 +923,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInType
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ECDSASign_Set(hpka, in);
|
||||
|
||||
primeordersize = in->primeOrderSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
|
||||
}
|
||||
|
|
@ -948,9 +938,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ECDSASign_Set(hpka, in);
|
||||
|
||||
primeordersize = in->primeOrderSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
|
||||
}
|
||||
|
|
@ -1128,9 +1116,7 @@ HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *i
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ECCMul_Set(hpka, in);
|
||||
|
||||
modulussize = in->modulusSize;
|
||||
|
||||
/* Start the operation */
|
||||
return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
|
||||
}
|
||||
|
|
@ -1145,9 +1131,37 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef
|
|||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ECCMul_Set(hpka, in);
|
||||
|
||||
modulussize = in->modulusSize;
|
||||
/* Start the operation */
|
||||
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
|
||||
}
|
||||
/**
|
||||
* @brief ECC scalar multiplication extended in blocking mode.
|
||||
* @param hpka PKA handle
|
||||
* @param in Input information
|
||||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout)
|
||||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ECCMulEx_Set(hpka, in);
|
||||
modulussize = in->modulusSize;
|
||||
/* Start the operation */
|
||||
return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ECC scalar multiplication extended in non-blocking mode with Interrupt.
|
||||
* @param hpka PKA handle
|
||||
* @param in Input information
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in)
|
||||
{
|
||||
/* Set input parameter in PKA RAM */
|
||||
PKA_ECCMulEx_Set(hpka, in);
|
||||
modulussize = in->modulusSize;
|
||||
/* Start the operation */
|
||||
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
|
||||
}
|
||||
|
|
@ -1704,13 +1718,11 @@ void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
|
|||
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
|
||||
{
|
||||
uint32_t mode = PKA_GetMode(hpka);
|
||||
FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR);
|
||||
FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR);
|
||||
FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND);
|
||||
FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR);
|
||||
uint32_t itsource = READ_REG(hpka->Instance->CR);
|
||||
uint32_t flag = READ_REG(hpka->Instance->SR);
|
||||
|
||||
/* Address error interrupt occurred */
|
||||
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET))
|
||||
if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR))
|
||||
{
|
||||
hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
|
||||
|
||||
|
|
@ -1719,7 +1731,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
|
|||
}
|
||||
|
||||
/* RAM access error interrupt occurred */
|
||||
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET))
|
||||
if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR))
|
||||
{
|
||||
hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
|
||||
|
||||
|
|
@ -1728,7 +1740,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
|
|||
}
|
||||
|
||||
/* OPERATION access error interrupt occurred */
|
||||
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET))
|
||||
if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR))
|
||||
{
|
||||
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
|
||||
|
||||
|
|
@ -1792,7 +1804,7 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
|
|||
}
|
||||
|
||||
/* End Of Operation interrupt occurred */
|
||||
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET))
|
||||
if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND))
|
||||
{
|
||||
/* Clear PROCEND flag */
|
||||
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
|
||||
|
|
@ -2591,7 +2603,50 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
|
|||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL));
|
||||
}
|
||||
/**
|
||||
* @brief Set input parameters.
|
||||
* @param hpka PKA handle
|
||||
* @param in Input information
|
||||
*/
|
||||
void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in)
|
||||
{
|
||||
/* Get the prime order n length */
|
||||
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
|
||||
|
||||
/* Get the modulus length */
|
||||
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
|
||||
|
||||
/* Get the coefficient a sign */
|
||||
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
|
||||
|
||||
/* Move the input parameters coefficient |a| to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
|
||||
|
||||
/* Move the input parameters coefficient b to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
|
||||
|
||||
/* Move the input parameters modulus value p to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
|
||||
|
||||
/* Move the input parameters scalar multiplier k to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
|
||||
|
||||
/* Move the input parameters Point P coordinate x to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
|
||||
|
||||
/* Move the input parameters Point P coordinate y to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
|
||||
|
||||
/* Move the input parameters curve prime order N to PKA RAM */
|
||||
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
|
||||
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set input parameters.
|
||||
|
|
|
|||
|
|
@ -147,6 +147,21 @@ typedef struct
|
|||
const uint8_t *primeOrder; /*!< pointer to order of the curve */
|
||||
} PKA_ECCMulInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *coefB; /*!< pointer to curve coefficient b */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
||||
const uint8_t *primeOrder; /*!< pointer to order of the curve */
|
||||
} PKA_ECCMulExInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
|
||||
|
|
@ -572,6 +587,8 @@ uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
|
|||
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in);
|
||||
void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
|
||||
|
|
|
|||
|
|
@ -53,7 +53,6 @@
|
|||
(#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
|
||||
(GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
|
||||
|
||||
|
||||
(#) For PSSI IO operations, two operation modes are available within this driver :
|
||||
|
||||
*** Polling mode IO operation ***
|
||||
|
|
@ -166,7 +165,6 @@
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -651,8 +649,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
|
|||
HAL_PSSI_DISABLE(hpssi);
|
||||
|
||||
/* Configure transfer parameters */
|
||||
hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
|
||||
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL);
|
||||
MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
|
||||
(PSSI_CR_OUTEN_OUTPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)));
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
/* DMA Disable */
|
||||
|
|
@ -804,8 +802,8 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
|
|||
/* Disable the selected PSSI peripheral */
|
||||
HAL_PSSI_DISABLE(hpssi);
|
||||
/* Configure transfer parameters */
|
||||
hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |
|
||||
((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL);
|
||||
MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
|
||||
(PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL)));
|
||||
|
||||
#if defined(HAL_DMA_MODULE_ENABLED)
|
||||
/* DMA Disable */
|
||||
|
|
@ -1122,7 +1120,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
|
|||
if (hpssi->hdmarx != NULL)
|
||||
{
|
||||
/* Configure BusWidth */
|
||||
if (hpssi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)
|
||||
if (hpssi->hdmarx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)
|
||||
{
|
||||
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
|
||||
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
|
||||
|
|
|
|||
|
|
@ -53,12 +53,18 @@ extern "C" {
|
|||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
|
||||
uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
|
||||
uint32_t ControlSignal; /* !< Configures Data enable and Data ready */
|
||||
uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */
|
||||
uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
|
||||
uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */
|
||||
uint32_t DataWidth; /* !< Configures the data width.
|
||||
This parameter can be a value of @ref PSSI_DATA_WIDTH. */
|
||||
uint32_t BusWidth; /* !< Configures the parallel bus width.
|
||||
This parameter can be a value of @ref PSSI_BUS_WIDTH. */
|
||||
uint32_t ControlSignal; /* !< Configures Data enable and Data ready.
|
||||
This parameter can be a value of @ref ControlSignal_Configuration. */
|
||||
uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity.
|
||||
This parameter can be a value of @ref Clock_Polarity. */
|
||||
uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity.
|
||||
This parameter can be a value of @ref Data_Enable_Polarity. */
|
||||
uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity.
|
||||
This parameter can be a value of @ref Ready_Polarity. */
|
||||
|
||||
} PSSI_InitTypeDef;
|
||||
|
||||
|
|
@ -216,7 +222,7 @@ typedef enum
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Reday_Polarity Reday Polarity
|
||||
/** @defgroup Ready_Polarity Ready Polarity
|
||||
* @{
|
||||
*/
|
||||
#define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */
|
||||
|
|
@ -230,8 +236,6 @@ typedef enum
|
|||
*/
|
||||
#define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */
|
||||
#define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -257,7 +261,6 @@ typedef enum
|
|||
#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -274,7 +277,6 @@ typedef enum
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -325,7 +327,6 @@ typedef enum
|
|||
#define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
|
||||
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the PSSI pending flags.
|
||||
|
|
@ -394,7 +395,6 @@ typedef enum
|
|||
((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE ))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the PSSI Bus Width is valid.
|
||||
* @param __BUSWIDTH__ PSSI Bush width
|
||||
|
|
@ -432,6 +432,7 @@ typedef enum
|
|||
|
||||
#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \
|
||||
((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH ))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -486,7 +487,7 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
|
|||
|
||||
/* Peripheral State functions ***************************************************/
|
||||
HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi);
|
||||
uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi);
|
||||
uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -507,7 +508,6 @@ void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
|
|||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -392,10 +392,11 @@ void HAL_PWR_EnterSTANDBYMode(void)
|
|||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif /* __CC_ARM */
|
||||
/* Wait For all memory accesses to complete before continuing */
|
||||
__DSB();
|
||||
|
||||
/* Ensure that the processor pipeline is flushed */
|
||||
__ISB();
|
||||
|
||||
/* Wait For Interrupt Request */
|
||||
__WFI();
|
||||
|
|
|
|||
|
|
@ -672,13 +672,23 @@ void HAL_PWREx_DisableFlashPowerDown(void)
|
|||
* content. The user can select which memory is discarded during STOP
|
||||
* mode by means of xxSO bits.
|
||||
* @param MemoryBlock : Specifies the memory block to shut-off during Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode
|
||||
* @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* @note The PWR_ETHERNET_MEMORY_BLOCK is not available for STM32H503xx devices.
|
||||
* This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx :
|
||||
* @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode
|
||||
* @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* This parameter can be one of the following values for STM32H533xx/STM32H523xx :
|
||||
* @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control
|
||||
* in Stop mode
|
||||
* @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control
|
||||
* in Stop mode
|
||||
* @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* This parameter can be one of the following values for STM32H503xx :
|
||||
* @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock)
|
||||
|
|
@ -694,13 +704,23 @@ void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock)
|
|||
* @brief Disable memory block shut-off in Stop mode
|
||||
* @param MemoryBlock : Specifies the memory block to keep content during
|
||||
* Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode
|
||||
* @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* @note The PWR_ETHERNET_MEMORY_BLOCK is not available for STM32H503xx devices.
|
||||
* This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx :
|
||||
* @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode
|
||||
* @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* This parameter can be one of the following values for STM32H533xx/STM32H523xx :
|
||||
* @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
|
||||
* @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control
|
||||
* in Stop mode
|
||||
* @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control
|
||||
* in Stop mode
|
||||
* @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* This parameter can be one of the following values for STM32H503xx :
|
||||
* @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode
|
||||
* @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock)
|
||||
|
|
|
|||
|
|
@ -181,15 +181,23 @@ typedef struct
|
|||
/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO /*!< RAM1 shut-off control in Stop mode */
|
||||
#if defined (PWR_PMCR_SRAM2_16SO)
|
||||
#define PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO /*!< Ethernet shut-off control in Stop mode */
|
||||
#define PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO /*!< RAM3 shut-off control in Stop mode */
|
||||
#define PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO /*!< RAM2 16k byte shut-off control in Stop mode */
|
||||
#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */
|
||||
#define PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO /*!< RAM2 16k byte shut-off control in Stop mode */
|
||||
#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */
|
||||
#elif defined (PWR_PMCR_SRAM2_16LSO)
|
||||
#define PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO /*!< RAM2 low 16k byte shut-off control in Stop mode */
|
||||
#define PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO /*!< RAM2 High 16k byte shut-off control in Stop mode */
|
||||
#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */
|
||||
#else
|
||||
#define PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO /*!< RAM2 48k byte shut-off control in Stop mode */
|
||||
#define PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO /*!< RAM2 shut-off control in Stop mode */
|
||||
#endif /* PWR_PMCR_SRAM2_16SO */
|
||||
#define PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO /*!< RAM1 shut-off control in Stop mode */
|
||||
#if defined (PWR_PMCR_SRAM3SO)
|
||||
#define PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO /*!< RAM3 shut-off control in Stop mode */
|
||||
#endif /* PWR_PMCR_SRAM3SO */
|
||||
#if defined (PWR_PMCR_ETHERNETSO)
|
||||
#define PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO /*!< Ethernet shut-off control in Stop mode */
|
||||
#endif /* PWR_PMCR_ETHERNETSO */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -413,13 +421,19 @@ typedef struct
|
|||
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
|
||||
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
|
||||
|
||||
#if defined (PWR_PMCR_SRAM2_16SO)
|
||||
/* Check memory block parameter */
|
||||
#if defined (PWR_PMCR_SRAM2_16SO)
|
||||
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_ETHERNET_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM2_16_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM1_MEMORY_BLOCK))
|
||||
#elif defined (PWR_PMCR_SRAM2_16LSO)
|
||||
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM1_MEMORY_BLOCK))
|
||||
#else
|
||||
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM2_MEMORY_BLOCK) || \
|
||||
((BLOCK) == PWR_RAM1_MEMORY_BLOCK))
|
||||
|
|
|
|||
|
|
@ -1,13 +1,12 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h5xx_hal_ramcfg.c
|
||||
* @author MCD Application Team
|
||||
* @author GPM Application Team
|
||||
* @brief RAMCFG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the RAMs configuration controller peripheral:
|
||||
* + RAMCFG Initialization and De-initialization Functions.
|
||||
* + RAMCFG ECC Operation Functions.
|
||||
* + RAMCFG Configure Wait State Functions.
|
||||
* + RAMCFG Write Protection Functions.
|
||||
* + RAMCFG Erase Operation Functions.
|
||||
* + RAMCFG Handle Interrupt and Callbacks Functions.
|
||||
|
|
@ -76,8 +75,11 @@
|
|||
call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the
|
||||
last fail RAM word detected (only for double error).
|
||||
|
||||
(+) Call HAL_RAMCFG_IsECCErrorDetected() to check if an ECC single/double
|
||||
error was detected. This API is used in silent mode (No ECC interrupt
|
||||
(+) Call HAL_RAMCFG_IsECCSingleErrorDetected() to check if an ECC single
|
||||
error was detected.
|
||||
Call HAL_RAMCFG_IsECCDoubleErrorDetected() to check if an ECC double
|
||||
error was detected.
|
||||
These APIs are used in silent mode (No ECC interrupt
|
||||
is enabled).
|
||||
|
||||
*** Write protection feature ***
|
||||
|
|
@ -217,7 +219,7 @@ HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg)
|
|||
/* Clear RAMCFG monitor flags */
|
||||
__HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
|
||||
|
||||
/* Initialise the RAMCFG error code */
|
||||
/* Initialize the RAMCFG error code */
|
||||
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
|
||||
|
||||
/* Initialize the RAMCFG state */
|
||||
|
|
@ -329,8 +331,10 @@ __weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg)
|
|||
The HAL_RAMCFG_DisableNotification() function allows disabling interrupts
|
||||
for single ECC error, double ECC error. When NMI interrupt is enabled it
|
||||
can only be disabled by a global peripheral reset or by a system reset.
|
||||
The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error
|
||||
has occurred.
|
||||
The HAL_RAMCFG_IsECCSingleErrorDetected() function allows to check if an
|
||||
single ECC error has occurred.
|
||||
The HAL_RAMCFG_IsECCDoubleErrorDetected() function allows to check if an
|
||||
double ECC error has occurred.
|
||||
The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of
|
||||
the last single ECC error detected.
|
||||
The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of
|
||||
|
|
@ -364,10 +368,15 @@ HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg)
|
|||
{
|
||||
/* Start the SRAM ECC mechanism and latching the error address */
|
||||
hramcfg->Instance->CR |= (RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
|
||||
|
||||
/* Update the RAMCFG state */
|
||||
hramcfg->State = HAL_RAMCFG_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Start latching the error address */
|
||||
hramcfg->Instance->CR |= RAMCFG_CR_ALE;
|
||||
}
|
||||
|
||||
/* Update the RAMCFG state */
|
||||
hramcfg->State = HAL_RAMCFG_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -407,10 +416,9 @@ HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg)
|
|||
|
||||
/* Stop the SRAM ECC mechanism and latching the error address */
|
||||
hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
|
||||
|
||||
/* Update the RAMCFG state */
|
||||
hramcfg->State = HAL_RAMCFG_STATE_READY;
|
||||
}
|
||||
/* Update the RAMCFG state */
|
||||
hramcfg->State = HAL_RAMCFG_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -530,7 +538,7 @@ uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(const RAMCFG_HandleTypeDef *hramcfg
|
|||
/* Check the parameters */
|
||||
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
|
||||
|
||||
/* Return the state of DEDC flag */
|
||||
/* Return the state of DED flag */
|
||||
return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_DOUBLEERR) == (RAMCFG_FLAG_DOUBLEERR)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
|
@ -563,6 +571,7 @@ uint32_t HAL_RAMCFG_GetDoubleErrorAddress(const RAMCFG_HandleTypeDef *hramcfg)
|
|||
|
||||
return hramcfg->Instance->DEAR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -602,6 +611,9 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg
|
|||
uint32_t page_mask_0 = 0U;
|
||||
uint32_t page_mask_1 = 0U;
|
||||
|
||||
#if defined (RAMCFG_WPR3_P64WP)
|
||||
uint32_t page_mask_2 = 0U;
|
||||
#endif /* RAMCFG_WPR3_P64WP */
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance));
|
||||
assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage));
|
||||
|
|
@ -612,6 +624,29 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg
|
|||
/* Update RAMCFG peripheral state */
|
||||
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
|
||||
|
||||
#if defined (RAMCFG_WPR3_P64WP)
|
||||
/* Repeat for page number to be protected */
|
||||
for (uint32_t count = 0U; count < NbPage; count++)
|
||||
{
|
||||
if ((StartPage + count) < 32U)
|
||||
{
|
||||
page_mask_0 |= (1UL << (StartPage + count));
|
||||
}
|
||||
else if ((StartPage + count) < 64U)
|
||||
{
|
||||
page_mask_1 |= (1UL << ((StartPage + count) - 32U));
|
||||
}
|
||||
else
|
||||
{
|
||||
page_mask_2 |= (1UL << ((StartPage + count) - 64U));
|
||||
}
|
||||
}
|
||||
|
||||
/* Apply mask to protect pages */
|
||||
SET_BIT(hramcfg->Instance->WPR1, page_mask_0);
|
||||
SET_BIT(hramcfg->Instance->WPR2, page_mask_1);
|
||||
SET_BIT(hramcfg->Instance->WPR3, page_mask_2);
|
||||
#else
|
||||
/* Repeat for page number to be protected */
|
||||
for (uint32_t count = 0U; count < NbPage; count++)
|
||||
{
|
||||
|
|
@ -628,7 +663,7 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg
|
|||
/* Apply mask to protect pages */
|
||||
SET_BIT(hramcfg->Instance->WPR1, page_mask_0);
|
||||
SET_BIT(hramcfg->Instance->WPR2, page_mask_1);
|
||||
|
||||
#endif /* RAMCFG_WPR3_P64WP */
|
||||
/* Update the RAMCFG state */
|
||||
hramcfg->State = HAL_RAMCFG_STATE_READY;
|
||||
}
|
||||
|
|
@ -641,6 +676,7 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg
|
|||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -718,6 +754,7 @@ HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg)
|
|||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1009,6 +1046,7 @@ HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, H
|
|||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1022,7 +1060,7 @@ HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, H
|
|||
===============================================================================
|
||||
[..]
|
||||
This section provides functions to check and get the RAMCFG state
|
||||
and the error code.
|
||||
and the error code.
|
||||
[..]
|
||||
The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral
|
||||
state.
|
||||
|
|
@ -1064,6 +1102,7 @@ uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg)
|
|||
/* Return the RAMCFG error code */
|
||||
return hramcfg->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -152,8 +152,6 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -254,7 +252,6 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions
|
||||
|
|
@ -335,6 +332,7 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg)
|
|||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -361,7 +359,11 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg)
|
|||
(((INTERRUPT) != 0U) && (((INTERRUPT) & ~(RAMCFG_IT_SINGLEERR | RAMCFG_IT_DOUBLEERR | RAMCFG_IT_NMIERR)) == 0U))
|
||||
|
||||
|
||||
#if defined (RAMCFG_WPR3_P64WP)
|
||||
#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 80U)
|
||||
#else
|
||||
#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U)
|
||||
#endif /* RAMCFG_WPR3_P64WP*/
|
||||
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -1697,11 +1697,11 @@ void HAL_RCC_NMI_IRQHandler(void)
|
|||
/* Check RCC CSSF interrupt flag */
|
||||
if (__HAL_RCC_GET_IT(RCC_IT_HSECSS))
|
||||
{
|
||||
/* RCC Clock Security System interrupt user callback */
|
||||
HAL_RCC_CSSCallback();
|
||||
|
||||
/* Clear RCC CSS pending bit */
|
||||
__HAL_RCC_CLEAR_IT(RCC_IT_HSECSS);
|
||||
|
||||
/* RCC Clock Security System interrupt user callback */
|
||||
HAL_RCC_CSSCallback();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -114,7 +114,6 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3);
|
|||
* @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
|
||||
* @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
|
||||
* @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***)
|
||||
* @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
|
||||
|
|
@ -1147,14 +1146,20 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe
|
|||
|
||||
switch (pPeriphClkInit->I3c2ClockSelection)
|
||||
{
|
||||
case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK1 is used as clock source for I3C2*/
|
||||
case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I3C2*/
|
||||
|
||||
/* I3C2 clock source config set later after clock selection check */
|
||||
break;
|
||||
|
||||
#if defined(RCC_I3C2CLKSOURCE_PLL3R)
|
||||
case RCC_I3C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C2*/
|
||||
/* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
|
||||
ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
|
||||
#else
|
||||
case RCC_I3C2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C2*/
|
||||
/* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
|
||||
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
|
||||
#endif /* RCC_I3C2CLKSOURCE_PLL3R */
|
||||
/* I3C2 clock source config set later after clock selection check */
|
||||
break;
|
||||
|
||||
|
|
@ -1166,7 +1171,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe
|
|||
ret = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret == HAL_OK)
|
||||
{
|
||||
/* Set the source of I3C2 clock*/
|
||||
|
|
@ -2367,6 +2371,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
/*------------------------------ USB Configuration -------------------------*/
|
||||
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
||||
{
|
||||
|
|
@ -2417,6 +2422,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe
|
|||
}
|
||||
|
||||
}
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
#if defined(CEC)
|
||||
/*-------------------------- CEC clock source configuration ----------------*/
|
||||
|
|
@ -2435,8 +2441,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the pPeriphClkInit according to the internal RCC configuration registers.
|
||||
* @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
|
|
@ -2444,7 +2448,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPe
|
|||
* clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6,
|
||||
* SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8,
|
||||
* UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1,
|
||||
* SAI2, USB,), PLL2 and PLL3.
|
||||
* SAI2, USB, PLAY1), PLL2 and PLL3.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
|
||||
|
|
@ -2455,8 +2459,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
|
|||
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \
|
||||
RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \
|
||||
RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
|
||||
RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_USB;
|
||||
RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER;
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
|
||||
#endif /* USB_DRD_FS */
|
||||
#if defined(UART4)
|
||||
pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART4;
|
||||
#endif /* UART4 */
|
||||
|
|
@ -2737,8 +2744,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
|
|||
pPeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
|
||||
#endif /* CEC */
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
/* Get the USB clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
/* Get the TIM Prescaler configuration -------------------------------------*/
|
||||
if ((RCC->CFGR1 & RCC_CFGR1_TIMPRE) == 0U)
|
||||
|
|
@ -2749,6 +2758,61 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
|
|||
{
|
||||
pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED;
|
||||
}
|
||||
|
||||
#if defined(PLAY1)
|
||||
/* Get the PLAY1 clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->PLAY1ClockSelection = __HAL_RCC_GET_PLAY1_SOURCE();
|
||||
#endif /* PLAY1 */
|
||||
|
||||
#if defined(USB_OTG_FS)
|
||||
/* Get the USB_OTG_FS clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->OtgfsClockSelection = __HAL_RCC_GET_OTGFS_SOURCE();
|
||||
#endif /* USB_OTG_FS */
|
||||
|
||||
#if defined(USB_OTG_HS)
|
||||
/* Get the USB_OTG_HS clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->OtghsClockSelection = __HAL_RCC_GET_OTGHS_SOURCE();
|
||||
#endif /* USB_OTG_HS */
|
||||
|
||||
#if defined(OCTOSPI2)
|
||||
/* Get the OSPI2 clock source -----------------------------------------------*/
|
||||
pPeriphClkInit->Ospi2ClockSelection = __HAL_RCC_GET_OSPI2_SOURCE();
|
||||
#endif /* OCTOSPI2 */
|
||||
|
||||
#if defined(LTDC)
|
||||
/* Get the LTDC clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
|
||||
#endif /* LTDC */
|
||||
|
||||
#if defined(ADF1)
|
||||
/* Get the ADF1 clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
|
||||
#endif /* ADF1 */
|
||||
|
||||
#if defined(MDF1)
|
||||
/* Get the MDF1 clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE();
|
||||
#endif /* MDF1 */
|
||||
|
||||
#if defined(RCC_CCIPR4_ETHCLKSEL)
|
||||
/* Get the ETH clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE();
|
||||
#endif /* RCC_CCIPR4_ETHCLKSEL */
|
||||
|
||||
#if defined(RCC_CCIPR5_ETHPTPCLKSEL)
|
||||
/* Get the ETHPTP clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->EthptpClockSelection = __HAL_RCC_GET_ETHPTP_SOURCE();
|
||||
#endif /* RCC_CCIPR5_ETHPTPCLKSEL */
|
||||
|
||||
#if defined(RCC_CCIPR5_ETHT1SCLKSEL)
|
||||
/* Get the ETHT1S clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->Etht1sClockSelection = __HAL_RCC_GET_ETHT1S_SOURCE();
|
||||
#endif /* RCC_CCIPR5_ETHT1SCLKSEL */
|
||||
|
||||
#if defined(RCC_CCIPR5_ETHREFCLKSEL)
|
||||
/* Get the ETHREF clock source ------------------------------------------------*/
|
||||
pPeriphClkInit->EthrefClockSelection = __HAL_RCC_GET_ETHREF_SOURCE();
|
||||
#endif /* RCC_CCIPR5_ETHREFCLKSEL */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -3179,7 +3243,6 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks)
|
|||
* @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
|
||||
* @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
|
||||
* @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***)
|
||||
* @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
|
||||
|
|
@ -4180,20 +4243,33 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
|
|||
case RCC_PERIPHCLK_I3C2:
|
||||
/* Get the current I3C2 source */
|
||||
srcclk = __HAL_RCC_GET_I3C2_SOURCE();
|
||||
|
||||
if (srcclk == RCC_I3C2CLKSOURCE_PCLK3)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK3Freq();
|
||||
}
|
||||
#if defined(RCC_I3C1CLKSOURCE_PLL3R)
|
||||
else if (srcclk == RCC_I3C2CLKSOURCE_PLL3R)
|
||||
{
|
||||
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
|
||||
frequency = pll3_clocks.PLL3_R_Frequency;
|
||||
}
|
||||
#else
|
||||
else if (srcclk == RCC_I3C2CLKSOURCE_PLL2R)
|
||||
{
|
||||
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
|
||||
frequency = pll2_clocks.PLL2_R_Frequency;
|
||||
}
|
||||
#endif /* RCC_I3C1CLKSOURCE_PLL3R */
|
||||
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_HSI))
|
||||
{
|
||||
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
|
||||
}
|
||||
#if defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx)
|
||||
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_CSI))
|
||||
{
|
||||
frequency = CSI_VALUE;
|
||||
}
|
||||
#endif /* defined(STM32H5E5xx) || defined(STM32H5E4xx) || defined(STM32H5F5xx) || defined(STM32H5F4xx) */
|
||||
/* Clock not enabled for I3C2 */
|
||||
else
|
||||
{
|
||||
|
|
@ -5191,6 +5267,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
|
|||
}
|
||||
break;
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
case RCC_PERIPHCLK_USB:
|
||||
/* Get the current USB kernel source */
|
||||
srcclk = __HAL_RCC_GET_USB_SOURCE();
|
||||
|
|
@ -5230,9 +5307,36 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
|
|||
default:
|
||||
frequency = 0U;
|
||||
break;
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
#if defined(RCC_CCIPR4_ETHCLKSEL)
|
||||
case RCC_PERIPHCLK_ETH:
|
||||
|
||||
/* Get the current ETH kernel source */
|
||||
srcclk = __HAL_RCC_GET_ETH_SOURCE();
|
||||
switch (srcclk)
|
||||
{
|
||||
case RCC_ETHCLKSOURCE_PLL1Q:
|
||||
{
|
||||
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
|
||||
frequency = pll1_clocks.PLL1_Q_Frequency;
|
||||
break;
|
||||
}
|
||||
case RCC_ETHCLKSOURCE_HSE:
|
||||
{
|
||||
frequency = HSE_VALUE;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
frequency = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
#endif /* RCC_CCIPR4_ETHCLKSEL */
|
||||
}
|
||||
}
|
||||
|
||||
return (frequency);
|
||||
}
|
||||
|
||||
|
|
@ -6269,5 +6373,3 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3)
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -346,12 +346,13 @@ typedef struct
|
|||
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
|
||||
#endif /* CEC */
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
uint32_t UsbClockSelection; /*!< Specifies USB clock source.
|
||||
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
uint32_t TimPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
|
||||
This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
|
||||
|
||||
} RCC_PeriphCLKInitTypeDef;
|
||||
|
||||
#if defined(CRS)
|
||||
|
|
@ -507,7 +508,9 @@ typedef struct
|
|||
#if defined(CEC)
|
||||
#define RCC_PERIPHCLK_CEC ((uint64_t)0x800000000U)
|
||||
#endif /* CEC */
|
||||
#if defined(USB_DRD_FS)
|
||||
#define RCC_PERIPHCLK_USB ((uint64_t)0x1000000000U)
|
||||
#endif /* USB_DRD_FS */
|
||||
#if defined(LPTIM3)
|
||||
#define RCC_PERIPHCLK_LPTIM3 ((uint64_t)0x2000000000U)
|
||||
#endif /* LPTIM3 */
|
||||
|
|
@ -528,7 +531,6 @@ typedef struct
|
|||
#if defined(I3C2)
|
||||
#define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U)
|
||||
#endif /* I3C2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -892,7 +894,11 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define RCC_I3C2CLKSOURCE_PCLK3 ((uint32_t)0x00000000U)
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
#define RCC_I3C2CLKSOURCE_PLL3R RCC_CCIPR4_I3C2SEL_0
|
||||
#else
|
||||
#define RCC_I3C2CLKSOURCE_PLL2R RCC_CCIPR4_I3C2SEL_0
|
||||
#endif /* RCC_CR_PLL3ON */
|
||||
#define RCC_I3C2CLKSOURCE_HSI RCC_CCIPR4_I3C2SEL_1
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1205,6 +1211,7 @@ typedef struct
|
|||
*/
|
||||
#endif /* CEC */
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1218,6 +1225,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
|
||||
* @{
|
||||
|
|
@ -2357,9 +2365,13 @@ typedef struct
|
|||
* @param __I3C2_CLKSOURCE__ specifies the I3C2 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*)
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock
|
||||
*
|
||||
* @retval None
|
||||
*
|
||||
* (*) : Not available for all stm32h5xxxx family lines.
|
||||
*/
|
||||
#define __HAL_RCC_I3C2_CONFIG(__I3C2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL, (uint32_t)(__I3C2_CLKSOURCE__))
|
||||
|
|
@ -2367,8 +2379,11 @@ typedef struct
|
|||
/** @brief Macro to get the I3C2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_PCLK3 PCLK3 selected as I3C2 clock
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_PLL3R PLL3R selected as I3C2 clock (*)
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_PLL2R PLL2R selected as I3C2 clock
|
||||
* @arg @ref RCC_I3C2CLKSOURCE_HSI HSI selected as I3C2 clock
|
||||
*
|
||||
* (*) : Not available for all stm32h5xxxx family lines.
|
||||
*/
|
||||
#define __HAL_RCC_GET_I3C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_I3C2SEL)))
|
||||
#endif /* I3C2 */
|
||||
|
|
@ -2917,6 +2932,7 @@ typedef struct
|
|||
#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR5, RCC_CCIPR5_CECSEL)))
|
||||
#endif /* CEC */
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
/** @brief Macro to configure the USB clock (USBCLK).
|
||||
* @param __USBCLKSource__ specifies the USB clock source.
|
||||
* This parameter can be one of the following values:
|
||||
|
|
@ -2942,6 +2958,7 @@ typedef struct
|
|||
* (**) : For stm32h503xx family line.
|
||||
*/
|
||||
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_USBSEL)))
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
/** @brief Macro to configure the Timers clocks prescalers
|
||||
* @param __PRESC__ specifies the Timers clocks prescalers selection
|
||||
|
|
@ -3137,11 +3154,11 @@ typedef struct
|
|||
RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
|
||||
RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \
|
||||
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | \
|
||||
RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
|
||||
RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
|
||||
RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | \
|
||||
RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | \
|
||||
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER)
|
||||
#elif defined(RCC_CR_PLL3ON)
|
||||
#elif defined(UART7)
|
||||
#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
|
||||
RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
|
||||
RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_UART9 | \
|
||||
|
|
@ -3152,9 +3169,20 @@ typedef struct
|
|||
RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | \
|
||||
RCC_PERIPHCLK_LPTIM6 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
|
||||
RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \
|
||||
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_I3C1 | \
|
||||
RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
|
||||
RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \
|
||||
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \
|
||||
RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \
|
||||
RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_OSPI | \
|
||||
RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USB | \
|
||||
RCC_PERIPHCLK_CKPER)
|
||||
#elif defined(USART6)
|
||||
#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
|
||||
RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
|
||||
RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
|
||||
RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | \
|
||||
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
|
||||
RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | \
|
||||
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1 | \
|
||||
RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 | \
|
||||
RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_CEC | \
|
||||
RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER)
|
||||
#else
|
||||
|
|
@ -3163,9 +3191,8 @@ typedef struct
|
|||
RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | RCC_PERIPHCLK_TIM | \
|
||||
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \
|
||||
RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC | \
|
||||
RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
|
||||
RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | \
|
||||
RCC_PERIPHCLK_CKPER)
|
||||
RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
|
||||
RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_CKPER)
|
||||
#endif /*FDCAN2 && SDMMC2 */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -3448,10 +3475,17 @@ typedef struct
|
|||
#endif /* RCC_CR_PLL3ON */
|
||||
|
||||
#if defined(I3C2)
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \
|
||||
((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \
|
||||
((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL3R) || \
|
||||
((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI))
|
||||
#else
|
||||
#define IS_RCC_I3C2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I3C2CLKSOURCE_PCLK3) || \
|
||||
((__SOURCE__) == RCC_I3C2CLKSOURCE_PLL2R) || \
|
||||
((__SOURCE__) == RCC_I3C2CLKSOURCE_HSI))
|
||||
#endif /* PLL3 */
|
||||
#endif /* I3C2 */
|
||||
|
||||
#if defined(SAI1)
|
||||
|
|
@ -3664,6 +3698,7 @@ typedef struct
|
|||
((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
|
||||
#endif /* SPI6 */
|
||||
|
||||
#if defined(USB_DRD_FS)
|
||||
#if defined(RCC_CR_PLL3ON)
|
||||
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USBCLKSOURCE_PLL1Q) || \
|
||||
|
|
@ -3675,6 +3710,7 @@ typedef struct
|
|||
((__SOURCE__) == RCC_USBCLKSOURCE_PLL2Q) || \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_HSI48))
|
||||
#endif /* RCC_CR_PLL3ON */
|
||||
#endif /* USB_DRD_FS */
|
||||
|
||||
#if defined(CEC)
|
||||
#define IS_RCC_CECCLKSOURCE(__SOURCE__) \
|
||||
|
|
|
|||
|
|
@ -199,6 +199,17 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
|||
|
||||
/* Clock Error Detection Configuration when CONDRT bit is set to 1 */
|
||||
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
|
||||
#if defined(RNG_CR_NIST_VALUE)
|
||||
/* Recommended value for NIST compliance, refer to application note AN4230 */
|
||||
WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE);
|
||||
#endif /* defined(RNG_CR_NIST_VALUE) */
|
||||
#if defined(RNG_HTCR_NIST_VALUE)
|
||||
/* Recommended value for NIST compliance, refer to application note AN4230 */
|
||||
WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE);
|
||||
#endif /* defined(RNG_HTCR_NIST_VALUE) */
|
||||
#if defined(RNG_NSCR_NIST_VALUE)
|
||||
WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE);
|
||||
#endif /* defined(RNG_NSCR_NIST_VALUE) */
|
||||
|
||||
/* Writing bit CONDRST=0 */
|
||||
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
|
||||
|
|
@ -233,12 +244,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
|||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
/* Check if data register contains valid random data */
|
||||
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
|
||||
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
|
||||
if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET)
|
||||
{
|
||||
hrng->State = HAL_RNG_STATE_ERROR;
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
|
||||
|
|
@ -674,8 +685,6 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
|
|||
/* Update the error code and status */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
|
||||
status = HAL_ERROR;
|
||||
/* Clear bit DRDY */
|
||||
CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
|
||||
}
|
||||
else /* No seed error */
|
||||
{
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
#if defined(RNG)
|
||||
|
||||
/** @addtogroup RNG_Ex
|
||||
/** @addtogroup RNGEx
|
||||
* @brief RNG Extended HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
/* Private defines -----------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup RNG_Ex_Private_Constants
|
||||
/** @addtogroup RNGEx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define RNG_TIMEOUT_VALUE 2U
|
||||
|
|
@ -53,11 +53,11 @@
|
|||
/* Private functions --------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
|
||||
/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions
|
||||
/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
|
@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function
|
||||
/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function
|
||||
* @brief Recover from seed error function
|
||||
*
|
||||
@verbatim
|
||||
|
|
|
|||
|
|
@ -34,19 +34,19 @@ extern "C" {
|
|||
#if defined(RNG)
|
||||
#if defined(RNG_CR_CONDRST)
|
||||
|
||||
/** @defgroup RNG_Ex RNG_Ex
|
||||
/** @defgroup RNGEx RNGEx
|
||||
* @brief RNG Extension HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
|
||||
* @brief RNG_Ex Exported types
|
||||
/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
|
||||
* @brief RNGEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RNG_Ex Configuration Structure definition
|
||||
* @brief RNGEx Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
|
|
@ -55,11 +55,11 @@ typedef struct
|
|||
uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */
|
||||
uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */
|
||||
uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can
|
||||
be a value of @ref RNG_Ex_Clock_Divider_Factor */
|
||||
be a value of @ref RNGEx_Clock_Divider_Factor */
|
||||
uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a
|
||||
value of @ref RNG_Ex_NIST_Compliance */
|
||||
value of @ref RNGEx_NIST_Compliance */
|
||||
uint32_t AutoReset; /*!< automatic reset When a noise source error occurs
|
||||
value of @ref RNG_Ex_Auto_Reset */
|
||||
value of @ref RNGEx_Auto_Reset */
|
||||
uint32_t HealthTest; /*!< RNG health test control must be a value
|
||||
between 0x0FFCABFF and 0x00005200 */
|
||||
} RNG_ConfigTypeDef;
|
||||
|
|
@ -69,11 +69,11 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
|
||||
/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal
|
||||
/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal
|
||||
* programmable divider acting on the incoming RNG clock
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -112,7 +112,7 @@ typedef struct
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration
|
||||
/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration
|
||||
* @{
|
||||
*/
|
||||
#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/
|
||||
|
|
@ -121,7 +121,7 @@ typedef struct
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration
|
||||
/** @defgroup RNGEx_Auto_Reset Auto Reset configuration
|
||||
* @{
|
||||
*/
|
||||
#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/
|
||||
|
|
@ -136,7 +136,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
|
||||
/** @defgroup RNGEx_Private_Types RNGEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -145,7 +145,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
|
||||
/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -154,7 +154,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
|
||||
/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -163,7 +163,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
|
||||
/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -202,7 +202,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
|
||||
/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -211,11 +211,11 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RNG_Ex_Exported_Functions
|
||||
/** @addtogroup RNGEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Ex_Exported_Functions_Group1
|
||||
/** @addtogroup RNGEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
|
||||
|
|
@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Ex_Exported_Functions_Group2
|
||||
/** @addtogroup RNGEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
|
||||
|
|
|
|||
|
|
@ -1349,14 +1349,8 @@ void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrtc);
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Set RTC_CR_BKP Bit */
|
||||
SET_BIT(RTC->CR, RTC_CR_BKP);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1369,14 +1363,8 @@ void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc)
|
|||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrtc);
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Clear RTC_CR_BKP Bit */
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_BKP);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1539,9 +1527,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
|
|||
}
|
||||
}
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Configure the Alarm register */
|
||||
if (sAlarm->Alarm == RTC_ALARM_A)
|
||||
{
|
||||
|
|
@ -1616,9 +1601,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
|
|||
SET_BIT(RTC->CR, RTC_CR_ALRBE);
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1758,9 +1740,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
|
|||
}
|
||||
}
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Configure the Alarm registers */
|
||||
if (sAlarm->Alarm == RTC_ALARM_A)
|
||||
{
|
||||
|
|
@ -1833,9 +1812,6 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
|
|||
SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE);
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1865,9 +1841,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* In case of interrupt mode is used, the interrupt source must disabled */
|
||||
if (Alarm == RTC_ALARM_A)
|
||||
{
|
||||
|
|
@ -1884,9 +1857,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
|
|||
CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR);
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
|
|||
|
|
@ -503,35 +503,22 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) for __HAL_RTC_GET_FLAG()
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flag Mask (5bits) for __HAL_RTC_GET_FLAG()
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask (5bits) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* Elements values convention: 000000XX000YYYYYb
|
||||
* - YYYYY : Interrupt flag position in the XX register (5bits)
|
||||
* - XX : Interrupt status register (2bits)
|
||||
* - 01: ICSR register
|
||||
* - 10: SR or SCR or MISR or SMISR registers
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending flag */
|
||||
#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
|
||||
#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
|
||||
#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
|
||||
#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
|
||||
#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
|
||||
#define RTC_FLAG_SSRUF (0x00000200U | RTC_SR_SSRUF_Pos) /*!< Clear SSR underflow flag */
|
||||
#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Clear Internal Time-stamp flag */
|
||||
#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Clear Time-stamp overflow flag */
|
||||
#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Clear Time-stamp flag */
|
||||
#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Clear Wakeup timer flag */
|
||||
#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Clear Alarm B flag */
|
||||
#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Clear Alarm A flag */
|
||||
#define RTC_FLAG_RECALPF (1U) /*!< Recalibration pending flag */
|
||||
#define RTC_FLAG_INITF (2U) /*!< Initialization flag */
|
||||
#define RTC_FLAG_RSF (3U) /*!< Registers synchronization flag */
|
||||
#define RTC_FLAG_INITS (4U) /*!< Initialization status flag */
|
||||
#define RTC_FLAG_SHPF (5U) /*!< Shift operation pending flag */
|
||||
#define RTC_FLAG_WUTWF (6U) /*!< Wakeup timer write flag */
|
||||
#define RTC_FLAG_SSRUF (7U) /*!< Clear SSR underflow flag */
|
||||
#define RTC_FLAG_ITSF (8U) /*!< Clear Internal Time-stamp flag */
|
||||
#define RTC_FLAG_TSOVF (9U) /*!< Clear Time-stamp overflow flag */
|
||||
#define RTC_FLAG_TSF (10U) /*!< Clear Time-stamp flag */
|
||||
#define RTC_FLAG_WUTF (11U) /*!< Clear Wakeup timer flag */
|
||||
#define RTC_FLAG_ALRBF (12U) /*!< Clear Alarm B flag */
|
||||
#define RTC_FLAG_ALRAF (13U) /*!< Clear Alarm A flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -669,7 +656,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \
|
||||
((__INTERRUPT__) == RTC_IT_ALRA) ?\
|
||||
(SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\
|
||||
((__INTERRUPT__) == RTC_IT_ALRB) ?\
|
||||
(SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\
|
||||
(0U)) /*!< Dummy action because is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
|
|
@ -680,7 +672,12 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \
|
||||
((__INTERRUPT__) == RTC_IT_ALRA) ?\
|
||||
(CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\
|
||||
((__INTERRUPT__) == RTC_IT_ALRB) ?\
|
||||
(CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\
|
||||
(0U)) /*!< Dummy action because is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
|
|
@ -689,10 +686,14 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) \
|
||||
? 1UL : 0UL)
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \
|
||||
((__INTERRUPT__) == RTC_IT_ALRA) ?\
|
||||
(READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\
|
||||
((__INTERRUPT__) == RTC_IT_ALRB) ?\
|
||||
(READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\
|
||||
(0U)) /*!< Return 0 because it is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
|
|
@ -701,10 +702,14 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) \
|
||||
? 1UL : 0UL)
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \
|
||||
((__INTERRUPT__) == RTC_IT_ALRA) ?\
|
||||
(READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\
|
||||
((__INTERRUPT__) == RTC_IT_ALRB) ?\
|
||||
(READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\
|
||||
(0U)) /*!< Return 0 because it is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarms flag status.
|
||||
|
|
@ -713,9 +718,14 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_ALRAF
|
||||
* @arg @ref RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \
|
||||
((__FLAG__) == RTC_FLAG_ALRAF) ?\
|
||||
(READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\
|
||||
((__FLAG__) == RTC_FLAG_ALRBF) ?\
|
||||
(READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\
|
||||
(0U)) /*!< Return 0 because it is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarms pending flags.
|
||||
|
|
@ -726,16 +736,19 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to
|
|||
* @arg @ref RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) \
|
||||
? ((RTC->SCR = (RTC_CLEAR_ALRAF))) :\
|
||||
(RTC->SCR = (RTC_CLEAR_ALRBF)))
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \
|
||||
((__FLAG__) == RTC_FLAG_ALRAF) ?\
|
||||
(SET_BIT(RTC->SCR, RTC_SCR_CALRAF)):\
|
||||
((__FLAG__) == RTC_FLAG_ALRBF) ?\
|
||||
(SET_BIT(RTC->SCR, RTC_SCR_CALRBF)):\
|
||||
(0U)) /*!< Dummy action because is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Check whether if the RTC Calendar is initialized.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
* @retval The state of RTC Calendar initialization (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
|
||||
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -247,9 +247,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Get the RTC_CR register and clear the bits to be configured */
|
||||
#if defined(RTC_CR_TSEDGE)
|
||||
CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE));
|
||||
|
|
@ -260,9 +257,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
|
|||
/* Configure the Time Stamp TSEDGE and Enable bits */
|
||||
SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -306,9 +300,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Get the RTC_CR register and clear the bits to be configured */
|
||||
#if defined(RTC_CR_TSEDGE)
|
||||
CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
|
||||
|
|
@ -322,9 +313,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
|
|||
/* Enable timestamp and IT */
|
||||
SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -347,9 +335,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* In case of interrupt mode is used, the interrupt source must disabled */
|
||||
#if defined(RTC_CR_TSEDGE)
|
||||
CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE));
|
||||
|
|
@ -357,9 +342,6 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
|
|||
CLEAR_BIT(RTC->CR, (RTC_CR_TSE | RTC_CR_TSIE));
|
||||
#endif /* RTC_CR_TSEDGE */
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -384,15 +366,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Configure the internal Time Stamp Enable bits */
|
||||
SET_BIT(RTC->CR, RTC_CR_ITSE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -415,15 +391,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Configure the internal Time Stamp Enable bits */
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_ITSE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
|
|
@ -619,9 +589,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Clear WUTE in RTC_CR to disable the wakeup timer */
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
|
||||
|
||||
|
|
@ -639,9 +606,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
|
|||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
|
||||
{
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
||||
|
||||
|
|
@ -667,9 +631,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
|
|||
/* Enable the Wakeup Timer */
|
||||
SET_BIT(RTC->CR, RTC_CR_WUTE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -708,9 +669,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Clear WUTE in RTC_CR to disable the wakeup timer */
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
|
||||
|
||||
|
|
@ -730,9 +688,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
|
|||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
|
||||
{
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
||||
|
||||
|
|
@ -758,9 +713,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
|
|||
/* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/
|
||||
SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE));
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -777,52 +729,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Disable the Wakeup Timer */
|
||||
/* In case of interrupt mode is used, the interrupt source must disabled */
|
||||
CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE));
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
|
||||
while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
||||
{
|
||||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
|
||||
{
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrtc);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -993,9 +909,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* check if a calibration is pending */
|
||||
|
|
@ -1006,8 +919,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo
|
|||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U)
|
||||
{
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
||||
|
|
@ -1024,6 +935,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t Smo
|
|||
}
|
||||
}
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Configure the Smooth calibration settings */
|
||||
MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM),
|
||||
(uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue));
|
||||
|
|
@ -1104,9 +1018,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until the shift is completed */
|
||||
|
|
@ -1117,9 +1028,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh
|
|||
/* New check to avoid false timeout detection in case of preemption */
|
||||
if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U)
|
||||
{
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
||||
|
||||
|
|
@ -1135,6 +1043,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t Sh
|
|||
}
|
||||
}
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
#if defined(RTC_CR_REFCKON)
|
||||
/* Check if the reference clock detection is disabled */
|
||||
if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U)
|
||||
|
|
@ -1210,18 +1121,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Configure the RTC_CR register */
|
||||
MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput);
|
||||
|
||||
/* Enable calibration output */
|
||||
SET_BIT(RTC->CR, RTC_CR_COE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1244,15 +1149,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Disable calibration output */
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_COE);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1368,15 +1267,9 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Set the BYPSHAD bit */
|
||||
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1401,15 +1294,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Reset the BYPSHAD bit */
|
||||
CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1476,15 +1363,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* Enable IT SSRU */
|
||||
__HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1507,15 +1388,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc)
|
|||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
/* In case of interrupt mode is used, the interrupt source must disabled */
|
||||
__HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
|
||||
/* Change RTC state */
|
||||
hrtc->State = HAL_RTC_STATE_READY;
|
||||
|
||||
|
|
@ -1740,13 +1615,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_T
|
|||
/* Timestamp on tamper */
|
||||
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/* Control register 1 */
|
||||
|
|
@ -1812,13 +1681,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RT
|
|||
/* Timestamp on tamper */
|
||||
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/* Interrupt enable register */
|
||||
|
|
@ -1913,13 +1776,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_
|
|||
tmp_cr = READ_REG(RTC->CR);
|
||||
if ((tmp_cr & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection))
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
tmp_cr1 = READ_REG(TAMP->CR1);
|
||||
|
|
@ -2179,13 +2036,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc,
|
|||
/* Timestamp enable on internal tamper */
|
||||
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/* No Erase Backup register enable for Internal Tamper */
|
||||
|
|
@ -2226,13 +2077,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc,
|
|||
/* Timestamp enable on internal tamper */
|
||||
if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection)
|
||||
{
|
||||
/* Disable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||
|
||||
MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection);
|
||||
|
||||
/* Enable the write protection for RTC registers */
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||
}
|
||||
|
||||
/* Interrupt enable register */
|
||||
|
|
|
|||
|
|
@ -942,11 +942,49 @@ typedef struct
|
|||
* @arg @ref RTC_FLAG_WUTF Wakeup timer flag
|
||||
* @arg @ref RTC_FLAG_ALRBF Alarm B flag
|
||||
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? \
|
||||
(RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
|
||||
(RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
|
||||
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \
|
||||
((__FLAG__) == RTC_FLAG_RECALPF) ? \
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \
|
||||
RTC_ICSR_RECALPF) : \
|
||||
((__FLAG__) == RTC_FLAG_INITF) ? \
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \
|
||||
RTC_ICSR_INITF) : \
|
||||
((__FLAG__) == RTC_FLAG_RSF) ? \
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \
|
||||
RTC_ICSR_RSF) : \
|
||||
((__FLAG__) == RTC_FLAG_INITS) ? \
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \
|
||||
RTC_ICSR_INITS) : \
|
||||
((__FLAG__) == RTC_FLAG_SHPF) ? \
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \
|
||||
RTC_ICSR_SHPF) : \
|
||||
((__FLAG__) == RTC_FLAG_WUTWF) ? \
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \
|
||||
RTC_ICSR_WUTWF) : \
|
||||
((__FLAG__) == RTC_FLAG_SSRUF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_SSRUF) == \
|
||||
RTC_SR_SSRUF) : \
|
||||
((__FLAG__) == RTC_FLAG_ITSF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_ITSF) == \
|
||||
RTC_SR_ITSF) : \
|
||||
((__FLAG__) == RTC_FLAG_TSOVF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_TSOVF) == \
|
||||
RTC_SR_TSOVF) : \
|
||||
((__FLAG__) == RTC_FLAG_TSF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_TSF) == \
|
||||
RTC_SR_TSF): \
|
||||
((__FLAG__) == RTC_FLAG_WUTF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_WUTF) == \
|
||||
RTC_SR_WUTF): \
|
||||
((__FLAG__) == RTC_FLAG_ALRBF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_ALRBF) == \
|
||||
RTC_SR_ALRBF) : \
|
||||
((__FLAG__) == RTC_FLAG_ALRAF) ? \
|
||||
(READ_BIT(RTC->SR, RTC_SR_ALRAF) == \
|
||||
RTC_SR_ALRAF) : \
|
||||
(0U)) /*!< Return 0 because it is an invalid parameter value */
|
||||
|
||||
/* ---------------------------------WAKEUPTIMER---------------------------------*/
|
||||
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
|
||||
|
|
@ -975,7 +1013,7 @@ typedef struct
|
|||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_WUTIE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC WakeUpTimer interrupt.
|
||||
|
|
@ -985,7 +1023,7 @@ typedef struct
|
|||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_WUTIE))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
|
||||
|
|
@ -993,10 +1031,9 @@ typedef struct
|
|||
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) !=\
|
||||
0UL) ? 1UL : 0UL)
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
|
||||
|
|
@ -1004,10 +1041,9 @@ typedef struct
|
|||
* @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != \
|
||||
0UL) ? 1UL : 0UL)
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_WUTIE)) != 0U)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC WakeUpTimers flag status.
|
||||
|
|
@ -1016,9 +1052,14 @@ typedef struct
|
|||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_WUTF
|
||||
* @arg @ref RTC_FLAG_WUTWF
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \
|
||||
((__FLAG__) == RTC_FLAG_WUTF) ?\
|
||||
(READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\
|
||||
((__FLAG__) == RTC_FLAG_WUTWF) ?\
|
||||
(READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\
|
||||
(0U)) /*!< Return 0 because it is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Wake Up timers pending flags.
|
||||
|
|
@ -1028,7 +1069,8 @@ typedef struct
|
|||
* @arg @ref RTC_FLAG_WUTF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
|
||||
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1060,7 +1102,7 @@ typedef struct
|
|||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_TSIE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp interrupt.
|
||||
|
|
@ -1070,7 +1112,7 @@ typedef struct
|
|||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_TSIE))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
|
||||
|
|
@ -1078,10 +1120,9 @@ typedef struct
|
|||
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != \
|
||||
0U) ? 1UL : 0UL)
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
|
||||
|
|
@ -1089,10 +1130,9 @@ typedef struct
|
|||
* @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ?\
|
||||
1UL : 0UL)
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_TSIE)) != 0U)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC TimeStamps flag status.
|
||||
|
|
@ -1101,9 +1141,14 @@ typedef struct
|
|||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_TSF
|
||||
* @arg @ref RTC_FLAG_TSOVF
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter.
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
|
||||
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \
|
||||
((__FLAG__) == RTC_FLAG_TSF) ?\
|
||||
(READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\
|
||||
((__FLAG__) == RTC_FLAG_TSOVF) ?\
|
||||
(READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\
|
||||
(0U)) /*!< Return 0 because it is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Time Stamps pending flags.
|
||||
|
|
@ -1114,7 +1159,12 @@ typedef struct
|
|||
* @arg @ref RTC_FLAG_TSOVF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
|
||||
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \
|
||||
((__FLAG__) == RTC_FLAG_TSF) ?\
|
||||
(SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\
|
||||
((__FLAG__) == RTC_FLAG_TSOVF) ?\
|
||||
(SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\
|
||||
(0U)) /*!< Dummy action because is an invalid parameter value */
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC internal TimeStamp peripheral.
|
||||
|
|
@ -1138,8 +1188,7 @@ typedef struct
|
|||
* @arg @ref RTC_FLAG_ITSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),\
|
||||
(__FLAG__)))
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_ITSF) == RTC_SR_ITSF))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Internal Time Stamps pending flags.
|
||||
|
|
@ -1149,8 +1198,7 @@ typedef struct
|
|||
* @arg @ref RTC_FLAG_ITSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__),\
|
||||
RTC_CLEAR_ITSF))
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CITSF))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp on Tamper detection.
|
||||
|
|
@ -1207,7 +1255,6 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the clock reference detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
|
|
@ -1222,21 +1269,19 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC shift operations flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_SHPF
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* ------------------------------Tamper----------------------------------*/
|
||||
/** @defgroup RTCEx_Tamper RTCEx tamper
|
||||
* @{
|
||||
|
|
@ -1409,7 +1454,7 @@ typedef struct
|
|||
* @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag
|
||||
* @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag
|
||||
* @arg RTC_FLAG_INT_TAMP_15: Internal Tamper15 flag
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U)
|
||||
|
||||
|
|
@ -1461,7 +1506,7 @@ typedef struct
|
|||
* @arg @ref RTC_IT_SSRU SSRU interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__))
|
||||
#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_SSRUIE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC SSRU interrupt.
|
||||
|
|
@ -1471,7 +1516,7 @@ typedef struct
|
|||
* @arg @ref RTC_IT_SSRU SSRU interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
|
||||
#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_SSRUIE))
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -1480,19 +1525,18 @@ typedef struct
|
|||
* @param __INTERRUPT__ specifies the RTC SSRU interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_SSRU SSRU interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) \
|
||||
? 1U : 0U)
|
||||
#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) ? 1U : 0U)
|
||||
/**
|
||||
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_SSRU SSRU interrupt
|
||||
* @retval None
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
|
||||
#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (RTC_CR_SSRUIE)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC SSRU's flag status.
|
||||
|
|
@ -1500,9 +1544,9 @@ typedef struct
|
|||
* @param __FLAG__ specifies the RTC SSRU Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_SSRUF
|
||||
* @retval None
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE)
|
||||
*/
|
||||
#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Wake Up timer's pending flags.
|
||||
|
|
@ -1512,7 +1556,7 @@ typedef struct
|
|||
* @arg @ref RTC_FLAG_SSRUF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF))
|
||||
#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@
|
|||
|
||||
[..]
|
||||
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
weak function.
|
||||
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the callback ID.
|
||||
[..]
|
||||
|
|
@ -186,10 +186,10 @@
|
|||
|
||||
[..]
|
||||
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
|
||||
all callbacks are reset to the corresponding legacy weak functions:
|
||||
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit callbacks that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
|
||||
reset to the legacy weak functions in the HAL_SAI_Init
|
||||
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
|
@ -206,7 +206,7 @@
|
|||
[..]
|
||||
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak callbacks are used.
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@
|
|||
|
||||
(#) At this stage, you can perform SD read/write/erase operations after SD card initialization
|
||||
|
||||
|
||||
*** SD Card Initialization and configuration ***
|
||||
================================================
|
||||
[..]
|
||||
|
|
@ -613,7 +612,6 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the SD MSP.
|
||||
* @param hsd: Pointer to SD handle
|
||||
|
|
@ -1316,7 +1314,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
|
|||
/* Enable transfer interrupts */
|
||||
__HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
|
||||
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
|
|
@ -1383,7 +1380,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *p
|
|||
config.DPSM = SDMMC_DPSM_DISABLE;
|
||||
(void)SDMMC_ConfigData(hsd->Instance, &config);
|
||||
|
||||
|
||||
__SDMMC_CMDTRANS_ENABLE(hsd->Instance);
|
||||
|
||||
hsd->Instance->IDMABASER = (uint32_t) pData ;
|
||||
|
|
@ -2330,7 +2326,6 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
|
|||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -2371,6 +2366,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
SDMMC_InitTypeDef Init;
|
||||
uint32_t errorstate;
|
||||
uint32_t sdmmc_clk;
|
||||
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
|
|
@ -2422,11 +2418,15 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
|
|||
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
|
||||
}
|
||||
#if defined(SDMMC2)
|
||||
else
|
||||
else if (hsd->Instance == SDMMC2)
|
||||
{
|
||||
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2);
|
||||
}
|
||||
#endif /* SDMMC2 */
|
||||
else
|
||||
{
|
||||
sdmmc_clk = 0U;
|
||||
}
|
||||
if (sdmmc_clk != 0U)
|
||||
{
|
||||
/* Configure the SDMMC peripheral */
|
||||
|
|
@ -2950,7 +2950,6 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
|
|||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Abort the current transfer and disable the SD (IT mode).
|
||||
* @param hsd: pointer to a SD_HandleTypeDef structure that contains
|
||||
|
|
@ -3008,7 +3007,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
|
|||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the sd card.
|
||||
* @param hsd: Pointer to SD handle
|
||||
|
|
@ -3515,7 +3513,6 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Finds the SD card SCR register value.
|
||||
* @param hsd: Pointer to SD handle
|
||||
|
|
@ -3570,7 +3567,6 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
|
|||
index++;
|
||||
}
|
||||
|
||||
|
||||
if ((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
|
||||
{
|
||||
return HAL_SD_ERROR_TIMEOUT;
|
||||
|
|
@ -3727,7 +3723,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode)
|
|||
|
||||
(void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
|
||||
|
||||
|
||||
errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode);
|
||||
if (errorstate != HAL_SD_ERROR_NONE)
|
||||
{
|
||||
|
|
@ -3745,7 +3740,6 @@ uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode)
|
|||
}
|
||||
loop ++;
|
||||
}
|
||||
|
||||
if ((HAL_GetTick() - Timeout) >= SDMMC_SWDATATIMEOUT)
|
||||
{
|
||||
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
@ -1333,7 +1333,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
|
|||
* the configuration information for SDRAM module.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
return hsdram->State;
|
||||
}
|
||||
|
|
@ -1356,6 +1356,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
|
|||
*/
|
||||
static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Derogation MISRAC2012-Rule-11.5 */
|
||||
SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
|
@ -1378,6 +1379,7 @@ static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Derogation MISRAC2012-Rule-11.5 */
|
||||
SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
|
@ -1400,6 +1402,7 @@ static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Derogation MISRAC2012-Rule-11.5 */
|
||||
SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
@ -212,7 +212,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
|
|||
* @{
|
||||
*/
|
||||
/* SDRAM State functions ********************************************************/
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2494,7 +2494,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
|
|||
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
|
||||
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
|
||||
}
|
||||
MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
|
||||
WRITE_REG(hsmartcard->Instance->RTOR, tmpreg);
|
||||
|
||||
/*-------------------------- USART BRR Configuration -----------------------*/
|
||||
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
|
||||
|
|
|
|||
|
|
@ -1037,6 +1037,122 @@ typedef enum
|
|||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif (defined(STM32H523xx) || defined(STM32H533xx))
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_CSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL2Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_PLL3Q: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
|
|
|
|||
|
|
@ -2585,8 +2585,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
|
|||
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
|
||||
}
|
||||
|
||||
/* Flush TX register */
|
||||
SMBUS_Flush_TXDR(hsmbus);
|
||||
if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
|
||||
{
|
||||
/* Flush TX register */
|
||||
SMBUS_Flush_TXDR(hsmbus);
|
||||
}
|
||||
|
||||
/* Store current volatile hsmbus->ErrorCode, misra rule */
|
||||
tmperror = hsmbus->ErrorCode;
|
||||
|
|
|
|||
|
|
@ -100,8 +100,6 @@ typedef struct
|
|||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
* This file provides firmware functions to manage the following
|
||||
* functionalities of SMBUS Extended peripheral:
|
||||
* + Extended features functions
|
||||
* + WakeUp Mode Functions
|
||||
* + FastModePlus Functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -9,7 +9,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
@ -1162,6 +1162,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
|
|||
*/
|
||||
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Derogation MISRAC2012-Rule-11.5 */
|
||||
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
|
@ -1184,6 +1185,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Derogation MISRAC2012-Rule-11.5 */
|
||||
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
|
@ -1206,6 +1208,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
|
|||
*/
|
||||
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Derogation MISRAC2012-Rule-11.5 */
|
||||
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2022 STMicroelectronics.
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
|
|
|
|||
|
|
@ -3854,7 +3854,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
||||
{
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
/* Input capture event */
|
||||
|
|
@ -3886,7 +3886,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
||||
|
|
@ -3916,7 +3916,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
||||
|
|
@ -3946,7 +3946,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
||||
|
|
@ -3976,7 +3976,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->PeriodElapsedCallback(htim);
|
||||
#else
|
||||
|
|
@ -3985,11 +3985,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
}
|
||||
}
|
||||
/* TIM Break input event */
|
||||
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
|
||||
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
||||
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
|
||||
{
|
||||
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->BreakCallback(htim);
|
||||
#else
|
||||
|
|
@ -4015,7 +4016,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->TriggerCallback(htim);
|
||||
#else
|
||||
|
|
@ -4028,7 +4029,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->CommutationCallback(htim);
|
||||
#else
|
||||
|
|
@ -4041,7 +4042,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->EncoderIndexCallback(htim);
|
||||
#else
|
||||
|
|
@ -4054,7 +4055,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->DirectionChangeCallback(htim);
|
||||
#else
|
||||
|
|
@ -4067,7 +4068,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->IndexErrorCallback(htim);
|
||||
#else
|
||||
|
|
@ -4080,7 +4081,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|||
{
|
||||
if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->TransitionErrorCallback(htim);
|
||||
#else
|
||||
|
|
@ -4617,6 +4618,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
|
|||
* @arg TIM_DMABASE_TISEL
|
||||
* @arg TIM_DMABASE_AF1
|
||||
* @arg TIM_DMABASE_AF2
|
||||
* @arg TIM_DMABASE_OR1
|
||||
* @param BurstRequestSrc TIM DMA Request sources
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
||||
|
|
@ -4633,7 +4635,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
|
|||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t BlockDataLength = 0;
|
||||
|
|
@ -4761,6 +4764,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
|
|||
* @arg TIM_DMABASE_TISEL
|
||||
* @arg TIM_DMABASE_AF1
|
||||
* @arg TIM_DMABASE_AF2
|
||||
* @arg TIM_DMABASE_OR1
|
||||
* @param BurstRequestSrc TIM DMA Request sources
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
||||
|
|
@ -5070,6 +5074,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
|
|||
* @arg TIM_DMABASE_TISEL
|
||||
* @arg TIM_DMABASE_AF1
|
||||
* @arg TIM_DMABASE_AF2
|
||||
* @arg TIM_DMABASE_OR1
|
||||
* @param BurstRequestSrc TIM DMA Request sources
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
||||
|
|
@ -5214,6 +5219,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
|
|||
* @arg TIM_DMABASE_TISEL
|
||||
* @arg TIM_DMABASE_AF1
|
||||
* @arg TIM_DMABASE_AF2
|
||||
* @arg TIM_DMABASE_OR1
|
||||
* @param BurstRequestSrc TIM DMA Request sources
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
|
||||
|
|
@ -5575,12 +5581,22 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
|
|||
CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
|
||||
break;
|
||||
}
|
||||
case TIM_CLEARINPUTSOURCE_OCREFCLR:
|
||||
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
case TIM_CLEARINPUTSOURCE_COMP1:
|
||||
case TIM_CLEARINPUTSOURCE_COMP2:
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_OCXREF_COMP_CLEARINPUT_INSTANCE(htim->Instance));
|
||||
|
||||
/* Clear the OCREF clear selection bit */
|
||||
CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
|
||||
|
||||
/* Set the clear input source */
|
||||
MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
|
||||
break;
|
||||
}
|
||||
#endif /* COMP1 && COMP2 */
|
||||
|
||||
case TIM_CLEARINPUTSOURCE_ETR:
|
||||
{
|
||||
|
|
@ -7033,38 +7049,18 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
|
|||
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -7131,42 +7127,18 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
|
|||
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -7230,11 +7202,6 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
}
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->PeriodElapsedCallback(htim);
|
||||
#else
|
||||
|
|
@ -7267,11 +7234,6 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
|
|||
{
|
||||
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
|
||||
|
||||
if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
}
|
||||
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->TriggerCallback(htim);
|
||||
#else
|
||||
|
|
@ -7341,6 +7303,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
|
|||
/* Generate an update event to reload the Prescaler
|
||||
and the repetition counter (only for advanced timer) value immediately */
|
||||
TIMx->EGR = TIM_EGR_UG;
|
||||
|
||||
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
||||
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
||||
{
|
||||
/* Clear the update flag */
|
||||
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -7465,7 +7434,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|||
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
||||
/* Reset the Output N State */
|
||||
tmpccer &= ~TIM_CCER_CC2NE;
|
||||
|
||||
}
|
||||
|
||||
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
||||
|
|
|
|||
|
|
@ -416,29 +416,28 @@ typedef struct
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
|
|
@ -471,9 +470,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
|
||||
#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
|
||||
#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */
|
||||
#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */
|
||||
#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */
|
||||
#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -507,6 +509,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
#define TIM_DMABASE_TISEL 0x00000017U
|
||||
#define TIM_DMABASE_AF1 0x00000018U
|
||||
#define TIM_DMABASE_AF2 0x00000019U
|
||||
#define TIM_DMABASE_OR1 0x0000001AU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1066,8 +1069,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
|||
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
|
||||
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
|
||||
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */
|
||||
#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */
|
||||
/**
|
||||
|
|
@ -1848,9 +1851,15 @@ mode.
|
|||
/** @defgroup TIM_Private_Macros TIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
|
||||
#else
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
|
||||
((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
|
||||
#endif /* COMP1 && COMP2 */
|
||||
|
||||
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
|
||||
((__BASE__) == TIM_DMABASE_CR2) || \
|
||||
|
|
@ -1958,8 +1967,9 @@ mode.
|
|||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
|
||||
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
|
||||
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
|
||||
((__PERIOD__) > 0U))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
|
|
@ -2022,7 +2032,6 @@ mode.
|
|||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
|
|
@ -2091,8 +2100,8 @@ mode.
|
|||
((__MODE__) == TIM_OCMODE_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
|
||||
((__MODE__) == TIM_OCMODE_ACTIVE) || \
|
||||
|
|
@ -2416,7 +2425,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
|
|||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
|
|
|
|||
|
|
@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
|
|||
|
||||
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
||||
tmpccer = htim->Instance->CCER;
|
||||
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
|
||||
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
||||
}
|
||||
|
|
@ -1149,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
|
|||
(+) Stop the Complementary PWM and disable interrupts.
|
||||
(+) Start the Complementary PWM and enable DMA transfers.
|
||||
(+) Stop the Complementary PWM and disable DMA transfers.
|
||||
(+) Start the Complementary Input Capture measurement.
|
||||
(+) Stop the Complementary Input Capture.
|
||||
(+) Start the Complementary Input Capture and enable interrupts.
|
||||
(+) Stop the Complementary Input Capture and disable interrupts.
|
||||
(+) Start the Complementary Input Capture and enable DMA transfers.
|
||||
(+) Stop the Complementary Input Capture and disable DMA transfers.
|
||||
(+) Start the Complementary One Pulse generation.
|
||||
(+) Stop the Complementary One Pulse.
|
||||
(+) Start the Complementary One Pulse and enable interrupts.
|
||||
(+) Stop the Complementary One Pulse and disable interrupts.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -1403,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
|||
|
||||
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
||||
tmpccer = htim->Instance->CCER;
|
||||
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET)
|
||||
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
||||
}
|
||||
|
|
@ -2196,6 +2185,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|||
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
||||
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
||||
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
||||
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
|
||||
|
||||
/* Check input state */
|
||||
__HAL_LOCK(htim);
|
||||
|
|
@ -2212,15 +2202,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
||||
|
||||
if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
|
||||
|
||||
/* Set BREAK AF mode */
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
|
||||
}
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
|
||||
|
||||
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
||||
{
|
||||
|
|
@ -2228,20 +2210,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|||
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
|
||||
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
||||
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
||||
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
|
||||
|
||||
/* Set the BREAK2 input related BDTR bits */
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
||||
|
||||
if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
|
||||
|
||||
/* Set BREAK2 AF mode */
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
|
||||
}
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
|
||||
}
|
||||
|
||||
/* Set TIMx_BDTR */
|
||||
|
|
@ -2265,7 +2240,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
|
||||
uint32_t BreakInput,
|
||||
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
|
||||
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmporx;
|
||||
|
|
@ -2366,50 +2340,73 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
|
|||
* @param htim TIM handle.
|
||||
* @param Remap specifies the TIM remapping source.
|
||||
* For TIM1, the parameter can take one of the following values:
|
||||
* @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
|
||||
* @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
|
||||
* @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
|
||||
* @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
|
||||
* @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
|
||||
* @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
|
||||
* @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
|
||||
* @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
|
||||
*
|
||||
* For TIM2, the parameter can take one of the following values:
|
||||
* @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
|
||||
* @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE
|
||||
* @arg TIM_TIM2_ETR_SAI1_FSA TIM2 ETR is connected to SAI1 FSA (*)
|
||||
* @arg TIM_TIM2_ETR_SAI1_FSB TIM2 ETR is connected to SAI1 FSB (*)
|
||||
* @arg TIM_TIM2_ETR_SAI1_FSA TIM2 ETR is connected to SAI1 FSA (*)
|
||||
* @arg TIM_TIM2_ETR_SAI1_FSB TIM2 ETR is connected to SAI1 FSB (*)
|
||||
* @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin
|
||||
* @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin (*)
|
||||
* @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*)
|
||||
* @arg TIM_TIM2_ETR_ETH_PPS TIM2 ETR is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin (*)
|
||||
* @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*)
|
||||
* @arg TIM_TIM2_ETR_USB_SOF TIM2 ETR is connected to USB SOF (*)
|
||||
* @arg TIM_TIM2_ETR_USBHS_SOF TIM2 ETR is connected to USBHS OTG SOF (*)
|
||||
* @arg TIM_TIM2_ETR_USBFS_SOF TIM2 ETR is connected to USBFS OTG SOF (*)
|
||||
* @arg TIM_TIM2_ETR_ETH_PPS TIM2 ETR is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM2_ETR_PLAY1_OUT0 TIM2 ETR is connected to PLAY1 output 0 (*)
|
||||
*
|
||||
* For TIM3, the parameter can take one of the following values:
|
||||
* @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO
|
||||
* @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1 (*)
|
||||
* @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2 (*)
|
||||
* @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3 (*)
|
||||
* @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin
|
||||
* @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin (*)
|
||||
* @arg TIM_TIM3_ETR_TIM5_ETR TIM3 ETR is connected to TIM5 ETR pin (*)
|
||||
* @arg TIM_TIM3_ETR_ETH_PPS TIM3 ETR is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin (*)
|
||||
* @arg TIM_TIM3_ETR_TIM5_ETR TIM3 ETR is connected to TIM5 ETR pin (*)
|
||||
* @arg TIM_TIM3_ETR_ETH_PPS TIM3 ETR is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM3_ETR_PLAY1_OUT0 TIM3 ETR is connected to PLAY1 output 0 (*)
|
||||
*
|
||||
* For TIM4, the parameter can take one of the following values: (**)
|
||||
* @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
|
||||
* @arg TIM_TIM4_ETR_TIM2_ETR TIM4 ETR is connected to TIM2 ETR pin
|
||||
* @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
|
||||
* @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin
|
||||
* @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
|
||||
* @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM4_ETR_TIM2_ETR TIM4 ETR is connected to TIM2 ETR pin
|
||||
* @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin
|
||||
* @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin
|
||||
*
|
||||
* For TIM5, the parameter can take one of the following values: (**)
|
||||
* @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO
|
||||
* @arg TIM_TIM2_ETR_SAI2_FSA TIM2 ETR is connected to SAI2 FSA
|
||||
* @arg TIM_TIM2_ETR_SAI2_FSB TIM2 ETR is connected to SAI2 FSB
|
||||
* @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin
|
||||
* @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin
|
||||
* @arg TIM_TIM5_ETR_TIM4_ETR TIM5 ETR is connected to TIM4 ETR pin
|
||||
* @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO
|
||||
* @arg TIM_TIM5_ETR_SAI2_FSA TIM5 ETR is connected to SAI2 FSA
|
||||
* @arg TIM_TIM5_ETR_SAI2_FSB TIM5 ETR is connected to SAI2 FSB
|
||||
* @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin
|
||||
* @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin
|
||||
* @arg TIM_TIM5_ETR_TIM4_ETR TIM5 ETR is connected to TIM4 ETR pin
|
||||
* @arg TIM_TIM5_ETR_USB_SOF TIM5 ETR is connected to USB SOF (*)
|
||||
* @arg TIM_TIM5_ETR_USBHS_SOF TIM5 ETR is connected to USBHS OTG SOF (*)
|
||||
* @arg TIM_TIM5_ETR_USBFS_SOF TIM5 ETR is connected to USBFS OTG SOF (*)
|
||||
*
|
||||
* For TIM8, the parameter can take one of the following values: (**)
|
||||
* @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO
|
||||
* @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1
|
||||
* @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2
|
||||
* @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3
|
||||
* @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*)
|
||||
* @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*)
|
||||
* @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*)
|
||||
*
|
||||
* (*) Value not defined in all devices.
|
||||
* (**) Timer instance not available on all devices. \n
|
||||
|
|
@ -2442,69 +2439,96 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
|||
* @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
|
||||
* For TIM1, the parameter is one of the following values:
|
||||
* @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM1_TI3_GPIO: TIM1 TI3 is connected to GPIO
|
||||
* @arg TIM_TIM1_TI4_GPIO: TIM1 TI4 is connected to GPIO
|
||||
*
|
||||
* For TIM2, the parameter is one of the following values:
|
||||
* @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM2_TI1_LSI: TIM2 TI1 is connected to LSI (*)
|
||||
* @arg TIM_TIM2_TI1_LSE: TIM2 TI1 is connected to LSE (*)
|
||||
* @arg TIM_TIM2_TI1_ETH_PPS TIM2 TI1 is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM2_TI1_RTC_WKUP: TIM2 TI2 is connected to RTC_WKUP (*)
|
||||
* @arg TIM_TIM2_TI1_TIM3_TI1: TIM2 TI2 is connected to TIM3_TI1 (*)
|
||||
* @arg TIM_TIM2_TI1_LSI: TIM2 TI1 is connected to LSI (*)
|
||||
* @arg TIM_TIM2_TI1_LSE: TIM2 TI1 is connected to LSE (*)
|
||||
* @arg TIM_TIM2_TI1_RTC_WKUP: TIM2 TI2 is connected to RTC_WKUP (*)
|
||||
* @arg TIM_TIM2_TI1_TIM3_TI1: TIM2 TI2 is connected to TIM3_TI1 (*)
|
||||
* @arg TIM_TIM2_TI1_ETH_PPS TIM2 TI1 is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM2_TI1_COMP1 TIM2 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM2_TI1_COMP2 TIM2 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM2_TI1_PLAY1_OUT3 TIM2 TI1 is connected to PLAY1 output 3 (*)
|
||||
* @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM2_TI2_HSI_1024: TIM2 TI2 is connected to HSI/1024 (*)
|
||||
* @arg TIM_TIM2_TI2_CSI_128: TIM2 TI2 is connected to CSI/128 (*)
|
||||
* @arg TIM_TIM2_TI2_MCO2: TIM2 TI2 is connected to MCO1 (*)
|
||||
* @arg TIM_TIM2_TI2_MCO1: TIM2 TI2 is connected to MCO1 (*)
|
||||
* @arg TIM_TIM2_TI2_HSI_1024: TIM2 TI2 is connected to HSI/1024 (*)
|
||||
* @arg TIM_TIM2_TI2_CSI_128: TIM2 TI2 is connected to CSI/128 (*)
|
||||
* @arg TIM_TIM2_TI2_MCO2: TIM2 TI2 is connected to MCO2 (*)
|
||||
* @arg TIM_TIM2_TI2_MCO1: TIM2 TI2 is connected to MCO1 (*)
|
||||
* @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO
|
||||
* @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
|
||||
* @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*)
|
||||
*
|
||||
* For TIM3, the parameter is one of the following values:
|
||||
* @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM3_TI1_MCO1: TIM3 TI2 is connected to MCO1 (*)
|
||||
* @arg TIM_TIM3_TI1_TIM2_TI1: TIM3 TI2 is connected to TIM2 TI1 (*)
|
||||
* @arg TIM_TIM3_TI1_HSE_1MHZ: TIM3 TI2 is connected to HSE_1MHZ (*)
|
||||
* @arg TIM_TIM3_TI1_ETH_PPS TIM3 TI1 is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM3_TI1_MCO1: TIM3 TI2 is connected to MCO1 (*)
|
||||
* @arg TIM_TIM3_TI1_TIM2_TI1: TIM3 TI2 is connected to TIM2 TI1 (*)
|
||||
* @arg TIM_TIM3_TI1_HSE_1MHZ: TIM3 TI2 is connected to HSE_1MHZ (*)
|
||||
* @arg TIM_TIM3_TI1_ETH_PPS TIM3 TI1 is connected to ETH PPS (*)
|
||||
* @arg TIM_TIM3_TI1_COMP1 TIM3 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM3_TI1_COMP2 TIM3 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM3_TI1_PLAY1_OUT3 TIM3 TI1 is connected to PLAY1 output 3 (*)
|
||||
* @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM3_TI2_CSI_128: TIM3 TI2 is connected to CSI_128 (*)
|
||||
* @arg TIM_TIM3_TI2_MCO2: TIM3 TI2 is connected to MCO2 (*)
|
||||
* @arg TIM_TIM3_TI2_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*)
|
||||
* @arg TIM_TIM3_TI2_CSI_128: TIM3 TI2 is connected to CSI_128 (*)
|
||||
* @arg TIM_TIM3_TI2_MCO2: TIM3 TI2 is connected to MCO2 (*)
|
||||
* @arg TIM_TIM3_TI2_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*)
|
||||
* @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM3_TI3_GPIO: TIM3 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM3_TI4_GPIO: TIM3 TI2 is connected to GPIO
|
||||
*
|
||||
* For TIM4, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM4_TI1_COMP1 TIM4 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM4_TI1_COMP2 TIM4 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO
|
||||
* @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO
|
||||
*
|
||||
* For TIM5, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM5_TI1_COMP1 TIM5 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM5_TI1_COMP2 TIM5 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM5_TI3_GPIO: TIM5 TI3 is connected to GPIO
|
||||
* @arg TIM_TIM5_TI4_GPIO: TIM5 TI4 is connected to GPIO
|
||||
*
|
||||
* For TIM8, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM8_TI1_COMP1 TIM8 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM8_TI1_COMP2 TIM8 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM8_TI2_GPIO: TIM8 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM8_TI3_GPIO: TIM8 TI3 is connected to GPIO
|
||||
* @arg TIM_TIM8_TI4_GPIO: TIM8 TI4 is connected to GPIO
|
||||
*
|
||||
* For TIM12, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM12_TI1_COMP1 TIM12 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM12_TI1_COMP2 TIM12 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM12_TI1_HSI_1024: TIM12 TI1 is connected to HSI/1024
|
||||
* @arg TIM_TIM12_TI1_CSI_128: TIM12 TI1 is connected to CSI/128
|
||||
* @arg TIM_TIM12_TI2_GPIO: TIM12 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM12_TI2_COMP2 TIM12 TI2 is connected to COMP2 output (*)
|
||||
*
|
||||
* For TIM13, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM12_TI1_GPIO: TIM13 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM13_TI1_GPIO: TIM13 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM13_TI1_I3C1_IBIACK TIM13 TI1 is connected to I3C1 IBI ACK (*)
|
||||
* @arg TIM_TIM13_TI1_COMP1 TIM13 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM13_TI1_COMP2 TIM13 TI1 is connected to COMP2 output (*)
|
||||
*
|
||||
* For TIM14, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM14_TI1_I3C2_IBIACK TIM14 TI1 is connected to I3C2 IBI ACK (*)
|
||||
* @arg TIM_TIM14_TI1_COMP1 TIM14 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM14_TI1_COMP2 TIM14 TI1 is connected to COMP2 output (*)
|
||||
*
|
||||
* For TIM15, the parameter can have the following values: (**)
|
||||
* @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
|
||||
|
|
@ -2513,22 +2537,30 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
|||
* @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4
|
||||
* @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
|
||||
* @arg TIM_TIM15_TI1_CSI_128: TIM15 TI1 is connected to CSI/128
|
||||
* @arg TIM_TIM15_TI1_MCO: TIM15 TI1 is connected to MCO
|
||||
* @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
|
||||
* @arg TIM_TIM15_TI1_COMP1 TIM15 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM15_TI1_COMP2 TIM15 TI1 is connected to COMP2 output (*)
|
||||
* @arg TIM_TIM15_TI2_GPIO: TIM15 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM15_TI2_TIM2: TIM15 TI1 is connected to TIM2
|
||||
* @arg TIM_TIM15_TI2_TIM3: TIM15 TI1 is connected to TIM3
|
||||
* @arg TIM_TIM15_TI2_TIM4: TIM15 TI1 is connected to TIM4
|
||||
* @arg TIM_TIM15_TI2_COMP1 TIM15 TI2 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM15_TI2_COMP2 TIM15 TI2 is connected to COMP2 output (*)
|
||||
*
|
||||
* For TIM16, the parameter is one of the following values: (**)
|
||||
* @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
|
||||
* @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
|
||||
* @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTCWKUP
|
||||
* @arg TIM_TIM16_TI1_COMP1 TIM16 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM16_TI1_COMP2 TIM16 TI1 is connected to COMP2 output (*)
|
||||
*
|
||||
* For TIM17, the parameter can have the following values: (**)
|
||||
* @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ
|
||||
* @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
|
||||
* @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
|
||||
* @arg TIM_TIM17_TI1_COMP1 TIM17 TI1 is connected to COMP1 output (*)
|
||||
* @arg TIM_TIM17_TI1_COMP2 TIM17 TI1 is connected to COMP2 output (*)
|
||||
*
|
||||
* (*) Value not defined in all devices. \n
|
||||
* (**) Timer instance not available on all devices. \n
|
||||
|
|
@ -2548,6 +2580,18 @@ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISel
|
|||
{
|
||||
case TIM_CHANNEL_1:
|
||||
MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
|
||||
|
||||
#if defined(TIM17)
|
||||
/* If required, set OR1 bit to request HSE 1MHz clock */
|
||||
if ((IS_TIM_RTCPREEN_INSTANCE(htim->Instance)) && (IS_TIM_RTCPREEN_SELECTION(TISelection)))
|
||||
{
|
||||
SET_BIT(htim->Instance->OR1, TIM_OR1_RTCPREEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(htim->Instance->OR1, TIM_OR1_RTCPREEN);
|
||||
}
|
||||
#endif /* TIM17 */
|
||||
break;
|
||||
case TIM_CHANNEL_2:
|
||||
MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
|
||||
|
|
@ -2620,7 +2664,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
|
|||
uint32_t tmpbdtr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAKINPUT(BreakInput));
|
||||
|
||||
switch (BreakInput)
|
||||
|
|
@ -2637,7 +2681,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
|
|||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case TIM_BREAKINPUT_BRK2:
|
||||
{
|
||||
/* Check initial conditions */
|
||||
|
|
@ -2675,7 +2718,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3
|
|||
uint32_t tickstart;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAKINPUT(BreakInput));
|
||||
|
||||
switch (BreakInput)
|
||||
|
|
@ -3089,7 +3132,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
|
|||
*/
|
||||
|
||||
/**
|
||||
* @brief Hall commutation changed callback in non-blocking mode
|
||||
* @brief Commutation callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -3103,7 +3146,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|||
*/
|
||||
}
|
||||
/**
|
||||
* @brief Hall commutation changed half complete callback in non-blocking mode
|
||||
* @brief Commutation half complete callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -3118,7 +3161,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Hall Break detection callback in non-blocking mode
|
||||
* @brief Break detection callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -3133,7 +3176,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief Hall Break2 detection callback in non blocking mode
|
||||
* @brief Break2 detection callback in non blocking mode
|
||||
* @param htim: TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -3322,38 +3365,18 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
|
|||
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -3393,6 +3416,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
|
|||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
|
|
@ -3424,13 +3452,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
|
|||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
||||
tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
|
||||
|
||||
/* Reset the CCxNE Bit */
|
||||
TIMx->CCER &= ~tmp;
|
||||
|
||||
/* Set or reset the CCxNE Bit */
|
||||
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
||||
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -106,70 +106,119 @@ typedef struct
|
|||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */
|
||||
#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */
|
||||
#if defined(COMP1)
|
||||
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */
|
||||
#endif /* COMP1 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
#if defined(COMP1)
|
||||
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */
|
||||
#endif /* COMP1 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
|
||||
|
||||
#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */
|
||||
#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */
|
||||
#if defined(COMP1)
|
||||
#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */
|
||||
#endif /* COMP1 */
|
||||
#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to LSE */
|
||||
#if defined(COMP2)
|
||||
#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP2 output */
|
||||
#endif /* COMP2 */
|
||||
#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */
|
||||
#if defined(SAI1)
|
||||
#define TIM_TIM2_ETR_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
|
||||
#define TIM_TIM2_ETR_SAI1_FSB (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to SAI1 */
|
||||
#define TIM_TIM2_ETR_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
|
||||
#define TIM_TIM2_ETR_SAI1_FSB (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 */
|
||||
#endif /* SAI1 */
|
||||
#define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_3) /*!< TIM2_ETR is connected to TIM3 ETR */
|
||||
#define TIM_TIM2_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM3 ETR */
|
||||
#if defined(TIM4)
|
||||
#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_3) /*!< TIM2_ETR is connected to TIM4 ETR */
|
||||
#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM4 ETR */
|
||||
#endif /* TIM4 */
|
||||
#if defined(TIM5)
|
||||
#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3 ) /*!< TIM2_ETR is connected to TIM5 ETR */
|
||||
#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM5 ETR */
|
||||
#endif /* TIM5 */
|
||||
#if defined(USB_DRD_FS)
|
||||
#define TIM_TIM2_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USB SOF */
|
||||
#elif defined(USB_OTG_HS)
|
||||
#define TIM_TIM2_ETR_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to USBHS OTG SOF */
|
||||
#define TIM_TIM2_ETR_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USBFS OTG SOF */
|
||||
#endif /* USB_DRD_FS */
|
||||
#if defined(ETH_NS)
|
||||
#define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< TIM2_ETR is connected to ETH PPS */
|
||||
#define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to ETH PPS */
|
||||
#endif /* ETH_NS */
|
||||
#if defined(PLAY1)
|
||||
#define TIM_TIM2_ETR_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< TIM2_ETR is connected to PLAY1 output 0 */
|
||||
#endif /* PLAY1 */
|
||||
|
||||
#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */
|
||||
#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */
|
||||
#if defined(COMP1)
|
||||
#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */
|
||||
#endif /* COMP1 */
|
||||
#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */
|
||||
#if defined(COMP2)
|
||||
#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */
|
||||
#endif /* COMP2 */
|
||||
#if defined(ADC2)
|
||||
#define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC2 AWD1 */
|
||||
#define TIM_TIM3_ETR_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to ADC2 AWD2 */
|
||||
#define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC2 AWD3 */
|
||||
#endif /* ADC2 */
|
||||
#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */
|
||||
#if defined(TIM4)
|
||||
#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to TIM4 ETR */
|
||||
#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to TIM4 ETR */
|
||||
#endif /* TIM4 */
|
||||
#if defined(TIM5)
|
||||
#define TIM_TIM3_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM5 ETR */
|
||||
#define TIM_TIM3_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM5 ETR */
|
||||
#endif /* TIM5 */
|
||||
#if defined(ETH_NS)
|
||||
#define TIM_TIM3_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< TIM3_ETR is connected to ETH PPS */
|
||||
#define TIM_TIM3_ETR_ETH_PPS (TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< TIM3_ETR is connected to ETH PPS */
|
||||
#endif /* ETH_NS */
|
||||
#if defined(PLAY1)
|
||||
#define TIM_TIM3_ETR_PLAY1_OUT0 TIM1_AF1_ETRSEL_Msk /*!< TIM3_ETR is connected to PLAY1 output 0 */
|
||||
#endif /* PLAY1 */
|
||||
|
||||
#if defined(TIM4)
|
||||
#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */
|
||||
#define TIM_TIM4_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM2 ETR */
|
||||
#define TIM_TIM4_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM3 ETR */
|
||||
#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */
|
||||
#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM4_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM2 ETR */
|
||||
#define TIM_TIM4_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM3 ETR */
|
||||
#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */
|
||||
#endif /* TIM4 */
|
||||
|
||||
#if defined(TIM5)
|
||||
#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */
|
||||
#define TIM_TIM5_ETR_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 */
|
||||
#define TIM_TIM5_ETR_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 */
|
||||
#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */
|
||||
#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */
|
||||
#define TIM_TIM5_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM4 ETR */
|
||||
#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */
|
||||
#define TIM_TIM5_ETR_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 */
|
||||
#define TIM_TIM5_ETR_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */
|
||||
#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */
|
||||
#define TIM_TIM5_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM4 ETR */
|
||||
#if defined(USB_DRD_FS)
|
||||
#define TIM_TIM5_ETR_USB_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USB SOF */
|
||||
#elif defined(USB_OTG_HS)
|
||||
#define TIM_TIM5_ETR_USBHS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM5_ETR is connected to USBHS OTG SOF */
|
||||
#define TIM_TIM5_ETR_USBFS_SOF (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USBFS OTG SOF */
|
||||
#endif /* USB_DRD_FS */
|
||||
#endif /* TIM5 */
|
||||
|
||||
#if defined(TIM8)
|
||||
#define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to ADC1 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD3 */
|
||||
#define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */
|
||||
#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to ADC2 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */
|
||||
#if defined(ADC3)
|
||||
#define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
|
||||
#define TIM_TIM8_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */
|
||||
#endif /* ADC3 */
|
||||
#endif /* TIM8 */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -191,6 +240,15 @@ typedef struct
|
|||
#if defined(COMP1)
|
||||
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */
|
||||
#endif /* COMP1 */
|
||||
#if defined(COMP2)
|
||||
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */
|
||||
#endif /* COMP2 */
|
||||
#if defined(PLAY1)
|
||||
#define TIM_BREAKINPUTSOURCE_PLAY1 0x00000008U /*!< The PLAY1 output is connected to the break input (only for BKIN) */
|
||||
#endif /* PLAY1 */
|
||||
#if defined(MDF1)
|
||||
#define TIM_BREAKINPUTSOURCE_MDF1 0x00000100U /*!< The Digital filter break output is connected to the break input */
|
||||
#endif /* MDF1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -217,9 +275,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */
|
||||
#if defined(COMP1)
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP1 OUT */
|
||||
#define TIM_TIM1_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1_TI1 is connected to COMP2 OUT */
|
||||
#elif defined(COMP1)
|
||||
#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */
|
||||
#endif /* COMP1 */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM1_TI2_GPIO 0x00000000UL /*!< TIM1_TI2 is connected to GPIO */
|
||||
#define TIM_TIM1_TI3_GPIO 0x00000000UL /*!< TIM1_TI3 is connected to GPIO */
|
||||
#define TIM_TIM1_TI4_GPIO 0x00000000UL /*!< TIM1_TI4 is connected to GPIO */
|
||||
|
|
@ -234,6 +295,11 @@ typedef struct
|
|||
#if defined(ETH_NS)
|
||||
#define TIM_TIM2_TI1_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */
|
||||
#endif /* ETH_NS */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM2_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to COMP2 output */
|
||||
#define TIM_TIM2_TI1_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to PLAY1 output 3 */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */
|
||||
#if defined(STM32H503xx)
|
||||
#define TIM_TIM2_TI2_HSI_1024 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to HSI_1024 */
|
||||
|
|
@ -241,11 +307,15 @@ typedef struct
|
|||
#define TIM_TIM2_TI2_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */
|
||||
#define TIM_TIM2_TI2_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 output */
|
||||
#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM2_TI3_GPIO 0x00000000UL /*!< TIM2_TI3 is connected to GPIO */
|
||||
#define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */
|
||||
#if defined(COMP1)
|
||||
#if defined(STM32H503xx)
|
||||
#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 */
|
||||
#endif /* COMP1 */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
#define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
|
||||
#if defined(STM32H503xx)
|
||||
|
|
@ -257,17 +327,30 @@ typedef struct
|
|||
#if defined(ETH_NS)
|
||||
#define TIM_TIM3_TI1_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to ETH PPS */
|
||||
#endif /* ETH_NS */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM3_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to COMP2 output */
|
||||
#define TIM_TIM3_TI1_PLAY1_OUT3 TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to PLAY1 output 3 */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */
|
||||
#if defined(STM32H503xx)
|
||||
#define TIM_TIM3_TI2_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */
|
||||
#define TIM_TIM3_TI2_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */
|
||||
#define TIM_TIM3_TI2_HSI_1024 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM3_TI2 is connected to HSI 1024 */
|
||||
#endif /* STM32H503xx */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 output */
|
||||
#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM3_TI3_GPIO 0x00000000UL /*!< TIM3_TI3 is connected to GPIO */
|
||||
#define TIM_TIM3_TI4_GPIO 0x00000000UL /*!< TIM3_TI4 is connected to GPIO */
|
||||
|
||||
#if defined(TIM4)
|
||||
#define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM4_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */
|
||||
#define TIM_TIM4_TI3_GPIO 0x00000000UL /*!< TIM4_TI3 is connected to GPIO */
|
||||
#define TIM_TIM4_TI4_GPIO 0x00000000UL /*!< TIM4_TI4 is connected to GPIO */
|
||||
|
|
@ -275,6 +358,10 @@ typedef struct
|
|||
|
||||
#if defined(TIM5)
|
||||
#define TIM_TIM5_TI1_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM5_TI2_GPIO 0x00000000UL /*!< TIM5_TI2 is connected to GPIO */
|
||||
#define TIM_TIM5_TI3_GPIO 0x00000000UL /*!< TIM5_TI3 is connected to GPIO */
|
||||
#define TIM_TIM5_TI4_GPIO 0x00000000UL /*!< TIM5_TI4 is connected to GPIO */
|
||||
|
|
@ -282,6 +369,10 @@ typedef struct
|
|||
|
||||
#if defined(TIM8)
|
||||
#define TIM_TIM8_TI1_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM8_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM8_TI2_GPIO 0x00000000UL /*!< TIM8_TI2 is connected to GPIO */
|
||||
#define TIM_TIM8_TI3_GPIO 0x00000000UL /*!< TIM8_TI3 is connected to GPIO */
|
||||
#define TIM_TIM8_TI4_GPIO 0x00000000UL /*!< TIM8_TI4 is connected to GPIO */
|
||||
|
|
@ -289,16 +380,38 @@ typedef struct
|
|||
|
||||
#if defined(TIM12)
|
||||
#define TIM_TIM12_TI1_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM12_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM12_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM12_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM12_TI1_HSI_1024 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to HSI 1024 */
|
||||
#define TIM_TIM12_TI1_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */
|
||||
#define TIM_TIM12_TI2_GPIO 0x00000000UL /*!< TIM12_TI2 is connected to GPIO */
|
||||
#if defined(COMP2)
|
||||
#define TIM_TIM12_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM12_TI2 is connected to COMP2 output */
|
||||
#endif /* COMP2 */
|
||||
#endif /* TIM12 */
|
||||
|
||||
#if defined(TIM13)
|
||||
#define TIM_TIM13_TI1_GPIO 0x00000000UL /*!< TIM13_TI1 is connected to GPIO */
|
||||
#if defined(I3C1)
|
||||
#define TIM_TIM13_TI1_I3C1_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM13_TI1 is connected to I3C1 IBI ACK */
|
||||
#endif /* I3C1 */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM13_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM13_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM13_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM13_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#endif /* TIM13 */
|
||||
|
||||
#if defined(TIM14)
|
||||
#define TIM_TIM14_TI1_GPIO 0x00000000UL /*!< TIM14_TI1 is connected to GPIO */
|
||||
#if defined(I3C2)
|
||||
#define TIM_TIM14_TI1_I3C2_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM14_TI1 is connected to I3C2 IBI ACK */
|
||||
#endif /* I3C1 */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM14_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM14_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM14_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM14_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#endif /* TIM14 */
|
||||
|
||||
#if defined(TIM15)
|
||||
|
|
@ -309,10 +422,18 @@ typedef struct
|
|||
#define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */
|
||||
#define TIM_TIM15_TI1_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to CSI 128*/
|
||||
#define TIM_TIM15_TI1_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM15_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
|
||||
#define TIM_TIM15_TI2_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */
|
||||
#define TIM_TIM15_TI2_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */
|
||||
#define TIM_TIM15_TI2_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM15_TI2_COMP1 TIM_TISEL_TI2SEL_2 /*!< TIM15_TI2 is connected to COMP1 output */
|
||||
#define TIM_TIM15_TI2_COMP2 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#endif /* TIM15 */
|
||||
|
||||
#if defined(TIM16)
|
||||
|
|
@ -320,12 +441,20 @@ typedef struct
|
|||
#define TIM_TIM16_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */
|
||||
#define TIM_TIM16_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */
|
||||
#define TIM_TIM16_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM16_TI1_COMP1 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM16_TI1_COMP2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#endif /* TIM16 */
|
||||
|
||||
#if defined(TIM17)
|
||||
#define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
|
||||
#define TIM_TIM17_TI1_HSE_1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to HSE 1MHZ */
|
||||
#define TIM_TIM17_TI1_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define TIM_TIM17_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to COMP1 output */
|
||||
#define TIM_TIM17_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to COMP2 output */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
#endif /* TIM17 */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -507,12 +636,18 @@ typedef struct
|
|||
#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
|
||||
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
|
||||
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
|
||||
#if defined(COMP1)
|
||||
#if defined(COMP1) && defined(COMP2)
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_PLAY1) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1))
|
||||
#elif defined(COMP1)
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1))
|
||||
#else
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)
|
||||
#endif /* COMP1 */
|
||||
#endif /* COMP1 && COMP2 */
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
|
||||
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
|
||||
|
|
@ -716,7 +851,7 @@ typedef struct
|
|||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \
|
||||
|| \
|
||||
|| \
|
||||
(((INSTANCE) == TIM12) && \
|
||||
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
|
||||
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
|
||||
|
|
@ -1005,6 +1140,10 @@ typedef struct
|
|||
((__SELECTION__) == TIM_TS_ITR10)|| \
|
||||
((__SELECTION__) == TIM_TS_ITR11)|| \
|
||||
((__SELECTION__) == TIM_TS_NONE))))
|
||||
|
||||
#if defined(TIM17)
|
||||
#define IS_TIM_RTCPREEN_SELECTION(__SELECTION__) ((__SELECTION__) == TIM_TIM17_TI1_HSE_1MHZ)
|
||||
#endif /* TIM17 */
|
||||
#endif /* STM32H503xx */
|
||||
|
||||
#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \
|
||||
|
|
|
|||
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Reference in New Issue