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Merge pull request #7351 from jeromecoutant/PR_ASTYLE 

STM32 files with MBED astyle rules
pull/7361/head
Cruz Monrreal 2018-06-28 10:06:03 -05:00 committed by GitHub
parent 5bf483ee17 408209989e
commit bf21bac52d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
279 changed files with 4542 additions and 4306 deletions
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80
features/mbedtls/targets/TARGET_STM/aes_alt.c
View File

@ -51,12 +51,14 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B;
memcpy(ctx->aes_key, key, 32);
break;
default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
default :
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
}
/* Deinitializes the CRYP peripheral */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR)
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) {
return (HAL_ERROR);
}
ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
ctx->hcryp_aes.Instance = CRYP;
@ -67,8 +69,9 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
#endif
if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR)
if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR) {
return (HAL_ERROR);
}
/* allow multi-instance of CRYP use: save context for CRYP HW module CR */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
@ -79,7 +82,10 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
volatile unsigned char *p = (unsigned char *)v;
while (n--) {
*p++ = 0;
}
}
@ -92,8 +98,9 @@ void mbedtls_aes_init( mbedtls_aes_context *ctx )
void mbedtls_aes_free(mbedtls_aes_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
}
/* Force the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_FORCE_RESET();
@ -150,7 +157,8 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
#if defined(MBEDTLS_CIPHER_MODE_CBC)
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
static int st_cbc_restore_context(mbedtls_aes_context *ctx){
static int st_cbc_restore_context(mbedtls_aes_context *ctx)
{
uint32_t tickstart;
tickstart = HAL_GetTick();
while ((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0) {
@ -169,28 +177,34 @@ static int st_hal_cryp_cbc( mbedtls_aes_context *ctx, uint32_t opmode, size_t le
ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init
/* At this moment only, we know we have CBC mode: Re-initialize AES
IP with proper parameters and apply key and IV for multi context usecase */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
ctx->hcryp_aes.Init.OperatingMode = opmode;
ctx->hcryp_aes.Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
if(HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0)
if (HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0) {
return ST_ERR_AES_BUSY;
}
return 0;
}
#else /* STM32F4 and STM32F7 */
static int st_cbc_restore_context(mbedtls_aes_context *ctx){
static int st_cbc_restore_context(mbedtls_aes_context *ctx)
{
/* allow multi-instance of CRYP use: restore context for CRYP hw module */
ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
/* Re-initialize AES processor with proper parameters
and (re-)apply key and IV for multi context usecases */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
}
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
return 0;
}
@ -205,17 +219,20 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
{
uint32_t tickstart;
uint32_t *iv_ptr = (uint32_t *)&iv[0];
if( length % 16 )
if (length % 16) {
return (MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH);
}
ctx->hcryp_aes.Init.pInitVect = &iv[0];
if (st_cbc_restore_context(ctx) != 0)
if (st_cbc_restore_context(ctx) != 0) {
return (ST_ERR_AES_BUSY);
}
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
if (mode == MBEDTLS_AES_DECRYPT) {
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0)
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) {
return ST_ERR_AES_BUSY;
}
/* Save the internal IV vector for multi context purpose */
tickstart = HAL_GetTick();
while ((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0) {
@ -230,8 +247,9 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
*iv_ptr++ = ctx->hcryp_aes.Instance->IVR1;
*iv_ptr++ = ctx->hcryp_aes.Instance->IVR0;
} else {
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0)
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) {
return ST_ERR_AES_BUSY;
}
memcpy(iv, output, 16); /* current output is the IV vector for the next call */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
}
@ -239,8 +257,9 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
#else
if (mode == MBEDTLS_AES_DECRYPT) {
if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK)
if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
/* Save the internal IV vector for multi context purpose */
tickstart = HAL_GetTick();
while ((ctx->hcryp_aes.Instance->SR & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM) {
@ -255,8 +274,9 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
*iv_ptr++ = ctx->hcryp_aes.Instance->IV1LR;
*iv_ptr++ = ctx->hcryp_aes.Instance->IV1RR;
} else {
if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK)
if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
memcpy(iv, output, 16); /* current output is the IV vector for the next call */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
}
@ -281,8 +301,9 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
if (mode == MBEDTLS_AES_DECRYPT) {
while (length--) {
if (n == 0)
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) {
return ST_ERR_AES_BUSY;
}
c = *input++;
*output++ = (unsigned char)(c ^ iv[n]);
@ -293,8 +314,9 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
} else {
while (length--) {
if (n == 0)
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) {
return ST_ERR_AES_BUSY;
}
iv[n] = *output++ = (unsigned char)(iv[n] ^ *input++);
@ -320,16 +342,19 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
while (length--) {
memcpy(ov, iv, 16);
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) {
return ST_ERR_AES_BUSY;
}
if( mode == MBEDTLS_AES_DECRYPT )
if (mode == MBEDTLS_AES_DECRYPT) {
ov[16] = *input;
}
c = *output++ = (unsigned char)(iv[0] ^ *input++);
if( mode == MBEDTLS_AES_ENCRYPT )
if (mode == MBEDTLS_AES_ENCRYPT) {
ov[16] = c;
}
memcpy(iv, ov + 1, 16);
}
@ -351,16 +376,17 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
int c, i;
size_t n = *nc_off;
while( length-- )
{
while (length--) {
if (n == 0) {
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ) != 0)
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block) != 0) {
return ST_ERR_AES_BUSY;
}
for (i = 16; i > 0; i--)
if( ++nonce_counter[i - 1] != 0 )
if (++nonce_counter[i - 1] != 0) {
break;
}
}
c = *input++;
*output++ = (unsigned char)(c ^ stream_block[n]);

3
features/mbedtls/targets/TARGET_STM/aes_alt.h
View File

@ -41,8 +41,7 @@ extern "C" {
* - to simplify key expansion in the 256-bit case by
* generating an extra round key
*/
typedef struct
{
typedef struct {
unsigned char aes_key[32]; /* Decryption key */
CRYP_HandleTypeDef hcryp_aes;
uint32_t ctx_save_cr; /* save context for multi-instance */

11
features/mbedtls/targets/TARGET_STM/md5_alt.c
View File

@ -24,8 +24,12 @@
#include "mbedtls/platform.h"
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = v; while( n-- ) *p++ = 0;
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = v;
while (n--) {
*p++ = 0;
}
}
static int st_md5_restore_hw_context(mbedtls_md5_context *ctx)
@ -79,8 +83,9 @@ void mbedtls_md5_init( mbedtls_md5_context *ctx )
void mbedtls_md5_free(mbedtls_md5_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
}
mbedtls_zeroize(ctx, sizeof(mbedtls_md5_context));
}

3
features/mbedtls/targets/TARGET_STM/md5_alt.h
View File

@ -41,8 +41,7 @@ extern "C" {
* ST_MD5_BLOCK_SIZE bytes per ST_MD5_BLOCK_SIZE bytes
* If MD5_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_MD5_Finish
*/
typedef struct
{
typedef struct {
HASH_HandleTypeDef hhash_md5;/*!< ST HAL HASH struct */
unsigned char sbuf[ST_MD5_BLOCK_SIZE]; /*!< MBEDTLS_MD5_BLOCK_SIZE buffer to store values so that algorithm is caled once the buffer is filled */
unsigned char sbuf_len; /*!< number of bytes to be processed in sbuf */

11
features/mbedtls/targets/TARGET_STM/sha1_alt.c
View File

@ -22,8 +22,12 @@
#include "mbedtls/platform.h"
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = (unsigned char *)v;
while (n--) {
*p++ = 0;
}
}
static int st_sha1_restore_hw_context(mbedtls_sha1_context *ctx)
@ -77,8 +81,9 @@ void mbedtls_sha1_init( mbedtls_sha1_context *ctx )
void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
}
mbedtls_zeroize(ctx, sizeof(mbedtls_sha1_context));
}

3
features/mbedtls/targets/TARGET_STM/sha1_alt.h
View File

@ -41,8 +41,7 @@ extern "C" {
* multiples of ST_SHA1_BLOCK_SIZE bytes
* If SHA1_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_SHA1_Finish
*/
typedef struct
{
typedef struct {
unsigned char sbuf[ST_SHA1_BLOCK_SIZE]; /*!< MBEDTLS_SHA1_BLOCK_SIZE buffer to store values so that algorithm is caled once the buffer is filled */
unsigned char sbuf_len; /*!< number of bytes remaining in sbuf to be processed */
HASH_HandleTypeDef hhash_sha1; /*!< ST HAL HASH struct */

11
features/mbedtls/targets/TARGET_STM/sha256_alt.c
View File

@ -23,8 +23,12 @@
#include "mbedtls/platform.h"
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = v; while( n-- ) *p++ = 0;
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = v;
while (n--) {
*p++ = 0;
}
}
static int st_sha256_restore_hw_context(mbedtls_sha256_context *ctx)
@ -77,8 +81,9 @@ void mbedtls_sha256_init( mbedtls_sha256_context *ctx )
void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
}
mbedtls_zeroize(ctx, sizeof(mbedtls_sha256_context));
}

3
features/mbedtls/targets/TARGET_STM/sha256_alt.h
View File

@ -40,8 +40,7 @@ extern "C" {
* ST_SHA256_BLOCK_SIZE bytes per ST_SHA256_BLOCK_SIZE bytes
* If sha256_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_SHA256_Finish
*/
typedef struct
{
typedef struct {
int is224; /*!< 0 => SHA-256, else SHA-224 */
HASH_HandleTypeDef hhash_sha256;
unsigned char sbuf[ST_SHA256_BLOCK_SIZE]; /*!< ST_SHA256_BLOCK_SIZE buffer to store values so that algorithm is called once the buffer is filled */

3
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/stm32f2_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,

3
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,

3
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,

3
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,

3
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/stm32f7_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,

15
features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.cpp
View File

@ -432,7 +432,8 @@ void STM32_EMAC::disable_interrupts(void)
* @param mac A 6-byte array to write the MAC address
*/
void mbed_mac_address(char *mac) {
void mbed_mac_address(char *mac)
{
if (mbed_otp_mac_address(mac)) {
return;
} else {
@ -441,11 +442,13 @@ void mbed_mac_address(char *mac) {
return;
}
__weak uint8_t mbed_otp_mac_address(char *mac) {
__weak uint8_t mbed_otp_mac_address(char *mac)
{
return 0;
}
void mbed_default_mac_address(char *mac) {
void mbed_default_mac_address(char *mac)
{
unsigned char ST_mac_addr[3] = {0x00, 0x80, 0xe1}; // default STMicro mac address
// Read unic id
@ -560,12 +563,14 @@ void STM32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
memory_manager = &mem_mngr;
}
STM32_EMAC &STM32_EMAC::get_instance() {
STM32_EMAC &STM32_EMAC::get_instance()
{
static STM32_EMAC emac;
return emac;
}
// Weak so a module can override
MBED_WEAK EMAC &EMAC::get_default_instance() {
MBED_WEAK EMAC &EMAC::get_default_instance()
{
return STM32_EMAC::get_instance();
}

6
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h
View File

@ -42,8 +42,7 @@
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
typedef struct {
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
@ -92,7 +91,8 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
USBHAL *USBHAL::instance;
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
USBHAL_Private_t *HALPriv = new (USBHAL_Private_t);
hpcd.Instance = USB;

9
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
View File

@ -44,8 +44,7 @@
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
typedef struct {
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
@ -71,8 +70,7 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
uint32_t len;
if (fifo == 0) {
len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ >> 16;
}
else {
} else {
len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
}
return len * 4;
@ -90,7 +88,8 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
USBHAL *USBHAL::instance;
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
USBHAL_Private_t *HALPriv = new (USBHAL_Private_t);
memset(&hpcd.Init, 0, sizeof(hpcd.Init));

89
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp
View File

@ -139,38 +139,46 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
/* hal pcd handler , used for STM32 HAL PCD Layer */
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
{
return 0;
}
USBHAL::~USBHAL(void) {
USBHAL::~USBHAL(void)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_PCD_DeInit(&hpcd);
delete HALPriv;
}
void USBHAL::connect(void) {
void USBHAL::connect(void)
{
NVIC_EnableIRQ(USBHAL_IRQn);
}
void USBHAL::disconnect(void) {
void USBHAL::disconnect(void)
{
NVIC_DisableIRQ(USBHAL_IRQn);
}
void USBHAL::configureDevice(void) {
void USBHAL::configureDevice(void)
{
// Not needed
}
void USBHAL::unconfigureDevice(void) {
void USBHAL::unconfigureDevice(void)
{
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
void USBHAL::setAddress(uint8_t address)
{
HAL_PCD_SetAddress(&hpcd, address);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags)
{
uint32_t epIndex = EP_ADDR(endpoint);
uint32_t type;
uint32_t len;
@ -193,7 +201,9 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag
type = 3;
break;
}
if (maxPacket > MAXTRANSFER_SIZE) return false;
if (maxPacket > MAXTRANSFER_SIZE) {
return false;
}
if (epIndex & 0x80) {
len = HAL_PCDEx_GetTxFiFo(&hpcd, epIndex & 0x7f);
MBED_ASSERT(len >= maxPacket);
@ -204,15 +214,18 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flag
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
void USBHAL::EP0setup(uint8_t *buffer)
{
memcpy(buffer, hpcd.Setup, MAX_PACKET_SIZE_SETUP);
memset(hpcd.Setup, 0, MAX_PACKET_SIZE_SETUP);
}
void USBHAL::EP0readStage(void) {
void USBHAL::EP0readStage(void)
{
}
void USBHAL::EP0read(void) {
void USBHAL::EP0read(void)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t epIndex = EP_ADDR(EP0OUT);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0;
@ -223,7 +236,8 @@ void USBHAL::EP0read(void) {
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, 0);
HALPriv->epComplete[EP0OUT] = 0;
@ -234,21 +248,25 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
/* check that endpoint maximum size is not exceeding TX fifo */
MBED_ASSERT(hpcd.IN_ep[0].maxpacket >= size);
endpointWrite(EP0IN, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
void USBHAL::EP0getWriteResult(void)
{
}
void USBHAL::EP0stall(void) {
void USBHAL::EP0stall(void)
{
stallEndpoint(EP0IN);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx;
@ -260,14 +278,16 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 0) {
/* no reception possible !!! */
bytesRead = 0;
return EP_COMPLETED;
}else if ((HALPriv->epComplete[endpoint]!=1))
} else if ((HALPriv->epComplete[endpoint] != 1)) {
return EP_PENDING;
}
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t *buff = (uint8_t *)HALPriv->pBufRx;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, epIndex);
@ -277,7 +297,8 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
HAL_StatusTypeDef ret;
@ -286,19 +307,24 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
ret = HAL_PCD_EP_Transmit(&hpcd, epIndex, data, size);
MBED_ASSERT(ret != HAL_BUSY);
// update the status
if (ret != HAL_OK) return EP_INVALID;
if (ret != HAL_OK) {
return EP_INVALID;
}
// fix me return is too simple
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 1)
if (HALPriv->epComplete[endpoint] == 1) {
return EP_COMPLETED;
}
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
void USBHAL::stallEndpoint(uint8_t endpoint)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_StatusTypeDef ret;
HALPriv->epComplete[endpoint] = 0;
@ -306,25 +332,30 @@ void USBHAL::stallEndpoint(uint8_t endpoint) {
MBED_ASSERT(ret != HAL_BUSY);
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
void USBHAL::unstallEndpoint(uint8_t endpoint)
{
HAL_StatusTypeDef ret;
ret = HAL_PCD_EP_ClrStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret != HAL_BUSY);
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
bool USBHAL::getEndpointStallState(uint8_t endpoint)
{
return false;
}
void USBHAL::remoteWakeup(void) {
void USBHAL::remoteWakeup(void)
{
}
void USBHAL::_usbisr(void) {
void USBHAL::_usbisr(void)
{
instance->usbisr();
}
void USBHAL::usbisr(void) {
void USBHAL::usbisr(void)
{
HAL_PCD_IRQHandler(&instance->hpcd);
}

90
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp
View File

@ -32,11 +32,13 @@ static uint32_t rxFifoCount = 0;
static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
{
return 0;
}
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP1_IN_callback;
@ -94,32 +96,39 @@ USBHAL::USBHAL(void) {
NVIC_SetPriority(OTG_FS_IRQn, 1);
}
USBHAL::~USBHAL(void) {
USBHAL::~USBHAL(void)
{
}
void USBHAL::connect(void) {
void USBHAL::connect(void)
{
NVIC_EnableIRQ(OTG_FS_IRQn);
}
void USBHAL::disconnect(void) {
void USBHAL::disconnect(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
}
void USBHAL::configureDevice(void) {
void USBHAL::configureDevice(void)
{
// Not needed
}
void USBHAL::unconfigureDevice(void) {
void USBHAL::unconfigureDevice(void)
{
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
void USBHAL::setAddress(uint8_t address)
{
OTG_FS->DREGS.DCFG |= (address << 4);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
uint32_t flags) {
uint32_t flags)
{
uint32_t epIndex = endpoint >> 1;
uint32_t type;
@ -151,8 +160,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
if (endpoint == EP0IN) {
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
else {
} else {
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
@ -169,8 +177,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
}
else { // Out endpoint
} else { // Out endpoint
// Set the out EP specific control settings
control |= (1 << 26); // CNAK
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
@ -182,17 +189,21 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
void USBHAL::EP0setup(uint8_t *buffer)
{
memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
}
void USBHAL::EP0readStage(void) {
void USBHAL::EP0readStage(void)
{
}
void USBHAL::EP0read(void) {
void USBHAL::EP0read(void)
{
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
uint32_t *buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
@ -203,14 +214,17 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
endpointWrite(0, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
void USBHAL::EP0getWriteResult(void)
{
}
void USBHAL::EP0stall(void) {
void USBHAL::EP0stall(void)
{
// If we stall the out endpoint here then we have problems transferring
// and setup requests after the (stalled) get device qualifier requests.
// TODO: Find out if this is correct behavior, or whether we are doing
@ -219,7 +233,8 @@ void USBHAL::EP0stall(void) {
// stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
uint32_t epIndex = endpoint >> 1;
uint32_t size = (1 << 19) | // 1 packet
(maximumSize << 0); // Packet size
@ -234,7 +249,8 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead)
{
if (!(epComplete & (1 << endpoint))) {
return EP_PENDING;
}
@ -249,7 +265,8 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
uint32_t epIndex = endpoint >> 1;
OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
(size << 0); // Size of packet
@ -268,7 +285,8 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
if (epComplete & (1 << endpoint)) {
epComplete &= ~(1 << endpoint);
return EP_COMPLETED;
@ -277,36 +295,41 @@ EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
void USBHAL::stallEndpoint(uint8_t endpoint)
{
if (endpoint & 0x1) { // In EP
OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
else { // Out EP
} else { // Out EP
OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
void USBHAL::unstallEndpoint(uint8_t endpoint)
{
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
bool USBHAL::getEndpointStallState(uint8_t endpoint)
{
return false;
}
void USBHAL::remoteWakeup(void) {
void USBHAL::remoteWakeup(void)
{
}
void USBHAL::_usbisr(void) {
void USBHAL::_usbisr(void)
{
instance->usbisr();
}
void USBHAL::usbisr(void) {
void USBHAL::usbisr(void)
{
if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
suspendStateChanged(1);
};
@ -363,8 +386,7 @@ void USBHAL::usbisr(void) {
// Out packet
if (endpoint == EP0OUT) {
EP0out();
}
else {
} else {
epComplete |= (1 << endpoint);
if ((instance->*(epCallback[endpoint - 2]))()) {
epComplete &= ~(1 << endpoint);

21
features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h
View File

@ -28,8 +28,7 @@
#ifndef __USB_OTG_REGS_H__
#define __USB_OTG_REGS_H__
typedef struct //000h
{
typedef struct { //000h
__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
@ -51,8 +50,7 @@ typedef struct //000h
}
USB_OTG_GREGS;
typedef struct // 800h
{
typedef struct { // 800h
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
@ -70,8 +68,7 @@ typedef struct // 800h
}
USB_OTG_DREGS;
typedef struct
{
typedef struct {
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
@ -83,8 +80,7 @@ typedef struct
}
USB_OTG_INEPREGS;
typedef struct
{
typedef struct {
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
@ -94,8 +90,7 @@ typedef struct
}
USB_OTG_OUTEPREGS;
typedef struct
{
typedef struct {
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
@ -106,8 +101,7 @@ typedef struct
}
USB_OTG_HREGS;
typedef struct
{
typedef struct {
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
@ -117,8 +111,7 @@ typedef struct
}
USB_OTG_HC_REGS;
typedef struct
{
typedef struct {
USB_OTG_GREGS GREGS;
uint32_t RESERVED0[188];
USB_OTG_HREGS HREGS;

6
targets/TARGET_STM/TARGET_STM32F0/analogout_device.c
View File

@ -35,7 +35,8 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
__HAL_RCC_DAC1_FORCE_RESET();
__HAL_RCC_DAC1_RELEASE_RESET();

5
targets/TARGET_STM/TARGET_STM32F0/pin_device.h
View File

@ -60,10 +60,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F0/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32F0/serial_device.c
View File

@ -569,13 +569,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
}

3
targets/TARGET_STM/TARGET_STM32F0/spi_api.c
View File

@ -46,7 +46,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
/* SPI_1, SPI_2. Source CLK is PCKL1 */
return HAL_RCC_GetPCLK1Freq();
}

9
targets/TARGET_STM/TARGET_STM32F1/pin_device.h
View File

@ -102,19 +102,22 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
switch (pull_config) {
case GPIO_PULLUP:
if (function == LL_GPIO_MODE_FLOATING)
if (function == LL_GPIO_MODE_FLOATING) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
}
LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
break;
case GPIO_PULLDOWN:
if (function == LL_GPIO_MODE_FLOATING)
if (function == LL_GPIO_MODE_FLOATING) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
}
LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
break;
default:
/* Input+NoPull = Floating for F1 family */
if (function == LL_GPIO_MODE_INPUT)
if (function == LL_GPIO_MODE_INPUT) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_FLOATING);
}
break;
}
}

3
targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM1_BASE)
{PWM_1, PWMOUT_ON_APB2},
#endif

6
targets/TARGET_STM/TARGET_STM32F1/serial_device.c
View File

@ -443,13 +443,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {

3
targets/TARGET_STM/TARGET_STM32F1/spi_api.c
View File

@ -46,7 +46,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

5
targets/TARGET_STM/TARGET_STM32F2/pin_device.h
View File

@ -130,10 +130,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F2/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32F2/serial_device.c
View File

@ -526,13 +526,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {

3
targets/TARGET_STM/TARGET_STM32F2/spi_api.c
View File

@ -48,7 +48,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

6
targets/TARGET_STM/TARGET_STM32F3/analogin_device.c
View File

@ -170,8 +170,7 @@ uint16_t adc_read(analogin_t *obj)
if ((ADCName)obj->handle.Instance == ADC_1) {
sConfig.Channel = ADC_CHANNEL_VOPAMP1;
sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5;
}
else {
} else {
sConfig.Channel = ADC_CHANNEL_15;
}
break;
@ -179,8 +178,7 @@ uint16_t adc_read(analogin_t *obj)
if ((ADCName)obj->handle.Instance == ADC_1) {
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5;
}
else {
} else {
sConfig.Channel = ADC_CHANNEL_16;
}
break;

14
targets/TARGET_STM/TARGET_STM32F3/analogout_device.c
View File

@ -39,7 +39,8 @@
static int pa4_used = 0;
static int pa5_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -115,10 +116,15 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->pin == PA_4) pa4_used = 0;
if (obj->pin == PA_5) pa5_used = 0;
if (obj->pin == PA_4) {
pa4_used = 0;
}
if (obj->pin == PA_5) {
pa5_used = 0;
}
if ((pa4_used == 0) && (pa5_used == 0)) {
__HAL_RCC_DAC1_FORCE_RESET();

5
targets/TARGET_STM/TARGET_STM32F3/pin_device.h
View File

@ -61,10 +61,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32F3/serial_device.c
View File

@ -486,13 +486,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
}

3
targets/TARGET_STM/TARGET_STM32F3/spi_api.c
View File

@ -48,7 +48,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

5
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c
View File

@ -196,10 +196,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 1
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 16 MHz with xtal
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz with external clock (MCO)
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c
View File

@ -192,10 +192,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 1
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c
View File

@ -203,10 +203,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 1
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c
View File

@ -202,10 +202,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 1
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)
}
#endif
return 1; // OK

6
targets/TARGET_STM/TARGET_STM32F4/analogout_device.c
View File

@ -35,7 +35,8 @@
#include "stm32f4xx_hal.h"
#include "PeripheralPins.h"
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
}
#endif // DEVICE_ANALOGOUT

5
targets/TARGET_STM/TARGET_STM32F4/pin_device.h
View File

@ -129,10 +129,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32F4/serial_device.c
View File

@ -571,13 +571,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {

3
targets/TARGET_STM/TARGET_STM32F4/spi_api.c
View File

@ -49,7 +49,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

6
targets/TARGET_STM/TARGET_STM32F7/analogout_device.c
View File

@ -35,7 +35,8 @@
#include "stm32f7xx_hal.h"
#include "PeripheralPins.h"
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
}

9
targets/TARGET_STM/TARGET_STM32F7/flash_api.c
View File

@ -49,14 +49,12 @@ int32_t flash_init(flash_t *obj)
/* Allow Access to option bytes sector */
HAL_FLASH_OB_Lock();
#if MBED_CONF_TARGET_FLASH_DUAL_BANK
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK)
{
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK) {
error("The Dual Bank mode option byte (nDBANK) must be enabled (box unchecked)\n");
return -1;
}
#else // SINGLE BANK
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK)
{
if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK) {
error("The Dual Bank mode option byte (nDBANK) must be disabled (box checked)\n");
return -1;
}
@ -219,8 +217,7 @@ static uint32_t GetSector(uint32_t address)
sector += 12 + (tmp >> 14);
} else if (address < ADDR_FLASH_SECTOR_17) { // Sector 16
sector += FLASH_SECTOR_16;
}
else { // Sectors 17 to 23
} else { // Sectors 17 to 23
tmp = address - ADDR_FLASH_SECTOR_12;
sector += 16 + (tmp >> 17);
}

5
targets/TARGET_STM/TARGET_STM32F7/pin_device.h
View File

@ -131,10 +131,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32F7/serial_device.c
View File

@ -524,13 +524,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
}

3
targets/TARGET_STM/TARGET_STM32F7/spi_api.c
View File

@ -48,7 +48,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

3
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/system_clock.c
View File

@ -200,8 +200,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
if (bypass == 0) { // Xtal used
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_2); // 16 MHz
}
else { // External clock used
} else { // External clock used
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_4); // 8 MHz
}
#endif

3
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c
View File

@ -84,8 +84,7 @@ void SystemInit (void)
*/
void SetSysClock(void)
{
if (SetSysClock_PLL_HSI() == 0)
{
if (SetSysClock_PLL_HSI() == 0) {
while (1) {
MBED_ASSERT(1);
}

14
targets/TARGET_STM/TARGET_STM32L0/analogout_device.c
View File

@ -39,7 +39,8 @@
static int channel1_used = 0;
static int channel2_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -96,11 +97,16 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->channel == DAC_CHANNEL_1) channel1_used = 0;
if (obj->channel == DAC_CHANNEL_1) {
channel1_used = 0;
}
#if defined(DAC_CHANNEL_2)
if (obj->channel == DAC_CHANNEL_2) channel2_used = 0;
if (obj->channel == DAC_CHANNEL_2) {
channel2_used = 0;
}
#endif
if ((channel1_used == 0) && (channel2_used == 0)) {
__DAC_FORCE_RESET();

12
targets/TARGET_STM/TARGET_STM32L0/flash_api.c
View File

@ -148,7 +148,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
return status;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
return MBED_FLASH_INVALID_SIZE;
} else {
@ -157,16 +158,19 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {
}
}
uint32_t flash_get_page_size(const flash_t *obj) {
uint32_t flash_get_page_size(const flash_t *obj)
{
/* Page size is the minimum programable size, which 4 bytes */
return 4;
}
uint32_t flash_get_start_address(const flash_t *obj) {
uint32_t flash_get_start_address(const flash_t *obj)
{
return FLASH_BASE;
}
uint32_t flash_get_size(const flash_t *obj) {
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_SIZE;
}

5
targets/TARGET_STM/TARGET_STM32L0/pin_device.h
View File

@ -60,10 +60,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32L0/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

3
targets/TARGET_STM/TARGET_STM32L0/serial_device.c
View File

@ -480,7 +480,8 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
}

3
targets/TARGET_STM/TARGET_STM32L0/spi_api.c
View File

@ -49,7 +49,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

18
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c
View File

@ -49,7 +49,8 @@ enum {
word_write
};
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
@ -61,7 +62,8 @@ static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
}
}
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data)
{
if (addr > XDOT_EEPROM_SIZE - 2) {
return -1;
}
@ -73,7 +75,8 @@ static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
}
}
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data)
{
if (addr > XDOT_EEPROM_SIZE - 4) {
return -1;
}
@ -85,7 +88,8 @@ static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
}
}
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) {
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
@ -96,7 +100,8 @@ static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) {
}
int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
uint32_t bytes_written = 0;
if (addr + size > XDOT_EEPROM_SIZE) {
@ -261,7 +266,8 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
return 0;
}
int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
if (addr + size > XDOT_EEPROM_SIZE) {
return -1;
}

33
targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c
View File

@ -37,15 +37,18 @@ static uint32_t portB[6];
static uint32_t portC[6];
static uint32_t portH[6];
void xdot_disable_systick_int() {
void xdot_disable_systick_int()
{
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
void xdot_enable_systick_int() {
void xdot_enable_systick_int()
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
void xdot_save_gpio_state() {
void xdot_save_gpio_state()
{
portA[0] = GPIOA->MODER;
portA[1] = GPIOA->OTYPER;
portA[2] = GPIOA->OSPEEDR;
@ -75,7 +78,8 @@ void xdot_save_gpio_state() {
portH[5] = GPIOH->AFR[1];
}
void xdot_restore_gpio_state() {
void xdot_restore_gpio_state()
{
GPIOA->MODER = portA[0];
GPIOA->OTYPER = portA[1];
GPIOA->OSPEEDR = portA[2];
@ -105,7 +109,8 @@ void xdot_restore_gpio_state() {
GPIOH->AFR[1] = portH[5];
}
void xdot_enter_stop_mode() {
void xdot_enter_stop_mode()
{
GPIO_InitTypeDef GPIO_InitStruct;
// disable ADC and DAC - they can consume power in stop mode
@ -271,18 +276,22 @@ void xdot_enter_stop_mode() {
DAC->CR |= DAC_CR_EN2;
}
void xdot_enter_standby_mode() {
void xdot_enter_standby_mode()
{
// enable ULP and enable fast wakeup
HAL_PWREx_EnableUltraLowPower();
HAL_PWREx_EnableFastWakeUp();
// disable HSI, MSI, and LSI if they are running
if (RCC->CR & RCC_CR_HSION)
if (RCC->CR & RCC_CR_HSION) {
RCC->CR &= ~RCC_CR_HSION;
if (RCC->CR & RCC_CR_MSION)
}
if (RCC->CR & RCC_CR_MSION) {
RCC->CR &= ~RCC_CR_MSION;
if (RCC->CSR & RCC_CSR_LSION)
}
if (RCC->CSR & RCC_CSR_LSION) {
RCC->CSR &= ~RCC_CSR_LSION;
}
// make sure wakeup and standby flags are cleared
@ -293,10 +302,12 @@ void xdot_enter_standby_mode() {
HAL_PWR_EnterSTANDBYMode();
}
void xdot_enable_standby_wake_pin() {
void xdot_enable_standby_wake_pin()
{
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
}
void xdot_disable_standby_wake_pin() {
void xdot_disable_standby_wake_pin()
{
HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
}

18
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.c
View File

@ -49,7 +49,8 @@ enum {
word_write
};
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
@ -61,7 +62,8 @@ static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) {
}
}
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data)
{
if (addr > XDOT_EEPROM_SIZE - 2) {
return -1;
}
@ -73,7 +75,8 @@ static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) {
}
}
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
static int xdot_eeprom_write_word(uint32_t addr, uint32_t data)
{
if (addr > XDOT_EEPROM_SIZE - 4) {
return -1;
}
@ -85,7 +88,8 @@ static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) {
}
}
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) {
static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data)
{
if (addr > XDOT_EEPROM_SIZE - 1) {
return -1;
}
@ -96,7 +100,8 @@ static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) {
}
int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
uint32_t bytes_written = 0;
if (addr + size > XDOT_EEPROM_SIZE) {
@ -261,7 +266,8 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
return 0;
}
int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size) {
int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size)
{
if (addr + size > XDOT_EEPROM_SIZE) {
return -1;
}

33
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c
View File

@ -37,15 +37,18 @@ static uint32_t portB[6];
static uint32_t portC[6];
static uint32_t portH[6];
void xdot_disable_systick_int() {
void xdot_disable_systick_int()
{
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
void xdot_enable_systick_int() {
void xdot_enable_systick_int()
{
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
void xdot_save_gpio_state() {
void xdot_save_gpio_state()
{
portA[0] = GPIOA->MODER;
portA[1] = GPIOA->OTYPER;
portA[2] = GPIOA->OSPEEDR;
@ -75,7 +78,8 @@ void xdot_save_gpio_state() {
portH[5] = GPIOH->AFR[1];
}
void xdot_restore_gpio_state() {
void xdot_restore_gpio_state()
{
GPIOA->MODER = portA[0];
GPIOA->OTYPER = portA[1];
GPIOA->OSPEEDR = portA[2];
@ -105,7 +109,8 @@ void xdot_restore_gpio_state() {
GPIOH->AFR[1] = portH[5];
}
void xdot_enter_stop_mode() {
void xdot_enter_stop_mode()
{
GPIO_InitTypeDef GPIO_InitStruct;
// disable ADC and DAC - they can consume power in stop mode
@ -271,18 +276,22 @@ void xdot_enter_stop_mode() {
DAC->CR |= DAC_CR_EN2;
}
void xdot_enter_standby_mode() {
void xdot_enter_standby_mode()
{
// enable ULP and enable fast wakeup
HAL_PWREx_EnableUltraLowPower();
HAL_PWREx_EnableFastWakeUp();
// disable HSI, MSI, and LSI if they are running
if (RCC->CR & RCC_CR_HSION)
if (RCC->CR & RCC_CR_HSION) {
RCC->CR &= ~RCC_CR_HSION;
if (RCC->CR & RCC_CR_MSION)
}
if (RCC->CR & RCC_CR_MSION) {
RCC->CR &= ~RCC_CR_MSION;
if (RCC->CSR & RCC_CSR_LSION)
}
if (RCC->CSR & RCC_CSR_LSION) {
RCC->CSR &= ~RCC_CSR_LSION;
}
// make sure wakeup and standby flags are cleared
@ -293,11 +302,13 @@ void xdot_enter_standby_mode() {
HAL_PWR_EnterSTANDBYMode();
}
void xdot_enable_standby_wake_pin() {
void xdot_enable_standby_wake_pin()
{
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1);
}
void xdot_disable_standby_wake_pin() {
void xdot_disable_standby_wake_pin()
{
HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1);
}

14
targets/TARGET_STM/TARGET_STM32L1/analogout_device.c
View File

@ -39,7 +39,8 @@
static int pa4_used = 0;
static int pa5_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
@ -94,10 +95,15 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->pin == PA_4) pa4_used = 0;
if (obj->pin == PA_5) pa5_used = 0;
if (obj->pin == PA_4) {
pa4_used = 0;
}
if (obj->pin == PA_5) {
pa5_used = 0;
}
if ((pa4_used == 0) && (pa5_used == 0)) {
__DAC_FORCE_RESET();
__DAC_RELEASE_RESET();

5
targets/TARGET_STM/TARGET_STM32L1/pin_device.h
View File

@ -60,10 +60,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32L1/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32L1/serial_device.c
View File

@ -479,13 +479,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {

3
targets/TARGET_STM/TARGET_STM32L1/spi_api.c
View File

@ -48,7 +48,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c
View File

@ -232,10 +232,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c
View File

@ -232,10 +232,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c
View File

@ -232,10 +232,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c
View File

@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c
View File

@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c
View File

@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c
View File

@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c
View File

@ -231,10 +231,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c
View File

@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c
View File

@ -226,10 +226,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

5
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c
View File

@ -226,10 +226,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
// Output clock on MCO1 pin(PA8) for debugging purpose
#if DEBUG_MCO == 2
if (bypass == 0)
if (bypass == 0) {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
else
} else {
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
}
#endif
return 1; // OK

14
targets/TARGET_STM/TARGET_STM32L4/analogout_device.c
View File

@ -39,7 +39,8 @@
static int channel1_used = 0;
static int channel2_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -100,11 +101,16 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->channel == DAC_CHANNEL_1) channel1_used = 0;
if (obj->channel == DAC_CHANNEL_1) {
channel1_used = 0;
}
#if defined(DAC_CHANNEL_2)
if (obj->channel == DAC_CHANNEL_2) channel2_used = 0;
if (obj->channel == DAC_CHANNEL_2) {
channel2_used = 0;
}
#endif
if ((channel1_used == 0) && (channel2_used == 0)) {

12
targets/TARGET_STM/TARGET_STM32L4/flash_api.c
View File

@ -238,7 +238,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
* @param address The sector starting address
* @return The size of a sector
*/
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
/* considering 1 sector = 1 page */
if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
return MBED_FLASH_INVALID_SIZE;
@ -253,7 +254,8 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {
* @param address The page starting address
* @return The size of a page
*/
uint32_t flash_get_page_size(const flash_t *obj) {
uint32_t flash_get_page_size(const flash_t *obj)
{
/* Page size is the minimum programable size, which 8 bytes */
return 8;
}
@ -263,7 +265,8 @@ uint32_t flash_get_page_size(const flash_t *obj) {
* @param obj The flash object
* @return The start address for the flash region
*/
uint32_t flash_get_start_address(const flash_t *obj) {
uint32_t flash_get_start_address(const flash_t *obj)
{
return FLASH_BASE;
}
@ -272,7 +275,8 @@ uint32_t flash_get_start_address(const flash_t *obj) {
* @param obj The flash object
* @return The flash region size
*/
uint32_t flash_get_size(const flash_t *obj) {
uint32_t flash_get_size(const flash_t *obj)
{
return FLASH_SIZE;
}

5
targets/TARGET_STM/TARGET_STM32L4/pin_device.h
View File

@ -60,10 +60,11 @@ static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t a
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

6
targets/TARGET_STM/TARGET_STM32L4/serial_device.c
View File

@ -503,13 +503,15 @@ uint8_t serial_rx_active(serial_t *obj)
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {

3
targets/TARGET_STM/TARGET_STM32L4/spi_api.c
View File

@ -47,7 +47,8 @@
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;

15
targets/TARGET_STM/gpio_api.c
View File

@ -36,7 +36,8 @@
extern const uint32_t ll_pin_defines[16];
// Enable GPIO clock and return GPIO base address
GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) {
GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx)
{
uint32_t gpio_add = 0;
switch (port_idx) {
case PortA:
@ -112,7 +113,8 @@ GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) {
return (GPIO_TypeDef *) gpio_add;
}
uint32_t gpio_set(PinName pin) {
uint32_t gpio_set(PinName pin)
{
MBED_ASSERT(pin != (PinName)NC);
pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
@ -121,7 +123,8 @@ uint32_t gpio_set(PinName pin) {
}
void gpio_init(gpio_t *obj, PinName pin) {
void gpio_init(gpio_t *obj, PinName pin)
{
obj->pin = pin;
if (pin == (PinName)NC) {
return;
@ -145,11 +148,13 @@ void gpio_init(gpio_t *obj, PinName pin) {
#endif
}
void gpio_mode(gpio_t *obj, PinMode mode) {
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
inline void gpio_dir(gpio_t *obj, PinDirection direction) {
inline void gpio_dir(gpio_t *obj, PinDirection direction)
{
if (direction == PIN_INPUT) {
LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT);
} else {

4
targets/TARGET_STM/gpio_irq_api.c
View File

@ -168,7 +168,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
gpio_channel_t *gpio_channel;
uint32_t gpio_idx;
if (pin == NC) return -1;
if (pin == NC) {
return -1;
}
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();

3
targets/TARGET_STM/hal_tick_16b.c
View File

@ -25,7 +25,8 @@ volatile uint32_t PreviousVal = 0;
void us_ticker_irq_handler(void);
#if defined(TARGET_STM32F0)
void timer_update_irq_handler(void) {
void timer_update_irq_handler(void)
{
#else
void timer_irq_handler(void)
{

147
targets/TARGET_STM/i2c_api.c
View File

@ -122,7 +122,8 @@ static void i2c5_irq(void)
}
#endif
void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
void i2c_ev_err_enable(i2c_t *obj, uint32_t handler)
{
struct i2c_s *obj_s = I2C_S(obj);
IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
@ -149,7 +150,8 @@ void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) {
NVIC_EnableIRQ(irq_error_n);
}
void i2c_ev_err_disable(i2c_t *obj) {
void i2c_ev_err_disable(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
IRQn_Type irq_event_n = obj_s->event_i2cIRQ;
IRQn_Type irq_error_n = obj_s->error_i2cIRQ;
@ -196,7 +198,8 @@ uint32_t i2c_get_irq_handler(i2c_t *obj)
return handler;
}
void i2c_hw_reset(i2c_t *obj) {
void i2c_hw_reset(i2c_t *obj)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
@ -255,7 +258,8 @@ void i2c_sw_reset(i2c_t *obj)
handle->Instance->CR1 |= I2C_CR1_PE;
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
struct i2c_s *obj_s = I2C_S(obj);
@ -323,8 +327,9 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
// I2C configuration
// Default hz value used for timeout computation
if(!obj_s->hz)
if (!obj_s->hz) {
obj_s->hz = 100000; // 100 kHz per default
}
// Reset to clear pending flags if any
i2c_hw_reset(obj);
@ -429,7 +434,8 @@ void i2c_frequency(i2c_t *obj, int hz)
obj_s->hz = hz;
}
i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c)
{
/* Aim of the function is to get i2c_s pointer using hi2c pointer */
/* Highly inspired from magical linux kernel's "container_of" */
/* (which was not directly used since not compatible with IAR toolchain) */
@ -442,7 +448,8 @@ i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){
return (obj);
}
void i2c_reset(i2c_t *obj) {
void i2c_reset(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
/* As recommended in i2c_api.h, mainly send stop */
i2c_stop(obj);
@ -456,7 +463,8 @@ void i2c_reset(i2c_t *obj) {
* There are 2 different IPs version that need to be supported
*/
#ifdef I2C_IP_VERSION_V1
int i2c_start(i2c_t *obj) {
int i2c_start(i2c_t *obj)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
@ -488,7 +496,8 @@ int i2c_start(i2c_t *obj) {
return 0;
}
int i2c_stop(i2c_t *obj) {
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c;
@ -498,13 +507,15 @@ int i2c_stop(i2c_t *obj) {
/* In case of mixed usage of the APIs (unitary + SYNC)
* re-init HAL state
*/
if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME)
if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) {
i2c_init(obj, obj_s->sda, obj_s->scl);
}
return 0;
}
int i2c_byte_read(i2c_t *obj, int last) {
int i2c_byte_read(i2c_t *obj, int last)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
@ -529,7 +540,8 @@ int i2c_byte_read(i2c_t *obj, int last) {
return (int)handle->Instance->DR;
}
int i2c_byte_write(i2c_t *obj, int data) {
int i2c_byte_write(i2c_t *obj, int data)
{
int timeout;
struct i2c_s *obj_s = I2C_S(obj);
@ -547,8 +559,7 @@ int i2c_byte_write(i2c_t *obj, int data) {
}
}
if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET)
{
if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET) {
__HAL_I2C_CLEAR_ADDRFLAG(handle);
}
@ -557,14 +568,16 @@ int i2c_byte_write(i2c_t *obj, int data) {
#endif //I2C_IP_VERSION_V1
#ifdef I2C_IP_VERSION_V2
int i2c_start(i2c_t *obj) {
int i2c_start(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
/* This I2C IP doesn't */
obj_s->pending_start = 1;
return 0;
}
int i2c_stop(i2c_t *obj) {
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int timeout = FLAG_TIMEOUT;
@ -609,7 +622,8 @@ int i2c_stop(i2c_t *obj) {
return 0;
}
int i2c_byte_read(i2c_t *obj, int last) {
int i2c_byte_read(i2c_t *obj, int last)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int timeout = FLAG_TIMEOUT;
@ -654,7 +668,8 @@ int i2c_byte_read(i2c_t *obj, int last) {
return data;
}
int i2c_byte_write(i2c_t *obj, int data) {
int i2c_byte_write(i2c_t *obj, int data)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int timeout = FLAG_TIMEOUT;
@ -719,7 +734,8 @@ int i2c_byte_write(i2c_t *obj, int data) {
/*
* SYNC APIS
*/
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int count = I2C_ERROR_BUS_BUSY, ret = 0;
@ -729,17 +745,19 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
uint32_t op2 = I2C_LAST_FRAME;
if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
if (stop)
if (stop) {
obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
else
} else {
obj_s->XferOperation = I2C_FIRST_FRAME;
}
} else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
(obj_s->XferOperation == I2C_NEXT_FRAME)) {
if (stop)
if (stop) {
obj_s->XferOperation = I2C_LAST_FRAME;
else
} else {
obj_s->XferOperation = I2C_NEXT_FRAME;
}
}
obj_s->event = 0;
@ -773,7 +791,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
return count;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int count = I2C_ERROR_BUS_BUSY, ret = 0;
@ -783,17 +802,19 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
uint32_t op2 = I2C_LAST_FRAME;
if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
if (stop)
if (stop) {
obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
else
} else {
obj_s->XferOperation = I2C_FIRST_FRAME;
}
} else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
(obj_s->XferOperation == I2C_NEXT_FRAME)) {
if (stop)
if (stop) {
obj_s->XferOperation = I2C_LAST_FRAME;
else
} else {
obj_s->XferOperation = I2C_NEXT_FRAME;
}
}
obj_s->event = 0;
@ -824,7 +845,8 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
return count;
}
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(hi2c);
struct i2c_s *obj_s = I2C_S(obj);
@ -839,8 +861,7 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
}
HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t *)obj->rx_buff.buffer, obj->rx_buff.length, obj_s->XferOperation);
}
else
} else
#endif
{
/* Set event flag */
@ -848,7 +869,8 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){
}
}
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(hi2c);
struct i2c_s *obj_s = I2C_S(obj);
@ -857,7 +879,8 @@ void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){
obj_s->event = I2C_EVENT_TRANSFER_COMPLETE;
}
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(hi2c);
struct i2c_s *obj_s = I2C_S(obj);
@ -865,8 +888,9 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
I2C_HandleTypeDef *handle = &(obj_s->handle);
uint32_t address = 0;
/* Store address to handle it after reset */
if(obj_s->slave)
if (obj_s->slave) {
address = handle->Init.OwnAddress1;
}
#endif
DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index);
@ -888,7 +912,8 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){
#if DEVICE_I2CSLAVE
/* SLAVE API FUNCTIONS */
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
@ -901,7 +926,8 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
HAL_I2C_EnableListen_IT(handle);
}
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
@ -922,7 +948,8 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) {
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(hi2c);
struct i2c_s *obj_s = I2C_S(obj);
@ -937,14 +964,16 @@ void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, ui
}
}
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(I2cHandle);
struct i2c_s *obj_s = I2C_S(obj);
obj_s->pending_slave_tx_master_rx = 0;
}
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(I2cHandle);
struct i2c_s *obj_s = I2C_S(obj);
@ -957,7 +986,8 @@ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
HAL_I2C_EnableListen_IT(hi2c);
}
int i2c_slave_receive(i2c_t *obj) {
int i2c_slave_receive(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
int retValue = NoData;
@ -973,7 +1003,8 @@ int i2c_slave_receive(i2c_t *obj) {
return (retValue);
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int count = 0;
@ -998,7 +1029,8 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) {
return count;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
int count = 0;
@ -1027,7 +1059,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) {
#if DEVICE_I2C_ASYNCH
/* ASYNCH MASTER API FUNCTIONS */
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Get object ptr based on handler ptr */
i2c_t *obj = get_i2c_obj(hi2c);
struct i2c_s *obj_s = I2C_S(obj);
@ -1041,7 +1074,8 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){
obj_s->event = I2C_EVENT_ERROR;
}
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) {
void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
{
// TODO: DMA usage is currently ignored by this way
(void) hint;
@ -1073,17 +1107,19 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
uint32_t op2 = I2C_LAST_FRAME;
if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
if (stop)
if (stop) {
obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
else
} else {
obj_s->XferOperation = I2C_FIRST_FRAME;
}
} else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
(obj_s->XferOperation == I2C_NEXT_FRAME)) {
if (stop)
if (stop) {
obj_s->XferOperation = I2C_LAST_FRAME;
else
} else {
obj_s->XferOperation = I2C_NEXT_FRAME;
}
}
if (tx_length > 0) {
HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, obj_s->XferOperation);
@ -1091,8 +1127,7 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
if (rx_length > 0) {
HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *)rx, rx_length, obj_s->XferOperation);
}
}
else if (tx_length && rx_length) {
} else if (tx_length && rx_length) {
/* Two steps operation, don't modify XferOperation, keep it for next step */
// Trick to remove compiler warning "left and right operands are identical" in some cases
uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
@ -1107,7 +1142,8 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
}
uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
uint32_t i2c_irq_handler_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
@ -1119,20 +1155,21 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj) {
return (obj_s->event & obj_s->available_events);
}
uint8_t i2c_active(i2c_t *obj) {
uint8_t i2c_active(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);
if (handle->State == HAL_I2C_STATE_READY) {
return 0;
}
else {
} else {
return 1;
}
}
void i2c_abort_asynch(i2c_t *obj) {
void i2c_abort_asynch(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
I2C_HandleTypeDef *handle = &(obj_s->handle);

3
targets/TARGET_STM/pinmap.c
View File

@ -141,8 +141,7 @@ void pin_mode(PinName pin, PinMode mode)
GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin);
if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE))
{
if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE)) {
if ((mode == OpenDrainNoPull) || (mode == OpenDrainPullUp) || (mode == OpenDrainPullDown)) {
LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN);
} else {

3
targets/TARGET_STM/pwmout_api.c
View File

@ -267,8 +267,9 @@ void pwmout_period_us(pwmout_t* obj, int us)
i++;
}
if(pwm_apb_map_table[i].pwm == 0)
if (pwm_apb_map_table[i].pwm == 0) {
error("Unknown PWM instance");
}
if (pwm_apb_map_table[i].pwmoutApb == PWMOUT_ON_APB1) {
PclkFreq = HAL_RCC_GetPCLK1Freq();

6
targets/TARGET_STM/serial_api.c
View File

@ -57,8 +57,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
if ((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX)) {
stdio_config = 1;
}
else {
} else {
if (uart_tx == pinmap_peripheral(STDIO_UART_TX, PinMap_UART_TX)) {
error("Error: new serial object is using same UART as STDIO");
}
@ -206,8 +205,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */
}
else {
} else {
#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE
obj_s->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */

9
targets/TARGET_STM/stm_spi_api.c
View File

@ -318,9 +318,11 @@ static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
SPI_BAUDRATEPRESCALER_32,
SPI_BAUDRATEPRESCALER_64,
SPI_BAUDRATEPRESCALER_128,
SPI_BAUDRATEPRESCALER_256};
SPI_BAUDRATEPRESCALER_256
};
void spi_frequency(spi_t *obj, int hz) {
void spi_frequency(spi_t *obj, int hz)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
uint8_t prescaler_rank = 0;
@ -578,8 +580,9 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
// don't do anything, if the buffers aren't valid
if (!use_tx && !use_rx)
if (!use_tx && !use_rx) {
return;
}
// copy the buffers to the SPI object
obj->tx_buff.buffer = (void *) tx;