diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1510/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1510/mbedtls_device.h index 7cb737741f..f40028d717 100644 --- a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1510/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1510/mbedtls_device.h @@ -1,5 +1,5 @@ /* - * mbedtls_device.h + * mbedtls_device.h ******************************************************************************* * Copyright (c) 2017, STMicroelectronics * SPDX-License-Identifier: Apache-2.0 diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1570/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1570/mbedtls_device.h index 7cb737741f..f40028d717 100644 --- a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1570/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1570/mbedtls_device.h @@ -1,5 +1,5 @@ /* - * mbedtls_device.h + * mbedtls_device.h ******************************************************************************* * Copyright (c) 2017, STMicroelectronics * SPDX-License-Identifier: Apache-2.0 diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L486RG/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L486RG/mbedtls_device.h index 7cb737741f..f40028d717 100644 --- a/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L486RG/mbedtls_device.h +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L486RG/mbedtls_device.h @@ -1,5 +1,5 @@ /* - * mbedtls_device.h + * mbedtls_device.h ******************************************************************************* * Copyright (c) 2017, STMicroelectronics * SPDX-License-Identifier: Apache-2.0 diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.c b/features/mbedtls/targets/TARGET_STM/aes_alt.c index bb11ee2451..414fb2efee 100644 --- a/features/mbedtls/targets/TARGET_STM/aes_alt.c +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.c @@ -31,16 +31,16 @@ #define CRYP AES #endif -static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) +static int aes_set_key(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits) { - switch( keybits ) { + switch (keybits) { case 128: ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_128B; memcpy(ctx->aes_key, key, 16); break; case 192: #if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC) - return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); + return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); #else ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_192B; memcpy(ctx->aes_key, key, 24); @@ -51,12 +51,14 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B; memcpy(ctx->aes_key, key, 32); break; - default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + default : + return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); } /* Deinitializes the CRYP peripheral */ - if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) + if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) { return (HAL_ERROR); + } ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B; ctx->hcryp_aes.Instance = CRYP; @@ -67,64 +69,69 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi #if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC) ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; #endif - if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR) + if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR) { return (HAL_ERROR); + } /* allow multi-instance of CRYP use: save context for CRYP HW module CR */ ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; - return(0); + return (0); } /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) +static void mbedtls_zeroize(void *v, size_t n) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; + volatile unsigned char *p = (unsigned char *)v; + while (n--) { + *p++ = 0; + } } -void mbedtls_aes_init( mbedtls_aes_context *ctx ) +void mbedtls_aes_init(mbedtls_aes_context *ctx) { - memset( ctx, 0, sizeof( mbedtls_aes_context ) ); + memset(ctx, 0, sizeof(mbedtls_aes_context)); } -void mbedtls_aes_free( mbedtls_aes_context *ctx ) +void mbedtls_aes_free(mbedtls_aes_context *ctx) { - if( ctx == NULL ) + if (ctx == NULL) { return; + } /* Force the CRYP Periheral Clock Reset */ __HAL_RCC_CRYP_FORCE_RESET(); /* Release the CRYP Periheral Clock Reset */ __HAL_RCC_CRYP_RELEASE_RESET(); - mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); + mbedtls_zeroize(ctx, sizeof(mbedtls_aes_context)); } -int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits) { int ret_val = 0; ret_val = aes_set_key(ctx, key, keybits); - return(ret_val); + return (ret_val); } -int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ) +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits) { int ret_val = 0; ret_val = aes_set_key(ctx, key, keybits); - return( ret_val ); + return (ret_val); } -int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) +int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]) { /* allow multi-instance of CRYP use: restore context for CRYP hw module */ @@ -133,27 +140,28 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B; ctx->hcryp_aes.Init.pKey = ctx->aes_key; - if(mode == MBEDTLS_AES_DECRYPT) { /* AES decryption */ - if (mbedtls_internal_aes_decrypt( ctx, input, output )){ + if (mode == MBEDTLS_AES_DECRYPT) { /* AES decryption */ + if (mbedtls_internal_aes_decrypt(ctx, input, output)) { return ST_ERR_AES_BUSY; } } else { /* AES encryption */ - if (mbedtls_internal_aes_encrypt( ctx, input, output )) { + if (mbedtls_internal_aes_encrypt(ctx, input, output)) { return ST_ERR_AES_BUSY; } } /* allow multi-instance of CRYP use: save context for CRYP HW module CR */ ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; - return( 0 ); + return (0); } #if defined(MBEDTLS_CIPHER_MODE_CBC) #if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC) -static int st_cbc_restore_context(mbedtls_aes_context *ctx){ +static int st_cbc_restore_context(mbedtls_aes_context *ctx) +{ uint32_t tickstart; tickstart = HAL_GetTick(); - while((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0){ + while ((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0) { if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) { return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy } @@ -163,62 +171,71 @@ static int st_cbc_restore_context(mbedtls_aes_context *ctx){ return 0; } -static int st_hal_cryp_cbc( mbedtls_aes_context *ctx, uint32_t opmode, size_t length, - unsigned char iv[16], uint8_t *input, uint8_t *output) +static int st_hal_cryp_cbc(mbedtls_aes_context *ctx, uint32_t opmode, size_t length, + unsigned char iv[16], uint8_t *input, uint8_t *output) { ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init /* At this moment only, we know we have CBC mode: Re-initialize AES IP with proper parameters and apply key and IV for multi context usecase */ - if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) + if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) { return ST_ERR_AES_BUSY; + } ctx->hcryp_aes.Init.OperatingMode = opmode; ctx->hcryp_aes.Init.ChainingMode = CRYP_CHAINMODE_AES_CBC; ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE; - if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) + if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) { return ST_ERR_AES_BUSY; + } - if(HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0) + if (HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0) { return ST_ERR_AES_BUSY; + } return 0; } #else /* STM32F4 and STM32F7 */ -static int st_cbc_restore_context(mbedtls_aes_context *ctx){ +static int st_cbc_restore_context(mbedtls_aes_context *ctx) +{ /* allow multi-instance of CRYP use: restore context for CRYP hw module */ ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr; /* Re-initialize AES processor with proper parameters and (re-)apply key and IV for multi context usecases */ - if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) + if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) { return ST_ERR_AES_BUSY; - if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) + } + if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) { return ST_ERR_AES_BUSY; + } return 0; } #endif /* TARGET_STM32L486xG || TARGET_STM32L443xC */ -int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) +int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) { uint32_t tickstart; uint32_t *iv_ptr = (uint32_t *)&iv[0]; - if( length % 16 ) - return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + if (length % 16) { + return (MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH); + } ctx->hcryp_aes.Init.pInitVect = &iv[0]; - if (st_cbc_restore_context(ctx) != 0) + if (st_cbc_restore_context(ctx) != 0) { return (ST_ERR_AES_BUSY); + } #if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC) - if( mode == MBEDTLS_AES_DECRYPT ) { - if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) + if (mode == MBEDTLS_AES_DECRYPT) { + if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) { return ST_ERR_AES_BUSY; + } /* Save the internal IV vector for multi context purpose */ tickstart = HAL_GetTick(); - while((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0){ + while ((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0) { if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) { return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy } @@ -230,20 +247,22 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, *iv_ptr++ = ctx->hcryp_aes.Instance->IVR1; *iv_ptr++ = ctx->hcryp_aes.Instance->IVR0; } else { - if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) + if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) { return ST_ERR_AES_BUSY; - memcpy( iv, output, 16 ); /* current output is the IV vector for the next call */ + } + memcpy(iv, output, 16); /* current output is the IV vector for the next call */ ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; } #else - if( mode == MBEDTLS_AES_DECRYPT ) { - if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) + if (mode == MBEDTLS_AES_DECRYPT) { + if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) { return ST_ERR_AES_BUSY; + } /* Save the internal IV vector for multi context purpose */ tickstart = HAL_GetTick(); - while((ctx->hcryp_aes.Instance->SR & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM){ + while ((ctx->hcryp_aes.Instance->SR & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM) { if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) { return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy } @@ -255,9 +274,10 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, *iv_ptr++ = ctx->hcryp_aes.Instance->IV1LR; *iv_ptr++ = ctx->hcryp_aes.Instance->IV1RR; } else { - if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) + if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) { return ST_ERR_AES_BUSY; - memcpy( iv, output, 16 ); /* current output is the IV vector for the next call */ + } + memcpy(iv, output, 16); /* current output is the IV vector for the next call */ ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; } @@ -267,115 +287,121 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) -int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) +int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) { int c; size_t n = *iv_off; - if( mode == MBEDTLS_AES_DECRYPT ) { - while( length-- ) { - if( n == 0 ) - if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0) + if (mode == MBEDTLS_AES_DECRYPT) { + while (length--) { + if (n == 0) + if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) { return ST_ERR_AES_BUSY; + } c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); + *output++ = (unsigned char)(c ^ iv[n]); iv[n] = (unsigned char) c; - n = ( n + 1 ) & 0x0F; + n = (n + 1) & 0x0F; } } else { - while( length-- ) { - if( n == 0 ) - if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0) + while (length--) { + if (n == 0) + if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) { return ST_ERR_AES_BUSY; + } - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + iv[n] = *output++ = (unsigned char)(iv[n] ^ *input++); - n = ( n + 1 ) & 0x0F; + n = (n + 1) & 0x0F; } } *iv_off = n; - return( 0 ); + return (0); } -int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) +int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) { unsigned char c; unsigned char ov[17]; - while( length-- ) { - memcpy( ov, iv, 16 ); - if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0) + while (length--) { + memcpy(ov, iv, 16); + if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) { return ST_ERR_AES_BUSY; + } - if( mode == MBEDTLS_AES_DECRYPT ) + if (mode == MBEDTLS_AES_DECRYPT) { ov[16] = *input; + } - c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + c = *output++ = (unsigned char)(iv[0] ^ *input++); - if( mode == MBEDTLS_AES_ENCRYPT ) + if (mode == MBEDTLS_AES_ENCRYPT) { ov[16] = c; + } - memcpy( iv, ov + 1, 16 ); + memcpy(iv, ov + 1, 16); } - return( 0 ); + return (0); } #endif /*MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) -int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ) +int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output) { int c, i; size_t n = *nc_off; - while( length-- ) - { - if( n == 0 ) { - if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ) != 0) + while (length--) { + if (n == 0) { + if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block) != 0) { return ST_ERR_AES_BUSY; + } - for( i = 16; i > 0; i-- ) - if( ++nonce_counter[i - 1] != 0 ) + for (i = 16; i > 0; i--) + if (++nonce_counter[i - 1] != 0) { break; + } } c = *input++; - *output++ = (unsigned char)( c ^ stream_block[n] ); + *output++ = (unsigned char)(c ^ stream_block[n]); - n = ( n + 1 ) & 0x0F; + n = (n + 1) & 0x0F; } *nc_off = n; - return( 0 ); + return (0); } #endif /* MBEDTLS_CIPHER_MODE_CTR */ -int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) +int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]) { if (HAL_CRYP_AESECB_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) { // error found @@ -385,11 +411,11 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, } -int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) +int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]) { - if(HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) { + if (HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) { // error found return ST_ERR_AES_BUSY; } @@ -397,18 +423,18 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, } #if !defined(MBEDTLS_DEPRECATED_REMOVED) -void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) +void mbedtls_aes_encrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]) { - mbedtls_internal_aes_encrypt( ctx, input, output ); + mbedtls_internal_aes_encrypt(ctx, input, output); } -void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) +void mbedtls_aes_decrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]) { - mbedtls_internal_aes_decrypt( ctx, input, output ); + mbedtls_internal_aes_decrypt(ctx, input, output); } #endif /* MBEDTLS_DEPRECATED_REMOVED */ #endif /*MBEDTLS_AES_ALT*/ diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.h b/features/mbedtls/targets/TARGET_STM/aes_alt.h index 120c9af5f1..a134172895 100644 --- a/features/mbedtls/targets/TARGET_STM/aes_alt.h +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.h @@ -41,8 +41,7 @@ extern "C" { * - to simplify key expansion in the 256-bit case by * generating an extra round key */ -typedef struct -{ +typedef struct { unsigned char aes_key[32]; /* Decryption key */ CRYP_HandleTypeDef hcryp_aes; uint32_t ctx_save_cr; /* save context for multi-instance */ @@ -54,14 +53,14 @@ mbedtls_aes_context; * * \param ctx AES context to be initialized */ -void mbedtls_aes_init( mbedtls_aes_context *ctx ); +void mbedtls_aes_init(mbedtls_aes_context *ctx); /** * \brief Clear AES context * * \param ctx AES context to be cleared */ -void mbedtls_aes_free( mbedtls_aes_context *ctx ); +void mbedtls_aes_free(mbedtls_aes_context *ctx); /** * \brief AES key schedule (encryption) @@ -72,8 +71,8 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx ); * * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ -int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits); /** * \brief AES key schedule (decryption) @@ -84,8 +83,8 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, * * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH */ -int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits ); +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits); /** * \brief AES-ECB block encryption/decryption @@ -97,10 +96,10 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, * * \return 0 if successful */ -int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ); +int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]); #if defined(MBEDTLS_CIPHER_MODE_CBC) /** @@ -125,12 +124,12 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, * * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH */ -int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); +int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); #endif /* MBEDTLS_CIPHER_MODE_CBC */ #if defined(MBEDTLS_CIPHER_MODE_CFB) @@ -159,13 +158,13 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, * * \return 0 if successful */ -int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); +int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); /** * \brief AES-CFB8 buffer encryption/decryption. @@ -191,12 +190,12 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, * * \return 0 if successful */ -int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); +int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); #endif /*MBEDTLS_CIPHER_MODE_CFB */ #if defined(MBEDTLS_CIPHER_MODE_CTR) @@ -222,13 +221,13 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, * * \return 0 if successful */ -int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output ); +int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output); #endif /* MBEDTLS_CIPHER_MODE_CTR */ /** @@ -242,9 +241,9 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, * * \return 0 if successful */ -int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ); +int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]); /** * \brief Internal AES block decryption function @@ -257,9 +256,9 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, * * \return 0 if successful */ -int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ); +int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]); #if !defined(MBEDTLS_DEPRECATED_REMOVED) #if defined(MBEDTLS_DEPRECATED_WARNING) @@ -277,9 +276,9 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, * \param input Plaintext block * \param output Output (ciphertext) block */ -MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ); +MBEDTLS_DEPRECATED void mbedtls_aes_encrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]); /** * \brief Deprecated internal AES block decryption function @@ -291,9 +290,9 @@ MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, * \param input Ciphertext block * \param output Output (plaintext) block */ -MBEDTLS_DEPRECATED void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ); +MBEDTLS_DEPRECATED void mbedtls_aes_decrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]); #undef MBEDTLS_DEPRECATED #endif /* !MBEDTLS_DEPRECATED_REMOVED */ diff --git a/features/mbedtls/targets/TARGET_STM/md5_alt.c b/features/mbedtls/targets/TARGET_STM/md5_alt.c index 853d1db24e..1498ce70f6 100644 --- a/features/mbedtls/targets/TARGET_STM/md5_alt.c +++ b/features/mbedtls/targets/TARGET_STM/md5_alt.c @@ -24,8 +24,12 @@ #include "mbedtls/platform.h" /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = v; + while (n--) { + *p++ = 0; + } } static int st_md5_restore_hw_context(mbedtls_md5_context *ctx) @@ -42,7 +46,7 @@ static int st_md5_restore_hw_context(mbedtls_md5_context *ctx) } HASH->STR = ctx->ctx_save_str; HASH->CR = (ctx->ctx_save_cr | HASH_CR_INIT); - for (i=0;i<38;i++) { + for (i = 0; i < 38; i++) { HASH->CSR[i] = ctx->ctx_save_csr[i]; } return 1; @@ -62,35 +66,36 @@ static int st_md5_save_hw_context(mbedtls_md5_context *ctx) /* allow multi-instance of HASH use: restore context for HASH HW module CR */ ctx->ctx_save_cr = HASH->CR; ctx->ctx_save_str = HASH->STR; - for (i=0;i<38;i++) { + for (i = 0; i < 38; i++) { ctx->ctx_save_csr[i] = HASH->CSR[i]; } return 1; } -void mbedtls_md5_init( mbedtls_md5_context *ctx ) +void mbedtls_md5_init(mbedtls_md5_context *ctx) { - mbedtls_zeroize( ctx, sizeof( mbedtls_md5_context ) ); + mbedtls_zeroize(ctx, sizeof(mbedtls_md5_context)); /* Enable HASH clock */ __HAL_RCC_HASH_CLK_ENABLE(); } -void mbedtls_md5_free( mbedtls_md5_context *ctx ) +void mbedtls_md5_free(mbedtls_md5_context *ctx) { - if( ctx == NULL ) + if (ctx == NULL) { return; - mbedtls_zeroize( ctx, sizeof( mbedtls_md5_context ) ); + } + mbedtls_zeroize(ctx, sizeof(mbedtls_md5_context)); } -void mbedtls_md5_clone( mbedtls_md5_context *dst, - const mbedtls_md5_context *src ) +void mbedtls_md5_clone(mbedtls_md5_context *dst, + const mbedtls_md5_context *src) { *dst = *src; } -int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx ) +int mbedtls_md5_starts_ret(mbedtls_md5_context *ctx) { /* HASH IP initialization */ if (HAL_HASH_DeInit(&ctx->hhash_md5) != 0) { @@ -112,7 +117,7 @@ int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx ) return 0; } -int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE] ) +int mbedtls_internal_md5_process(mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE]) { if (st_md5_restore_hw_context(ctx) != 1) { // Return HASH_BUSY timeout error here @@ -128,7 +133,7 @@ int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char return 0; } -int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen ) +int mbedtls_md5_update_ret(mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen) { int err; size_t currentlen = ilen; @@ -142,7 +147,7 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input // store mechanism to accumulate ST_MD5_BLOCK_SIZE bytes (512 bits) in the HW if (currentlen < (ST_MD5_BLOCK_SIZE - ctx->sbuf_len)) { // only buffurize - memcpy(ctx->sbuf+ctx->sbuf_len, input, currentlen); + memcpy(ctx->sbuf + ctx->sbuf_len, input, currentlen); ctx->sbuf_len += currentlen; } else { // fill buffer and process it @@ -154,14 +159,14 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input } // Process every input as long as it is %64 bytes, ie 512 bits size_t iter = currentlen / ST_MD5_BLOCK_SIZE; - if (iter !=0) { + if (iter != 0) { if (HAL_HASH_MD5_Accumulate(&ctx->hhash_md5, (uint8_t *)(input + ST_MD5_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_MD5_BLOCK_SIZE)) != 0) { return MBEDTLS_ERR_MD5_HW_ACCEL_FAILED; } } // sbuf is completely accumulated, now copy up to 63 remaining bytes ctx->sbuf_len = currentlen % ST_MD5_BLOCK_SIZE; - if (ctx->sbuf_len !=0) { + if (ctx->sbuf_len != 0) { memcpy(ctx->sbuf, input + ilen - ctx->sbuf_len, ctx->sbuf_len); } } @@ -174,7 +179,7 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input return 0; } -int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] ) +int mbedtls_md5_finish_ret(mbedtls_md5_context *ctx, unsigned char output[16]) { if (st_md5_restore_hw_context(ctx) != 1) { // Return HASH_BUSY timeout error here @@ -186,7 +191,7 @@ int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] ) return MBEDTLS_ERR_MD5_HW_ACCEL_FAILED; } - mbedtls_zeroize( ctx->sbuf, ST_MD5_BLOCK_SIZE); + mbedtls_zeroize(ctx->sbuf, ST_MD5_BLOCK_SIZE); ctx->sbuf_len = 0; __HAL_HASH_START_DIGEST(); diff --git a/features/mbedtls/targets/TARGET_STM/md5_alt.h b/features/mbedtls/targets/TARGET_STM/md5_alt.h index 605fee5410..43a549d357 100644 --- a/features/mbedtls/targets/TARGET_STM/md5_alt.h +++ b/features/mbedtls/targets/TARGET_STM/md5_alt.h @@ -41,8 +41,7 @@ extern "C" { * ST_MD5_BLOCK_SIZE bytes per ST_MD5_BLOCK_SIZE bytes * If MD5_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_MD5_Finish */ -typedef struct -{ +typedef struct { HASH_HandleTypeDef hhash_md5;/*!< ST HAL HASH struct */ unsigned char sbuf[ST_MD5_BLOCK_SIZE]; /*!< MBEDTLS_MD5_BLOCK_SIZE buffer to store values so that algorithm is caled once the buffer is filled */ unsigned char sbuf_len; /*!< number of bytes to be processed in sbuf */ @@ -57,14 +56,14 @@ mbedtls_md5_context; * * \param ctx MD5 context to be initialized */ -void mbedtls_md5_init( mbedtls_md5_context *ctx ); +void mbedtls_md5_init(mbedtls_md5_context *ctx); /** * \brief Clear MD5 context * * \param ctx MD5 context to be cleared */ -void mbedtls_md5_free( mbedtls_md5_context *ctx ); +void mbedtls_md5_free(mbedtls_md5_context *ctx); /** * \brief Clone (the state of) an MD5 context @@ -72,8 +71,8 @@ void mbedtls_md5_free( mbedtls_md5_context *ctx ); * \param dst The destination context * \param src The context to be cloned */ -void mbedtls_md5_clone( mbedtls_md5_context *dst, - const mbedtls_md5_context *src ); +void mbedtls_md5_clone(mbedtls_md5_context *dst, + const mbedtls_md5_context *src); /** * \brief MD5 context setup @@ -82,7 +81,7 @@ void mbedtls_md5_clone( mbedtls_md5_context *dst, * * \returns error code */ -int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx ); +int mbedtls_md5_starts_ret(mbedtls_md5_context *ctx); /** * \brief MD5 process buffer @@ -93,7 +92,7 @@ int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx ); * * \returns error code */ -int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen ); +int mbedtls_md5_update_ret(mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen); /** * \brief MD5 final digest @@ -103,10 +102,10 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input * * \returns error code */ -int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] ); +int mbedtls_md5_finish_ret(mbedtls_md5_context *ctx, unsigned char output[16]); /* Internal use */ -int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE] ); +int mbedtls_internal_md5_process(mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE]); #if !defined(MBEDTLS_DEPRECATED_REMOVED) #if defined(MBEDTLS_DEPRECATED_WARNING) @@ -126,7 +125,7 @@ int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_md5_starts( mbedtls_md5_context *ctx ); +MBEDTLS_DEPRECATED void mbedtls_md5_starts(mbedtls_md5_context *ctx); /** * \brief MD5 process buffer @@ -142,9 +141,9 @@ MBEDTLS_DEPRECATED void mbedtls_md5_starts( mbedtls_md5_context *ctx ); * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_md5_update( mbedtls_md5_context *ctx, - const unsigned char *input, - size_t ilen ); +MBEDTLS_DEPRECATED void mbedtls_md5_update(mbedtls_md5_context *ctx, + const unsigned char *input, + size_t ilen); /** * \brief MD5 final digest @@ -159,8 +158,8 @@ MBEDTLS_DEPRECATED void mbedtls_md5_update( mbedtls_md5_context *ctx, * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_md5_finish( mbedtls_md5_context *ctx, - unsigned char output[16] ); +MBEDTLS_DEPRECATED void mbedtls_md5_finish(mbedtls_md5_context *ctx, + unsigned char output[16]); /** * \brief MD5 process data block (internal use only) @@ -175,8 +174,8 @@ MBEDTLS_DEPRECATED void mbedtls_md5_finish( mbedtls_md5_context *ctx, * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_md5_process( mbedtls_md5_context *ctx, - const unsigned char data[64] ); +MBEDTLS_DEPRECATED void mbedtls_md5_process(mbedtls_md5_context *ctx, + const unsigned char data[64]); #undef MBEDTLS_DEPRECATED #endif /* !MBEDTLS_DEPRECATED_REMOVED */ diff --git a/features/mbedtls/targets/TARGET_STM/sha1_alt.c b/features/mbedtls/targets/TARGET_STM/sha1_alt.c index e4a9e5ac51..00fd001c35 100644 --- a/features/mbedtls/targets/TARGET_STM/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_STM/sha1_alt.c @@ -22,8 +22,12 @@ #include "mbedtls/platform.h" /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = (unsigned char *)v; + while (n--) { + *p++ = 0; + } } static int st_sha1_restore_hw_context(mbedtls_sha1_context *ctx) @@ -40,7 +44,7 @@ static int st_sha1_restore_hw_context(mbedtls_sha1_context *ctx) } HASH->STR = ctx->ctx_save_str; HASH->CR = (ctx->ctx_save_cr | HASH_CR_INIT); - for (i=0;i<38;i++) { + for (i = 0; i < 38; i++) { HASH->CSR[i] = ctx->ctx_save_csr[i]; } return 1; @@ -60,35 +64,36 @@ static int st_sha1_save_hw_context(mbedtls_sha1_context *ctx) /* allow multi-instance of HASH use: restore context for HASH HW module CR */ ctx->ctx_save_cr = HASH->CR; ctx->ctx_save_str = HASH->STR; - for (i=0;i<38;i++) { + for (i = 0; i < 38; i++) { ctx->ctx_save_csr[i] = HASH->CSR[i]; } return 1; } -void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) { - mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_context ) ); + mbedtls_zeroize(ctx, sizeof(mbedtls_sha1_context)); /* Enable HASH clock */ __HAL_RCC_HASH_CLK_ENABLE(); } -void mbedtls_sha1_free( mbedtls_sha1_context *ctx ) +void mbedtls_sha1_free(mbedtls_sha1_context *ctx) { - if( ctx == NULL ) + if (ctx == NULL) { return; - mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_context ) ); + } + mbedtls_zeroize(ctx, sizeof(mbedtls_sha1_context)); } -void mbedtls_sha1_clone( mbedtls_sha1_context *dst, - const mbedtls_sha1_context *src ) +void mbedtls_sha1_clone(mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src) { *dst = *src; } -int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ) +int mbedtls_sha1_starts_ret(mbedtls_sha1_context *ctx) { /* Deinitializes the HASH peripheral */ if (HAL_HASH_DeInit(&ctx->hhash_sha1) == HAL_ERROR) { @@ -109,7 +114,7 @@ int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ) return 0; } -int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE] ) +int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE]) { if (st_sha1_restore_hw_context(ctx) != 1) { // return HASH_BUSY timeout Error here @@ -126,7 +131,7 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned cha return 0; } -int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen ) +int mbedtls_sha1_update_ret(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) { int err; size_t currentlen = ilen; @@ -136,11 +141,11 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp } // store mechanism to accumulate ST_SHA1_BLOCK_SIZE bytes (512 bits) in the HW - if (currentlen == 0){ // only change HW status is size if 0 - if(ctx->hhash_sha1.Phase == HAL_HASH_PHASE_READY) { - /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT; + if (currentlen == 0) { // only change HW status is size if 0 + if (ctx->hhash_sha1.Phase == HAL_HASH_PHASE_READY) { + /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute + the message digest of a new message */ + HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT; } ctx->hhash_sha1.Phase = HAL_HASH_PHASE_PROCESS; } else if (currentlen < (ST_SHA1_BLOCK_SIZE - ctx->sbuf_len)) { @@ -162,7 +167,7 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp } // sbuf is completely accumulated, now copy up to 63 remaining bytes ctx->sbuf_len = currentlen % ST_SHA1_BLOCK_SIZE; - if (ctx->sbuf_len !=0) { + if (ctx->sbuf_len != 0) { memcpy(ctx->sbuf, input + ilen - ctx->sbuf_len, ctx->sbuf_len); } } @@ -173,7 +178,7 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp return 0; } -int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ) +int mbedtls_sha1_finish_ret(mbedtls_sha1_context *ctx, unsigned char output[20]) { if (st_sha1_restore_hw_context(ctx) != 1) { // return HASH_BUSY timeout Error here @@ -189,7 +194,7 @@ int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ctx->sbuf_len = 0; __HAL_HASH_START_DIGEST(); - if (HAL_HASH_SHA1_Finish(&ctx->hhash_sha1, output, 10) != 0){ + if (HAL_HASH_SHA1_Finish(&ctx->hhash_sha1, output, 10) != 0) { return MBEDTLS_ERR_SHA1_HW_ACCEL_FAILED; } if (st_sha1_save_hw_context(ctx) != 1) { diff --git a/features/mbedtls/targets/TARGET_STM/sha1_alt.h b/features/mbedtls/targets/TARGET_STM/sha1_alt.h index e35007e5da..bb4991d580 100644 --- a/features/mbedtls/targets/TARGET_STM/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_STM/sha1_alt.h @@ -41,8 +41,7 @@ extern "C" { * multiples of ST_SHA1_BLOCK_SIZE bytes * If SHA1_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_SHA1_Finish */ -typedef struct -{ +typedef struct { unsigned char sbuf[ST_SHA1_BLOCK_SIZE]; /*!< MBEDTLS_SHA1_BLOCK_SIZE buffer to store values so that algorithm is caled once the buffer is filled */ unsigned char sbuf_len; /*!< number of bytes remaining in sbuf to be processed */ HASH_HandleTypeDef hhash_sha1; /*!< ST HAL HASH struct */ @@ -57,14 +56,14 @@ mbedtls_sha1_context; * * \param ctx SHA-1 context to be initialized */ -void mbedtls_sha1_init( mbedtls_sha1_context *ctx ); +void mbedtls_sha1_init(mbedtls_sha1_context *ctx); /** * \brief Clear SHA-1 context * * \param ctx SHA-1 context to be cleared */ -void mbedtls_sha1_free( mbedtls_sha1_context *ctx ); +void mbedtls_sha1_free(mbedtls_sha1_context *ctx); /** * \brief Clone (the state of) a SHA-1 context @@ -72,8 +71,8 @@ void mbedtls_sha1_free( mbedtls_sha1_context *ctx ); * \param dst The destination context * \param src The context to be cloned */ -void mbedtls_sha1_clone( mbedtls_sha1_context *dst, - const mbedtls_sha1_context *src ); +void mbedtls_sha1_clone(mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src); /** * \brief SHA-1 context setup @@ -82,7 +81,7 @@ void mbedtls_sha1_clone( mbedtls_sha1_context *dst, * * \returns error code */ -int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ); +int mbedtls_sha1_starts_ret(mbedtls_sha1_context *ctx); /** * \brief SHA-1 process buffer @@ -93,7 +92,7 @@ int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ); * * \returns error code */ -int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen ); +int mbedtls_sha1_update_ret(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen); /** * \brief SHA-1 final digest @@ -103,10 +102,10 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp * * \returns error code */ -int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ); +int mbedtls_sha1_finish_ret(mbedtls_sha1_context *ctx, unsigned char output[20]); /* Internal use */ -int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE] ); +int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE]); #if !defined(MBEDTLS_DEPRECATED_REMOVED) #if defined(MBEDTLS_DEPRECATED_WARNING) @@ -126,7 +125,7 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned cha * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ); +MBEDTLS_DEPRECATED void mbedtls_sha1_starts(mbedtls_sha1_context *ctx); /** * \brief SHA-1 process buffer @@ -142,9 +141,9 @@ MBEDTLS_DEPRECATED void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ); * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_sha1_update( mbedtls_sha1_context *ctx, - const unsigned char *input, - size_t ilen ); +MBEDTLS_DEPRECATED void mbedtls_sha1_update(mbedtls_sha1_context *ctx, + const unsigned char *input, + size_t ilen); /** * \brief SHA-1 final digest @@ -159,8 +158,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha1_update( mbedtls_sha1_context *ctx, * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, - unsigned char output[20] ); +MBEDTLS_DEPRECATED void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, + unsigned char output[20]); /** * \brief SHA-1 process data block (internal use only) @@ -175,8 +174,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, * stronger message digests instead. * */ -MBEDTLS_DEPRECATED void mbedtls_sha1_process( mbedtls_sha1_context *ctx, - const unsigned char data[64] ); +MBEDTLS_DEPRECATED void mbedtls_sha1_process(mbedtls_sha1_context *ctx, + const unsigned char data[64]); #undef MBEDTLS_DEPRECATED #endif /* !MBEDTLS_DEPRECATED_REMOVED */ diff --git a/features/mbedtls/targets/TARGET_STM/sha256_alt.c b/features/mbedtls/targets/TARGET_STM/sha256_alt.c index 620de52e29..7f37aa7a94 100644 --- a/features/mbedtls/targets/TARGET_STM/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_STM/sha256_alt.c @@ -23,8 +23,12 @@ #include "mbedtls/platform.h" /* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; +static void mbedtls_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = v; + while (n--) { + *p++ = 0; + } } static int st_sha256_restore_hw_context(mbedtls_sha256_context *ctx) @@ -41,7 +45,7 @@ static int st_sha256_restore_hw_context(mbedtls_sha256_context *ctx) } HASH->STR = ctx->ctx_save_str; HASH->CR = (ctx->ctx_save_cr | HASH_CR_INIT); - for (i=0;i<38;i++) { + for (i = 0; i < 38; i++) { HASH->CSR[i] = ctx->ctx_save_csr[i]; } return 1; @@ -61,34 +65,35 @@ static int st_sha256_save_hw_context(mbedtls_sha256_context *ctx) /* allow multi-instance of HASH use: restore context for HASH HW module CR */ ctx->ctx_save_cr = HASH->CR; ctx->ctx_save_str = HASH->STR; - for (i=0;i<38;i++) { + for (i = 0; i < 38; i++) { ctx->ctx_save_csr[i] = HASH->CSR[i]; } return 1; } -void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) { - mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_context ) ); + mbedtls_zeroize(ctx, sizeof(mbedtls_sha256_context)); /* Enable HASH clock */ __HAL_RCC_HASH_CLK_ENABLE(); } -void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) +void mbedtls_sha256_free(mbedtls_sha256_context *ctx) { - if( ctx == NULL ) + if (ctx == NULL) { return; - mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_context ) ); + } + mbedtls_zeroize(ctx, sizeof(mbedtls_sha256_context)); } -void mbedtls_sha256_clone( mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src ) +void mbedtls_sha256_clone(mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src) { *dst = *src; } -int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ) +int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224) { /* HASH IP initialization */ if (HAL_HASH_DeInit(&ctx->hhash_sha256) == HAL_ERROR) { @@ -111,7 +116,7 @@ int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ) return 0; } -int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE] ) +int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE]) { if (st_sha256_restore_hw_context(ctx) != 1) { // Return HASH_BUSY timeout error here @@ -134,7 +139,7 @@ int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned return 0; } -int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen ) +int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) { int err; size_t currentlen = ilen; @@ -145,7 +150,7 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char // store mechanism to accumulate ST_SHA256_BLOCK_SIZE bytes (512 bits) in the HW if (currentlen == 0) { // only change HW status is size if 0 - if(ctx->hhash_sha256.Phase == HAL_HASH_PHASE_READY) { + if (ctx->hhash_sha256.Phase == HAL_HASH_PHASE_READY) { /* Select the SHA256 or SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute the message digest of a new message */ if (ctx->is224 == 0) { @@ -169,20 +174,20 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char } // Process every input as long as it is %64 bytes, ie 512 bits size_t iter = currentlen / ST_SHA256_BLOCK_SIZE; - if (iter !=0) { + if (iter != 0) { if (ctx->is224 == 0) { - if (HAL_HASHEx_SHA256_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) { + if (HAL_HASHEx_SHA256_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) { return MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED; } } else { - if (HAL_HASHEx_SHA224_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) { + if (HAL_HASHEx_SHA224_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) { return MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED; } } } // sbuf is completely accumulated, now copy up to 63 remaining bytes ctx->sbuf_len = currentlen % ST_SHA256_BLOCK_SIZE; - if (ctx->sbuf_len !=0) { + if (ctx->sbuf_len != 0) { memcpy(ctx->sbuf, input + ilen - ctx->sbuf_len, ctx->sbuf_len); } } @@ -193,7 +198,7 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char return 0; } -int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ) +int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx, unsigned char output[32]) { if (st_sha256_restore_hw_context(ctx) != 1) { // Return HASH_BUSY timeout error here diff --git a/features/mbedtls/targets/TARGET_STM/sha256_alt.h b/features/mbedtls/targets/TARGET_STM/sha256_alt.h index 14462471a8..522319cc8c 100644 --- a/features/mbedtls/targets/TARGET_STM/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_STM/sha256_alt.h @@ -40,10 +40,9 @@ extern "C" { * ST_SHA256_BLOCK_SIZE bytes per ST_SHA256_BLOCK_SIZE bytes * If sha256_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_SHA256_Finish */ -typedef struct -{ - int is224; /*!< 0 => SHA-256, else SHA-224 */ - HASH_HandleTypeDef hhash_sha256; +typedef struct { + int is224; /*!< 0 => SHA-256, else SHA-224 */ + HASH_HandleTypeDef hhash_sha256; unsigned char sbuf[ST_SHA256_BLOCK_SIZE]; /*!< ST_SHA256_BLOCK_SIZE buffer to store values so that algorithm is called once the buffer is filled */ unsigned char sbuf_len; /*!< number of bytes to be processed in sbuf */ uint32_t ctx_save_cr; @@ -57,14 +56,14 @@ mbedtls_sha256_context; * * \param ctx SHA-256 context to be initialized */ -void mbedtls_sha256_init( mbedtls_sha256_context *ctx ); +void mbedtls_sha256_init(mbedtls_sha256_context *ctx); /** * \brief Clear SHA-256 context * * \param ctx SHA-256 context to be cleared */ -void mbedtls_sha256_free( mbedtls_sha256_context *ctx ); +void mbedtls_sha256_free(mbedtls_sha256_context *ctx); /** * \brief Clone (the state of) a SHA-256 context @@ -72,8 +71,8 @@ void mbedtls_sha256_free( mbedtls_sha256_context *ctx ); * \param dst The destination context * \param src The context to be cloned */ -void mbedtls_sha256_clone( mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src ); +void mbedtls_sha256_clone(mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src); /** * \brief SHA-256 context setup @@ -83,7 +82,7 @@ void mbedtls_sha256_clone( mbedtls_sha256_context *dst, * * \returns error code */ -int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ); +int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224); /** * \brief SHA-256 process buffer @@ -94,9 +93,9 @@ int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ); * * \returns error code */ -int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, - const unsigned char *input, - size_t ilen ); +int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen); /** * \brief SHA-256 final digest @@ -106,10 +105,10 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, * * \returns error code */ -int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ); +int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx, unsigned char output[32]); /* Internal use */ -int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE] ); +int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE]); #if !defined(MBEDTLS_DEPRECATED_REMOVED) #if defined(MBEDTLS_DEPRECATED_WARNING) @@ -127,8 +126,8 @@ int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned * */ -MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, - int is224 ); +MBEDTLS_DEPRECATED void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, + int is224); /** * \brief This function feeds an input buffer into an ongoing @@ -140,9 +139,9 @@ MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, * \param input The buffer holding the data. * \param ilen The length of the input data. */ -MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx, - const unsigned char *input, - size_t ilen ); +MBEDTLS_DEPRECATED void mbedtls_sha256_update(mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen); /** * \brief This function finishes the SHA-256 operation, and writes @@ -153,8 +152,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx, * \param ctx The SHA-256 context. * \param output The SHA-224or SHA-256 checksum result. */ -MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, - unsigned char output[32] ); +MBEDTLS_DEPRECATED void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, + unsigned char output[32]); /** * \brief This function processes a single data block within @@ -166,8 +165,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, * \param ctx The SHA-256 context. * \param data The buffer holding one block of data. */ -MBEDTLS_DEPRECATED void mbedtls_sha256_process( mbedtls_sha256_context *ctx, - const unsigned char data[64] ); +MBEDTLS_DEPRECATED void mbedtls_sha256_process(mbedtls_sha256_context *ctx, + const unsigned char data[64]); #undef MBEDTLS_DEPRECATED #endif /* !MBEDTLS_DEPRECATED_REMOVED */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c index 1564ff264f..7b054c7eed 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -59,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -79,7 +79,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -88,7 +88,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/stm32f2_eth_conf.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/stm32f2_eth_conf.c index edf37ee5f9..dd004db579 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/stm32f2_eth_conf.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/stm32f2_eth_conf.c @@ -18,8 +18,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macconf = - { + ETH_MACInitTypeDef macconf = { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, .VLANTagIdentifier = 0x0U - }; + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_conf.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_conf.c index 7325f42caf..a11be4a4f7 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_conf.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_conf.c @@ -18,8 +18,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macconf = - { + ETH_MACInitTypeDef macconf = { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, .VLANTagIdentifier = 0x0U, - }; + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c index 172ae42d70..a95ea0f8ea 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c @@ -3,7 +3,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -20,7 +20,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> + RMII_MII_RXER ---------------------> RMII_MII_TX_EN --------------------> PB11 RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD1 ---------------------> PB13 @@ -28,7 +28,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -44,7 +44,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -53,7 +53,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ @@ -66,7 +66,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) RMII_MII_CRS_DV -------------------> PA7 RMII_MII_RXD0 ---------------------> PC4 RMII_MII_RXD1 ---------------------> PC5 - RMII_MII_RXER ---------------------> + RMII_MII_RXER ---------------------> RMII_MII_TX_EN --------------------> PB11 RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD1 ---------------------> PB13 diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_conf.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_conf.c index 7325f42caf..a11be4a4f7 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_conf.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_conf.c @@ -18,8 +18,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macconf = - { + ETH_MACInitTypeDef macconf = { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, .VLANTagIdentifier = 0x0U, - }; + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c index bcf70210a0..09dfb94000 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -59,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -79,7 +79,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -88,7 +88,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_conf.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_conf.c index 7325f42caf..a11be4a4f7 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_conf.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_conf.c @@ -18,8 +18,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macconf = - { + ETH_MACInitTypeDef macconf = { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, .VLANTagIdentifier = 0x0U, - }; + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c index bcf70210a0..09dfb94000 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -59,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -79,7 +79,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -88,7 +88,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c index d702d4902c..b0a2aec66e 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -60,7 +60,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -76,7 +76,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -85,7 +85,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c index c2a90fc33c..de6494121f 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c index 3d16e9f730..019898b9f7 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c index 3d16e9f730..019898b9f7 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c index 3d16e9f730..019898b9f7 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c @@ -33,7 +33,7 @@ /** * Override HAL Eth Init function */ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStructure; if (heth->Instance == ETH) { @@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); @@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } @@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) /** * Override HAL Eth DeInit function */ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { if (heth->Instance == ETH) { /* Peripheral clock disable */ diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/stm32f7_eth_conf.c b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/stm32f7_eth_conf.c index 6937e99b8a..76dbeb4fbd 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/stm32f7_eth_conf.c +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/stm32f7_eth_conf.c @@ -18,8 +18,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macconf = - { + ETH_MACInitTypeDef macconf = { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, .VLANTagIdentifier = 0x0 - }; + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.cpp b/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.cpp index 2d12be0de3..0950b5cdcc 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.cpp +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.cpp @@ -24,22 +24,22 @@ #define STM_ETH_IF_NAME "st" #if defined (__ICCARM__) /*!< IAR Compiler */ - #pragma data_alignment=4 +#pragma data_alignment=4 #endif __ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx DMA Descriptor */ #if defined (__ICCARM__) /*!< IAR Compiler */ - #pragma data_alignment=4 +#pragma data_alignment=4 #endif __ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */ #if defined (__ICCARM__) /*!< IAR Compiler */ - #pragma data_alignment=4 +#pragma data_alignment=4 #endif __ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */ #if defined (__ICCARM__) /*!< IAR Compiler */ - #pragma data_alignment=4 +#pragma data_alignment=4 #endif __ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */ @@ -326,16 +326,16 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf) */ void STM32_EMAC::packet_rx() { - /* move received packet into a new buf */ - while (1) { - emac_mem_buf_t *p = NULL; - if (low_level_input(&p) < 0) { - break; - } - if (p) { - emac_link_input_cb(p); - } - } + /* move received packet into a new buf */ + while (1) { + emac_mem_buf_t *p = NULL; + if (low_level_input(&p) < 0) { + break; + } + if (p) { + emac_link_input_cb(p); + } + } } /** \brief Worker thread. @@ -344,7 +344,7 @@ void STM32_EMAC::packet_rx() * * \param[in] pvParameters pointer to the interface data */ -void STM32_EMAC::thread_function(void* pvParameters) +void STM32_EMAC::thread_function(void *pvParameters) { static struct STM32_EMAC *stm32_enet = static_cast(pvParameters); @@ -391,16 +391,16 @@ void STM32_EMAC::phy_task() * * \param[in] pvParameters pointer to the interface data */ -void STM32_EMAC::rmii_watchdog_thread_function(void* pvParameters) +void STM32_EMAC::rmii_watchdog_thread_function(void *pvParameters) { struct STM32_EMAC *stm32_enet = static_cast(pvParameters); - while(1) { + while (1) { /* some good packets are received */ if (stm32_enet->EthHandle.Instance->MMCRGUFCR > 0) { /* RMII Init is OK - would need service to terminate or suspend * the thread */ - while(1) { + while (1) { /* don't do anything anymore */ osDelay(0xFFFFFFFF); } @@ -432,7 +432,8 @@ void STM32_EMAC::disable_interrupts(void) * @param mac A 6-byte array to write the MAC address */ -void mbed_mac_address(char *mac) { +void mbed_mac_address(char *mac) +{ if (mbed_otp_mac_address(mac)) { return; } else { @@ -441,11 +442,13 @@ void mbed_mac_address(char *mac) { return; } -__weak uint8_t mbed_otp_mac_address(char *mac) { +__weak uint8_t mbed_otp_mac_address(char *mac) +{ return 0; } -void mbed_default_mac_address(char *mac) { +void mbed_default_mac_address(char *mac) +{ unsigned char ST_mac_addr[3] = {0x00, 0x80, 0xe1}; // default STMicro mac address // Read unic id @@ -456,7 +459,7 @@ void mbed_default_mac_address(char *mac) { #elif defined (TARGET_STM32F7) uint32_t word0 = *(uint32_t *)0x1FF0F420; #else - #error MAC address can not be derived from target unique Id +#error MAC address can not be derived from target unique Id #endif mac[0] = ST_mac_addr[0]; @@ -522,37 +525,37 @@ bool STM32_EMAC::get_hwaddr(uint8_t *addr) const void STM32_EMAC::set_hwaddr(const uint8_t *addr) { - /* No-op at this stage */ + /* No-op at this stage */ } void STM32_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) { - emac_link_input_cb = input_cb; + emac_link_input_cb = input_cb; } void STM32_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) { - emac_link_state_cb = state_cb; + emac_link_state_cb = state_cb; } void STM32_EMAC::add_multicast_group(const uint8_t *addr) { - /* No-op at this stage */ + /* No-op at this stage */ } void STM32_EMAC::remove_multicast_group(const uint8_t *addr) { - /* No-op at this stage */ + /* No-op at this stage */ } void STM32_EMAC::set_all_multicast(bool all) { - /* No-op at this stage */ + /* No-op at this stage */ } void STM32_EMAC::power_down() { - /* No-op at this stage */ + /* No-op at this stage */ } void STM32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) @@ -560,12 +563,14 @@ void STM32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) memory_manager = &mem_mngr; } -STM32_EMAC &STM32_EMAC::get_instance() { +STM32_EMAC &STM32_EMAC::get_instance() +{ static STM32_EMAC emac; return emac; } // Weak so a module can override -MBED_WEAK EMAC &EMAC::get_default_instance() { +MBED_WEAK EMAC &EMAC::get_default_instance() +{ return STM32_EMAC::get_instance(); } diff --git a/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.h b/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.h index 08125e67cb..06077b4704 100644 --- a/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.h +++ b/features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.h @@ -155,8 +155,8 @@ private: bool low_level_init_successful(); void packet_rx(); int low_level_input(emac_mem_buf_t **buf); - static void thread_function(void* pvParameters); - static void rmii_watchdog_thread_function(void* pvParameters); + static void thread_function(void *pvParameters); + static void rmii_watchdog_thread_function(void *pvParameters); void phy_task(); void enable_interrupts(); void disable_interrupts(); diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h index d7cfc5b35c..18ef1ce0ef 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h @@ -42,8 +42,7 @@ #error "FIFO dimensioning incorrect" #endif -typedef struct -{ +typedef struct { USBHAL *inst; void (USBHAL::*bus_reset)(void); @@ -71,10 +70,10 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo) return 1024; } -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN; void (USBHAL::*func)(int frame) = priv->sof; (obj->*func)(sofnum); @@ -92,8 +91,9 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) USBHAL *USBHAL::instance; -USBHAL::USBHAL(void) { - USBHAL_Private_t *HALPriv = new(USBHAL_Private_t); +USBHAL::USBHAL(void) +{ + USBHAL_Private_t *HALPriv = new (USBHAL_Private_t); hpcd.Instance = USB; @@ -151,7 +151,7 @@ USBHAL::USBHAL(void) { __HAL_RCC_SYSCFG_CLK_ENABLE(); // Configure PCD and FIFOs - hpcd.pData = (void*)HALPriv; + hpcd.pData = (void *)HALPriv; hpcd.State = HAL_PCD_STATE_RESET; HAL_PCD_Init(&hpcd); diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h index 73f3b8db15..605365e44c 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h @@ -44,8 +44,7 @@ #error "FIFO dimensioning incorrect" #endif -typedef struct -{ +typedef struct { USBHAL *inst; void (USBHAL::*bus_reset)(void); @@ -71,17 +70,16 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo) uint32_t len; if (fifo == 0) { len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ >> 16; - } - else { + } else { len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16; } return len * 4; } -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8; void (USBHAL::*func)(int frame) = priv->sof; @@ -90,8 +88,9 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) USBHAL *USBHAL::instance; -USBHAL::USBHAL(void) { - USBHAL_Private_t *HALPriv = new(USBHAL_Private_t); +USBHAL::USBHAL(void) +{ + USBHAL_Private_t *HALPriv = new (USBHAL_Private_t); memset(&hpcd.Init, 0, sizeof(hpcd.Init)); @@ -215,7 +214,7 @@ USBHAL::USBHAL(void) { __HAL_RCC_SYSCFG_CLK_ENABLE(); // Configure PCD and FIFOs - hpcd.pData = (void*)HALPriv; + hpcd.pData = (void *)HALPriv; hpcd.State = HAL_PCD_STATE_RESET; HAL_PCD_Init(&hpcd); diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp index 6953f4a078..fa529d77ee 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp @@ -42,13 +42,13 @@ /* this call at device reception completion on a Out Enpoint */ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; uint8_t endpoint = ADDR_EPOUT(epnum); priv->epComplete[endpoint] = 1; /* -2 endpoint 0 In out are not in call back list */ if (epnum) { - bool (USBHAL::*func)(void) = priv->epCallback[endpoint-2]; + bool (USBHAL::*func)(void) = priv->epCallback[endpoint - 2]; (obj->*func)(); } else { void (USBHAL::*func)(void) = priv->ep0_out; @@ -59,13 +59,13 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) /* this is call at device transmission completion on In endpoint */ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; uint8_t endpoint = ADDR_EPIN(epnum); priv->epComplete[endpoint] = 1; /* -2 endpoint 0 In out are not in call back list */ if (epnum) { - bool (USBHAL::*func)(void) = priv->epCallback[endpoint-2]; + bool (USBHAL::*func)(void) = priv->epCallback[endpoint - 2]; (obj->*func)(); } else { void (USBHAL::*func)(void) = priv->ep0_in; @@ -75,158 +75,172 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) /* This is call at device set up reception */ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; - void (USBHAL::*func)(void)=priv->ep0_setup; - void (USBHAL::*func1)(void)=priv->ep0_read; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; + void (USBHAL::*func)(void) = priv->ep0_setup; + void (USBHAL::*func1)(void) = priv->ep0_read; (obj->*func)(); (obj->*func1)(); } void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; void (USBHAL::*func)(unsigned int suspended) = priv->suspend_change; (obj->*func)(1); } void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; void (USBHAL::*func)(unsigned int suspended) = priv->suspend_change; (obj->*func)(0); } void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; void (USBHAL::*func)(unsigned int suspended) = priv->connect_change; (obj->*func)(1); } void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; void (USBHAL::*func)(unsigned int suspended) = priv->connect_change; (obj->*func)(0); } void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) { - USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData)); - USBHAL *obj= priv->inst; + USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData)); + USBHAL *obj = priv->inst; unsigned int i; - for(i=0;iInit.dev_endpoints;i++) { - priv->epComplete[2*i]=0; - HAL_PCD_EP_Close(hpcd,EP_ADDR(2*i)); - HAL_PCD_EP_Flush(hpcd,EP_ADDR(2*i)); - priv->epComplete[2*i+1]=0; - HAL_PCD_EP_Close(hpcd,EP_ADDR(2*i+1)); - HAL_PCD_EP_Flush(hpcd,EP_ADDR(2*i+1)); + for (i = 0; i < hpcd->Init.dev_endpoints; i++) { + priv->epComplete[2 * i] = 0; + HAL_PCD_EP_Close(hpcd, EP_ADDR(2 * i)); + HAL_PCD_EP_Flush(hpcd, EP_ADDR(2 * i)); + priv->epComplete[2 * i + 1] = 0; + HAL_PCD_EP_Close(hpcd, EP_ADDR(2 * i + 1)); + HAL_PCD_EP_Flush(hpcd, EP_ADDR(2 * i + 1)); } - void (USBHAL::*func)(void)=priv->bus_reset; + void (USBHAL::*func)(void) = priv->bus_reset; bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) = priv->ep_realise; (obj->*func)(); - (obj->*ep_realise)(EP0IN, MAX_PACKET_SIZE_EP0,0); - (obj->*ep_realise)(EP0OUT, MAX_PACKET_SIZE_EP0,0); + (obj->*ep_realise)(EP0IN, MAX_PACKET_SIZE_EP0, 0); + (obj->*ep_realise)(EP0OUT, MAX_PACKET_SIZE_EP0, 0); } /* hal pcd handler , used for STM32 HAL PCD Layer */ -uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { +uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) +{ return 0; } -USBHAL::~USBHAL(void) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); - HAL_PCD_DeInit(&hpcd); - delete HALPriv; +USBHAL::~USBHAL(void) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); + HAL_PCD_DeInit(&hpcd); + delete HALPriv; } -void USBHAL::connect(void) { +void USBHAL::connect(void) +{ NVIC_EnableIRQ(USBHAL_IRQn); } -void USBHAL::disconnect(void) { +void USBHAL::disconnect(void) +{ NVIC_DisableIRQ(USBHAL_IRQn); } -void USBHAL::configureDevice(void) { +void USBHAL::configureDevice(void) +{ // Not needed } -void USBHAL::unconfigureDevice(void) { +void USBHAL::unconfigureDevice(void) +{ // Not needed } -void USBHAL::setAddress(uint8_t address) { - HAL_PCD_SetAddress(&hpcd, address); +void USBHAL::setAddress(uint8_t address) +{ + HAL_PCD_SetAddress(&hpcd, address); EP0write(0, 0); } -bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) { +bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) +{ uint32_t epIndex = EP_ADDR(endpoint); uint32_t type; uint32_t len; HAL_StatusTypeDef ret; switch (endpoint) { - case EP0IN: - case EP0OUT: - type = 0; - break; - case EPISO_IN: - case EPISO_OUT: - type = 1; - break; - case EPBULK_IN: - case EPBULK_OUT: - type = 2; - break; - case EPINT_IN: - case EPINT_OUT: - type = 3; - break; + case EP0IN: + case EP0OUT: + type = 0; + break; + case EPISO_IN: + case EPISO_OUT: + type = 1; + break; + case EPBULK_IN: + case EPBULK_OUT: + type = 2; + break; + case EPINT_IN: + case EPINT_OUT: + type = 3; + break; + } + if (maxPacket > MAXTRANSFER_SIZE) { + return false; } - if (maxPacket > MAXTRANSFER_SIZE) return false; if (epIndex & 0x80) { - len = HAL_PCDEx_GetTxFiFo(&hpcd,epIndex & 0x7f); + len = HAL_PCDEx_GetTxFiFo(&hpcd, epIndex & 0x7f); MBED_ASSERT(len >= maxPacket); } ret = HAL_PCD_EP_Open(&hpcd, epIndex, maxPacket, type); - MBED_ASSERT(ret!=HAL_BUSY); - return (ret == HAL_OK) ? true:false; + MBED_ASSERT(ret != HAL_BUSY); + return (ret == HAL_OK) ? true : false; } // read setup packet -void USBHAL::EP0setup(uint8_t *buffer) { +void USBHAL::EP0setup(uint8_t *buffer) +{ memcpy(buffer, hpcd.Setup, MAX_PACKET_SIZE_SETUP); - memset(hpcd.Setup,0,MAX_PACKET_SIZE_SETUP); + memset(hpcd.Setup, 0, MAX_PACKET_SIZE_SETUP); } -void USBHAL::EP0readStage(void) { +void USBHAL::EP0readStage(void) +{ } -void USBHAL::EP0read(void) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData; - uint32_t epIndex = EP_ADDR(EP0OUT); - uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0; - HAL_StatusTypeDef ret; - HALPriv->epComplete[EP0OUT] = 2; - ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, MAX_PACKET_SIZE_EP0 ); - MBED_ASSERT(ret!=HAL_BUSY); +void USBHAL::EP0read(void) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData; + uint32_t epIndex = EP_ADDR(EP0OUT); + uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0; + HAL_StatusTypeDef ret; + HALPriv->epComplete[EP0OUT] = 2; + ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, MAX_PACKET_SIZE_EP0); + MBED_ASSERT(ret != HAL_BUSY); } -uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData; +uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData; uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, 0); - HALPriv->epComplete[EP0OUT] = 0; + HALPriv->epComplete[EP0OUT] = 0; if (length) { uint8_t *buff = (uint8_t *)HALPriv->pBufRx0; memcpy(buffer, buff, length); @@ -234,97 +248,114 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { return length; } -void USBHAL::EP0write(uint8_t *buffer, uint32_t size) { +void USBHAL::EP0write(uint8_t *buffer, uint32_t size) +{ /* check that endpoint maximum size is not exceeding TX fifo */ MBED_ASSERT(hpcd.IN_ep[0].maxpacket >= size); endpointWrite(EP0IN, buffer, size); } -void USBHAL::EP0getWriteResult(void) { +void USBHAL::EP0getWriteResult(void) +{ } -void USBHAL::EP0stall(void) { +void USBHAL::EP0stall(void) +{ stallEndpoint(EP0IN); } -EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); +EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); uint32_t epIndex = EP_ADDR(endpoint); - uint8_t* pBuf = (uint8_t *)HALPriv->pBufRx; - HAL_StatusTypeDef ret; + uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx; + HAL_StatusTypeDef ret; // clean reception end flag before requesting reception HALPriv->epComplete[endpoint] = 2; ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, maximumSize); - MBED_ASSERT(ret!=HAL_BUSY); + MBED_ASSERT(ret != HAL_BUSY); return EP_PENDING; } -EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); - if (HALPriv->epComplete[endpoint]==0) { - /* no reception possible !!! */ - bytesRead = 0; +EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); + if (HALPriv->epComplete[endpoint] == 0) { + /* no reception possible !!! */ + bytesRead = 0; return EP_COMPLETED; - }else if ((HALPriv->epComplete[endpoint]!=1)) - return EP_PENDING; + } else if ((HALPriv->epComplete[endpoint] != 1)) { + return EP_PENDING; + } uint32_t epIndex = EP_ADDR(endpoint); uint8_t *buff = (uint8_t *)HALPriv->pBufRx; uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, epIndex); memcpy(buffer, buff, length); *bytesRead = length; - HALPriv->epComplete[endpoint]= 0; + HALPriv->epComplete[endpoint] = 0; return EP_COMPLETED; } -EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); +EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); uint32_t epIndex = EP_ADDR(endpoint); HAL_StatusTypeDef ret; // clean transmission end flag before requesting transmission HALPriv->epComplete[endpoint] = 2; ret = HAL_PCD_EP_Transmit(&hpcd, epIndex, data, size); - MBED_ASSERT(ret!=HAL_BUSY); + MBED_ASSERT(ret != HAL_BUSY); // update the status - if (ret != HAL_OK) return EP_INVALID; + if (ret != HAL_OK) { + return EP_INVALID; + } // fix me return is too simple return EP_PENDING; } -EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); - if (HALPriv->epComplete[endpoint] == 1) +EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); + if (HALPriv->epComplete[endpoint] == 1) { return EP_COMPLETED; + } return EP_PENDING; } -void USBHAL::stallEndpoint(uint8_t endpoint) { - USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); - HAL_StatusTypeDef ret; - HALPriv->epComplete[endpoint] = 0; - ret = HAL_PCD_EP_SetStall(&hpcd, EP_ADDR(endpoint)); - MBED_ASSERT(ret!=HAL_BUSY); +void USBHAL::stallEndpoint(uint8_t endpoint) +{ + USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData); + HAL_StatusTypeDef ret; + HALPriv->epComplete[endpoint] = 0; + ret = HAL_PCD_EP_SetStall(&hpcd, EP_ADDR(endpoint)); + MBED_ASSERT(ret != HAL_BUSY); } -void USBHAL::unstallEndpoint(uint8_t endpoint) { - HAL_StatusTypeDef ret; +void USBHAL::unstallEndpoint(uint8_t endpoint) +{ + HAL_StatusTypeDef ret; ret = HAL_PCD_EP_ClrStall(&hpcd, EP_ADDR(endpoint)); - MBED_ASSERT(ret!=HAL_BUSY); + MBED_ASSERT(ret != HAL_BUSY); } -bool USBHAL::getEndpointStallState(uint8_t endpoint) { +bool USBHAL::getEndpointStallState(uint8_t endpoint) +{ return false; } -void USBHAL::remoteWakeup(void) { +void USBHAL::remoteWakeup(void) +{ } -void USBHAL::_usbisr(void) { +void USBHAL::_usbisr(void) +{ instance->usbisr(); } -void USBHAL::usbisr(void) { +void USBHAL::usbisr(void) +{ HAL_PCD_IRQHandler(&instance->hpcd); } diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp index a7ef57a6ea..bad5770a64 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp @@ -22,7 +22,7 @@ #include "USBRegs_STM32.h" #include "pinmap.h" -USBHAL * USBHAL::instance; +USBHAL *USBHAL::instance; static volatile int epComplete = 0; @@ -32,11 +32,13 @@ static uint32_t rxFifoCount = 0; static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2]; -uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) { +uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) +{ return 0; } -USBHAL::USBHAL(void) { +USBHAL::USBHAL(void) +{ NVIC_DisableIRQ(OTG_FS_IRQn); epCallback[0] = &USBHAL::EP1_OUT_callback; epCallback[1] = &USBHAL::EP1_IN_callback; @@ -94,32 +96,39 @@ USBHAL::USBHAL(void) { NVIC_SetPriority(OTG_FS_IRQn, 1); } -USBHAL::~USBHAL(void) { +USBHAL::~USBHAL(void) +{ } -void USBHAL::connect(void) { +void USBHAL::connect(void) +{ NVIC_EnableIRQ(OTG_FS_IRQn); } -void USBHAL::disconnect(void) { +void USBHAL::disconnect(void) +{ NVIC_DisableIRQ(OTG_FS_IRQn); } -void USBHAL::configureDevice(void) { +void USBHAL::configureDevice(void) +{ // Not needed } -void USBHAL::unconfigureDevice(void) { +void USBHAL::unconfigureDevice(void) +{ // Not needed } -void USBHAL::setAddress(uint8_t address) { +void USBHAL::setAddress(uint8_t address) +{ OTG_FS->DREGS.DCFG |= (address << 4); EP0write(0, 0); } bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, - uint32_t flags) { + uint32_t flags) +{ uint32_t epIndex = endpoint >> 1; uint32_t type; @@ -151,8 +160,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, if (endpoint == EP0IN) { OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) | (bufferEnd << 0); - } - else { + } else { OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) | (bufferEnd << 0); } @@ -169,8 +177,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, // Unmask the interrupt OTG_FS->DREGS.DAINTMSK |= (1 << epIndex); - } - else { // Out endpoint + } else { // Out endpoint // Set the out EP specific control settings control |= (1 << 26); // CNAK OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control; @@ -182,18 +189,22 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, } // read setup packet -void USBHAL::EP0setup(uint8_t *buffer) { +void USBHAL::EP0setup(uint8_t *buffer) +{ memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0); } -void USBHAL::EP0readStage(void) { +void USBHAL::EP0readStage(void) +{ } -void USBHAL::EP0read(void) { +void USBHAL::EP0read(void) +{ } -uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { - uint32_t* buffer32 = (uint32_t *) buffer; +uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) +{ + uint32_t *buffer32 = (uint32_t *) buffer; uint32_t length = rxFifoCount; for (uint32_t i = 0; i < length; i += 4) { buffer32[i >> 2] = OTG_FS->FIFO[0][0]; @@ -203,14 +214,17 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) { return length; } -void USBHAL::EP0write(uint8_t *buffer, uint32_t size) { +void USBHAL::EP0write(uint8_t *buffer, uint32_t size) +{ endpointWrite(0, buffer, size); } -void USBHAL::EP0getWriteResult(void) { +void USBHAL::EP0getWriteResult(void) +{ } -void USBHAL::EP0stall(void) { +void USBHAL::EP0stall(void) +{ // If we stall the out endpoint here then we have problems transferring // and setup requests after the (stalled) get device qualifier requests. // TODO: Find out if this is correct behavior, or whether we are doing @@ -219,12 +233,13 @@ void USBHAL::EP0stall(void) { // stallEndpoint(EP0OUT); } -EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { +EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) +{ uint32_t epIndex = endpoint >> 1; uint32_t size = (1 << 19) | // 1 packet (maximumSize << 0); // Packet size // if (endpoint == EP0OUT) { - size |= (1 << 29); // 1 setup packet + size |= (1 << 29); // 1 setup packet // } OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size; OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint @@ -234,12 +249,13 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) { return EP_PENDING; } -EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) { +EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead) +{ if (!(epComplete & (1 << endpoint))) { return EP_PENDING; } - uint32_t* buffer32 = (uint32_t *) buffer; + uint32_t *buffer32 = (uint32_t *) buffer; uint32_t length = rxFifoCount; for (uint32_t i = 0; i < length; i += 4) { buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0]; @@ -249,7 +265,8 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_ return EP_COMPLETED; } -EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) { +EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) +{ uint32_t epIndex = endpoint >> 1; OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet (size << 0); // Size of packet @@ -259,7 +276,7 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2)); - for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) { + for (uint32_t i = 0; i < (size + 3) >> 2; i++, data += 4) { OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data; } @@ -268,7 +285,8 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) return EP_PENDING; } -EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) { +EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) +{ if (epComplete & (1 << endpoint)) { epComplete &= ~(1 << endpoint); return EP_COMPLETED; @@ -277,36 +295,41 @@ EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) { return EP_PENDING; } -void USBHAL::stallEndpoint(uint8_t endpoint) { +void USBHAL::stallEndpoint(uint8_t endpoint) +{ if (endpoint & 0x1) { // In EP OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable (1 << 21); // Stall - } - else { // Out EP + } else { // Out EP OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable (1 << 21); // Stall } } -void USBHAL::unstallEndpoint(uint8_t endpoint) { +void USBHAL::unstallEndpoint(uint8_t endpoint) +{ } -bool USBHAL::getEndpointStallState(uint8_t endpoint) { +bool USBHAL::getEndpointStallState(uint8_t endpoint) +{ return false; } -void USBHAL::remoteWakeup(void) { +void USBHAL::remoteWakeup(void) +{ } -void USBHAL::_usbisr(void) { +void USBHAL::_usbisr(void) +{ instance->usbisr(); } -void USBHAL::usbisr(void) { +void USBHAL::usbisr(void) +{ if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend suspendStateChanged(1); }; @@ -347,7 +370,7 @@ void USBHAL::usbisr(void) { if (type == 0x6) { // Setup packet - for (uint32_t i=0; i> 2] = OTG_FS->FIFO[0][i >> 2]; } rxFifoCount = 0; @@ -363,8 +386,7 @@ void USBHAL::usbisr(void) { // Out packet if (endpoint == EP0OUT) { EP0out(); - } - else { + } else { epComplete |= (1 << endpoint); if ((instance->*(epCallback[endpoint - 2]))()) { epComplete &= ~(1 << endpoint); @@ -372,7 +394,7 @@ void USBHAL::usbisr(void) { } } - for (uint32_t i=0; iFIFO[0][0]; } OTG_FS->GREGS.GINTSTS = (1 << 4); @@ -380,7 +402,7 @@ void USBHAL::usbisr(void) { if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt // Loop through the in endpoints - for (uint32_t i=0; i<4; i++) { + for (uint32_t i = 0; i < 4; i++) { if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h index 3e11a49c15..359426fb37 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h @@ -28,97 +28,90 @@ #ifndef __USB_OTG_REGS_H__ #define __USB_OTG_REGS_H__ -typedef struct //000h -{ - __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */ +typedef struct { //000h + __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */ } USB_OTG_GREGS; -typedef struct // 800h -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ +typedef struct { // 800h + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ } USB_OTG_DREGS; -typedef struct -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - uint32_t Reserved14; - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +typedef struct { + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + uint32_t Reserved14; + __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ } USB_OTG_INEPREGS; -typedef struct -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - uint32_t Reserved14[3]; +typedef struct { + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + uint32_t Reserved14[3]; } USB_OTG_OUTEPREGS; -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +typedef struct { + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ } USB_OTG_HREGS; -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - uint32_t Reserved[3]; +typedef struct { + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + uint32_t Reserved[3]; } USB_OTG_HC_REGS; -typedef struct -{ +typedef struct { USB_OTG_GREGS GREGS; uint32_t RESERVED0[188]; USB_OTG_HREGS HREGS; diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBEndpoint_STM.cpp b/features/unsupported/USBHost/targets/TARGET_STM/USBEndpoint_STM.cpp index a12d60e821..2db4bf625c 100644 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBEndpoint_STM.cpp +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBEndpoint_STM.cpp @@ -19,13 +19,13 @@ #include "USBEndpoint.h" extern uint32_t HAL_HCD_HC_GetMaxPacket(HCD_HandleTypeDef *hhcd, uint8_t chn_num); extern uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd, uint8_t chn_num); -extern void HAL_HCD_DisableInt(HCD_HandleTypeDef* hhcd, uint8_t chn_num); -extern void HAL_HCD_EnableInt(HCD_HandleTypeDef* hhcd, uint8_t chn_num); +extern void HAL_HCD_DisableInt(HCD_HandleTypeDef *hhcd, uint8_t chn_num); +extern void HAL_HCD_EnableInt(HCD_HandleTypeDef *hhcd, uint8_t chn_num); -void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD* td_list_[2]) +void USBEndpoint::init(HCED *hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD *td_list_[2]) { HCD_HandleTypeDef *hhcd; uint32_t *addr; @@ -36,7 +36,7 @@ void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir setup = (type == CONTROL_ENDPOINT) ? true : false; //TDs have been allocated by the host - memcpy((HCTD**)td_list, td_list_, sizeof(HCTD*)*2); //TODO: Maybe should add a param for td_list size... at least a define + memcpy((HCTD **)td_list, td_list_, sizeof(HCTD *) * 2); //TODO: Maybe should add a param for td_list size... at least a define memset(td_list_[0], 0, sizeof(HCTD)); memset(td_list_[1], 0, sizeof(HCTD)); @@ -56,11 +56,11 @@ void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir /* remove potential post pending from previous endpoint */ ep_queue.get(0); intf_nb = 0; - hhcd = (HCD_HandleTypeDef*)hced->hhcd; + hhcd = (HCD_HandleTypeDef *)hced->hhcd; addr = &((uint32_t *)hhcd->pData)[hced->ch_num]; *addr = 0; state = USB_TYPE_IDLE; - speed =false; + speed = false; } void USBEndpoint::setSize(uint32_t size) { @@ -77,7 +77,7 @@ void USBEndpoint::setDeviceAddress(uint8_t addr) if (this->speed) { USB_WARN("small speed device on hub not supported"); } - MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef*)hced->hhcd,hced->ch_num, address, addr, hcd_speed, type, size)!=HAL_BUSY); + MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num, address, addr, hcd_speed, type, size) != HAL_BUSY); this->device_address = addr; } @@ -98,26 +98,26 @@ void USBEndpoint::setState(USB_TYPE st) state = st; if (st == USB_TYPE_FREE) { - HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef*)hced->hhcd; + HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)hced->hhcd; uint32_t *addr = &((uint32_t *)hhcd->pData)[hced->ch_num]; if ((*addr) && (type != INTERRUPT_ENDPOINT)) { - this->ep_queue.put((uint8_t*)1); + this->ep_queue.put((uint8_t *)1); } - MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num)!=HAL_BUSY); - HAL_HCD_DisableInt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num); + MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num) != HAL_BUSY); + HAL_HCD_DisableInt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num); *addr = 0; } if (st == USB_TYPE_ERROR) { - MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num)!=HAL_BUSY); - HAL_HCD_DisableInt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num); + MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num) != HAL_BUSY); + HAL_HCD_DisableInt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num); } if (st == USB_TYPE_ERROR) { uint8_t hcd_speed = HCD_SPEED_FULL; /* small speed device with hub not supported if (this->speed) hcd_speed = HCD_SPEED_LOW;*/ - MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef*)hced->hhcd,hced->ch_num, address, 0, hcd_speed, type, size)!=HAL_BUSY); + MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num, address, 0, hcd_speed, type, size) != HAL_BUSY); } } @@ -128,7 +128,7 @@ extern uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd, uint8_t chn_num); USB_TYPE USBEndpoint::queueTransfer() { - HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef*)hced->hhcd; + HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)hced->hhcd; uint32_t *addr = &((uint32_t *)hhcd->pData)[hced->ch_num]; uint32_t type = HAL_HCD_HC_GetType(hhcd, hced->ch_num); uint32_t max_size = HAL_HCD_HC_GetMaxPacket(hhcd, hced->ch_num); @@ -138,14 +138,14 @@ USB_TYPE USBEndpoint::queueTransfer() return USB_TYPE_FREE; } ep_queue.get(0); - MBED_ASSERT(*addr ==0); + MBED_ASSERT(*addr == 0); transfer_len = td_current->size <= max_size ? td_current->size : max_size; buf_start = (uint8_t *)td_current->currBufPtr; //Now add this free TD at this end of the queue state = USB_TYPE_PROCESSING; /* one request */ - td_current->nextTD = (hcTd*)0; + td_current->nextTD = (hcTd *)0; #if defined(MAX_NYET_RETRY) td_current->retry = 0; #endif @@ -154,28 +154,28 @@ USB_TYPE USBEndpoint::queueTransfer() /* dir /setup is inverted for ST */ /* token is useful only ctrl endpoint */ /* last parameter is ping ? */ - MBED_ASSERT(HAL_HCD_HC_SubmitRequest((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num, dir-1, type,!setup,(uint8_t*) td_current->currBufPtr, transfer_len, 0)==HAL_OK); - HAL_HCD_EnableInt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num); + MBED_ASSERT(HAL_HCD_HC_SubmitRequest((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num, dir - 1, type, !setup, (uint8_t *) td_current->currBufPtr, transfer_len, 0) == HAL_OK); + HAL_HCD_EnableInt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num); return USB_TYPE_PROCESSING; } -void USBEndpoint::unqueueTransfer(volatile HCTD * td) +void USBEndpoint::unqueueTransfer(volatile HCTD *td) { - if (state==USB_TYPE_FREE) { + if (state == USB_TYPE_FREE) { return; } - uint32_t *addr = &((uint32_t *)((HCD_HandleTypeDef*)hced->hhcd)->pData)[hced->ch_num]; - td->state=0; - td->currBufPtr=0; - td->size=0; - td->nextTD=0; + uint32_t *addr = &((uint32_t *)((HCD_HandleTypeDef *)hced->hhcd)->pData)[hced->ch_num]; + td->state = 0; + td->currBufPtr = 0; + td->size = 0; + td->nextTD = 0; *addr = 0; td_current = td_next; td_next = td; } -void USBEndpoint::queueEndpoint(USBEndpoint * ed) +void USBEndpoint::queueEndpoint(USBEndpoint *ed) { nextEp = ed; } diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp index ec9d9785d8..eb58a9d1a4 100644 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp @@ -24,63 +24,63 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) { - USBHALHost_Private_t *priv=(USBHALHost_Private_t *)(hhcd->pData); - USBHALHost *obj= priv->inst; - void (USBHALHost::*func)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent ) = priv->deviceConnected; - (obj->*func)(0,1,0,NULL); + USBHALHost_Private_t *priv = (USBHALHost_Private_t *)(hhcd->pData); + USBHALHost *obj = priv->inst; + void (USBHALHost::*func)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent) = priv->deviceConnected; + (obj->*func)(0, 1, 0, NULL); } void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) { - USBHALHost_Private_t *priv=(USBHALHost_Private_t *)(hhcd->pData); - USBHALHost *obj= priv->inst; - void (USBHALHost::*func1)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr)= priv->deviceDisconnected; - (obj->*func1)(0,1,(USBHostHub *)NULL,0); + USBHALHost_Private_t *priv = (USBHALHost_Private_t *)(hhcd->pData); + USBHALHost *obj = priv->inst; + void (USBHALHost::*func1)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr) = priv->deviceDisconnected; + (obj->*func1)(0, 1, (USBHostHub *)NULL, 0); } -int HAL_HCD_HC_GetDirection(HCD_HandleTypeDef *hhcd,uint8_t chnum) +int HAL_HCD_HC_GetDirection(HCD_HandleTypeDef *hhcd, uint8_t chnum) { /* useful for transmission */ return hhcd->hc[chnum].ep_is_in; } -uint32_t HAL_HCD_HC_GetMaxPacket(HCD_HandleTypeDef *hhcd,uint8_t chnum) +uint32_t HAL_HCD_HC_GetMaxPacket(HCD_HandleTypeDef *hhcd, uint8_t chnum) { /* useful for transmission */ return hhcd->hc[chnum].max_packet; } -void HAL_HCD_EnableInt(HCD_HandleTypeDef *hhcd,uint8_t chnum) +void HAL_HCD_EnableInt(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USBx_HOST->HAINTMSK |= (1 << chnum); } -void HAL_HCD_DisableInt(HCD_HandleTypeDef *hhcd,uint8_t chnum) +void HAL_HCD_DisableInt(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; USBx_HOST->HAINTMSK &= ~(1 << chnum); } -uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd,uint8_t chnum) +uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd, uint8_t chnum) { /* useful for transmission */ return hhcd->hc[chnum].ep_type; } -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum, HCD_URBStateTypeDef urb_state) +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) { - USBHALHost_Private_t *priv=(USBHALHost_Private_t *)(hhcd->pData); - USBHALHost *obj= priv->inst; - void (USBHALHost::*func)(volatile uint32_t addr)= priv->transferCompleted; + USBHALHost_Private_t *priv = (USBHALHost_Private_t *)(hhcd->pData); + USBHALHost *obj = priv->inst; + void (USBHALHost::*func)(volatile uint32_t addr) = priv->transferCompleted; uint32_t addr = priv->addr[chnum]; uint32_t max_size = HAL_HCD_HC_GetMaxPacket(hhcd, chnum); uint32_t type = HAL_HCD_HC_GetType(hhcd, chnum); - uint32_t dir = HAL_HCD_HC_GetDirection(hhcd,chnum); + uint32_t dir = HAL_HCD_HC_GetDirection(hhcd, chnum); uint32_t length; - if ( (addr!=0)) { + if ((addr != 0)) { HCTD *td = (HCTD *)addr; - if ((type == EP_TYPE_BULK) || (type == EP_TYPE_CTRL )) { + if ((type == EP_TYPE_BULK) || (type == EP_TYPE_CTRL)) { switch (urb_state) { case URB_DONE: #if defined(MAX_NYET_RETRY) @@ -91,7 +91,7 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum, td->currBufPtr += max_size; td->size -= max_size; length = td->size <= max_size ? td->size : max_size; - MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir ,type , !td->setup,(uint8_t*) td->currBufPtr, length, 0)==HAL_OK); + MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir, type, !td->setup, (uint8_t *) td->currBufPtr, length, 0) == HAL_OK); HAL_HCD_EnableInt(hhcd, chnum); return; } @@ -106,7 +106,7 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum, td->retry++; #endif length = td->size <= max_size ? td->size : max_size; - MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir ,type , !td->setup,(uint8_t*) td->currBufPtr, length, 0)==HAL_OK); + MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir, type, !td->setup, (uint8_t *) td->currBufPtr, length, 0) == HAL_OK); HAL_HCD_EnableInt(hhcd, chnum); return; #if defined(MAX_NYET_RETRY) @@ -117,25 +117,25 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum, break; } } - if ((type == EP_TYPE_INTR) ) { + if ((type == EP_TYPE_INTR)) { /* reply a packet of length NULL, this will be analyse in call back * for mouse or hub */ - td->state =USB_TYPE_IDLE ; + td->state = USB_TYPE_IDLE ; HAL_HCD_DisableInt(hhcd, chnum); } else { td->state = (urb_state == URB_DONE) ? USB_TYPE_IDLE : USB_TYPE_ERROR; } - td->currBufPtr +=HAL_HCD_HC_GetXferCount(hhcd, chnum); + td->currBufPtr += HAL_HCD_HC_GetXferCount(hhcd, chnum); (obj->*func)(addr); } else { - if (urb_state !=0) { - USB_DBG_EVENT("spurious %d %d",chnum, urb_state); + if (urb_state != 0) { + USB_DBG_EVENT("spurious %d %d", chnum, urb_state); } } } -USBHALHost * USBHALHost::instHost; +USBHALHost *USBHALHost::instHost; void USBHALHost::init() @@ -209,37 +209,37 @@ bool USBHALHost::disableList(ENDPOINT_TYPE type) void USBHALHost::memInit() { - usb_hcca = (volatile HCD_HandleTypeDef *)usb_buf; + usb_hcca = (volatile HCD_HandleTypeDef *)usb_buf; usb_edBuf = usb_buf + HCCA_SIZE; - usb_tdBuf = usb_buf + HCCA_SIZE +(MAX_ENDPOINT*ED_SIZE); + usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT * ED_SIZE); /* init channel */ - memset((void*)usb_buf,0, TOTAL_SIZE); - for (int i=0; i < MAX_ENDPOINT; i++) { - HCED *hced = (HCED*)(usb_edBuf + i*ED_SIZE); + memset((void *)usb_buf, 0, TOTAL_SIZE); + for (int i = 0; i < MAX_ENDPOINT; i++) { + HCED *hced = (HCED *)(usb_edBuf + i * ED_SIZE); hced->ch_num = i; hced->hhcd = (HCCA *) usb_hcca; } } -volatile uint8_t * USBHALHost::getED() +volatile uint8_t *USBHALHost::getED() { for (int i = 0; i < MAX_ENDPOINT; i++) { - if ( !edBufAlloc[i] ) { + if (!edBufAlloc[i]) { edBufAlloc[i] = true; - return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE); + return (volatile uint8_t *)(usb_edBuf + i * ED_SIZE); } } perror("Could not allocate ED\r\n"); return NULL; //Could not alloc ED } -volatile uint8_t * USBHALHost::getTD() +volatile uint8_t *USBHALHost::getTD() { int i; for (i = 0; i < MAX_TD; i++) { - if ( !tdBufAlloc[i] ) { + if (!tdBufAlloc[i]) { tdBufAlloc[i] = true; - return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE); + return (volatile uint8_t *)(usb_tdBuf + i * TD_SIZE); } } perror("Could not allocate TD\r\n"); @@ -247,14 +247,14 @@ volatile uint8_t * USBHALHost::getTD() } -void USBHALHost::freeED(volatile uint8_t * ed) +void USBHALHost::freeED(volatile uint8_t *ed) { int i; i = (ed - usb_edBuf) / ED_SIZE; edBufAlloc[i] = false; } -void USBHALHost::freeTD(volatile uint8_t * td) +void USBHALHost::freeTD(volatile uint8_t *td) { int i; i = (td - usb_tdBuf) / TD_SIZE; diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h index 02fb5ef4c9..dd741ecd03 100644 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h @@ -47,8 +47,8 @@ typedef struct { * endpoint */ volatile uint32_t addr[MAX_ENDPOINT]; USBHALHost *inst; - void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent); - void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr); + void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub *hub_parent); + void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub *hub_parent, volatile uint32_t addr); void (USBHALHost::*transferCompleted)(volatile uint32_t addr); } USBHALHost_Private_t; @@ -120,7 +120,7 @@ static gpio_t gpio_powerpin; #endif -void usb_vbus( uint8_t state) +void usb_vbus(uint8_t state) { if (state == 0) { gpio_write(&gpio_powerpin, USB_POWER_OFF); @@ -135,14 +135,14 @@ USBHALHost::USBHALHost() { instHost = this; HCD_HandleTypeDef *hhcd = {0}; - USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t); + USBHALHost_Private_t *HALPriv = new (USBHALHost_Private_t); memset(HALPriv, 0, sizeof(USBHALHost_Private_t)); memInit(); - memset((void*)usb_hcca, 0, HCCA_SIZE); + memset((void *)usb_hcca, 0, HCCA_SIZE); hhcd = (HCD_HandleTypeDef *)usb_hcca; - hhcd->pData = (void*)HALPriv; + hhcd->pData = (void *)HALPriv; #if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI) hhcd->Instance = USB_OTG_HS; @@ -169,7 +169,7 @@ USBHALHost::USBHALHost() for (int i = 0; i < MAX_ENDPOINT; i++) { edBufAlloc[i] = false; - HALPriv->addr[i] = (uint32_t)-1; + HALPriv->addr[i] = (uint32_t) - 1; } for (int i = 0; i < MAX_TD; i++) { diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index d51be1905a..673f5f58b9 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -37,7 +37,7 @@ extern "C" { #endif /* STM PIN data as used in pin_function is coded on 32 bits as below - * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog + * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog * [3] Output Push-Pull / Open Drain (as in OTYPER reg) * [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc * [7:6] Reserved for speed config (as in OSPEEDR), but not used yet diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h index f200e31f11..a5e8457318 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h @@ -46,7 +46,7 @@ typedef enum { } DACName; typedef enum { - UART_1 = (int)USART1_BASE, + UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE } UARTName; @@ -63,7 +63,7 @@ typedef enum { typedef enum { PWM_1 = (int)TIM1_BASE, PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, + PWM_3 = (int)TIM3_BASE, PWM_14 = (int)TIM14_BASE, PWM_15 = (int)TIM15_BASE, PWM_16 = (int)TIM16_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h index 1b14225caf..6b25d5c481 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h @@ -49,17 +49,17 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -71,8 +71,8 @@ typedef enum { PB_0 = 0x10, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, @@ -87,8 +87,8 @@ typedef enum { PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -230,13 +230,13 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h index 45a37ac57d..d0f3565f66 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h @@ -49,7 +49,7 @@ struct gpio_irq_s { struct port_s { PortName port; uint32_t mask; - PinDirection direction; + PinDirection direction; __IO uint32_t *reg_in; __IO uint32_t *reg_out; }; diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h index f9413a8369..7fadb2f6f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h @@ -53,11 +53,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -69,8 +69,8 @@ typedef enum { PB_0 = 0x10, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, @@ -85,8 +85,8 @@ typedef enum { PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -175,13 +175,13 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PC_7, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h index 7c66e2ec0f..7dc5959b60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h @@ -53,11 +53,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -68,10 +68,10 @@ typedef enum { PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, @@ -142,11 +142,11 @@ typedef enum { SPI_CS = PB_1, PWM_OUT = PB_0, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h index 79ddecfcdc..d23462cf20 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h @@ -53,11 +53,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -68,10 +68,10 @@ typedef enum { PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_3 = 0x13, PB_4 = 0x14, PB_5 = 0x15, @@ -140,18 +140,18 @@ typedef enum { SPI_CS = PA_4, PWM_OUT = PB_0, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_4, USB_NOE_ALT0 = PA_13, USB_NOE_ALT1 = PA_15, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h index 6c8afc706f..c955ac438a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h @@ -53,11 +53,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -69,8 +69,8 @@ typedef enum { PB_0 = 0x10, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, @@ -85,8 +85,8 @@ typedef enum { PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -99,9 +99,9 @@ typedef enum { PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -173,18 +173,18 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h index 1277acc8a2..a4566355c9 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h @@ -53,11 +53,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -68,10 +68,10 @@ typedef enum { PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, @@ -85,10 +85,10 @@ typedef enum { PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -101,9 +101,9 @@ typedef enum { PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -175,18 +175,18 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h index 59f6d34975..5de08db82a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h @@ -53,11 +53,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -68,10 +68,10 @@ typedef enum { PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, @@ -85,15 +85,15 @@ typedef enum { PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT0 = PC_0 | ALT0, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT0 = PC_1 | ALT0, PC_2 = 0x22, PC_3 = 0x23, PC_4 = 0x24, @@ -103,9 +103,9 @@ typedef enum { PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -178,13 +178,13 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_4, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, SYS_WKUP1 = PA_0, diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c index da73e70b30..182ada25c2 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c @@ -35,7 +35,8 @@ #include "mbed_error.h" #include "PeripheralPins.h" -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object @@ -73,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = (DAC_TypeDef *)(obj->dac); obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ // Reset DAC and disable clock __HAL_RCC_DAC1_FORCE_RESET(); __HAL_RCC_DAC1_RELEASE_RESET(); diff --git a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c index 9a2d7c4c8e..169128d994 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c @@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, } } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) { address = address + MIN_PROG_SIZE; data = data + MIN_PROG_SIZE; } else { diff --git a/targets/TARGET_STM/TARGET_STM32F0/pin_device.h b/targets/TARGET_STM/TARGET_STM32F0/pin_device.h index 158ad745b3..79adc55b34 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F0/pin_device.h @@ -56,14 +56,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32F0/pwmout_device.c index 369c7443ec..9837b7be3d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index d3f784e127..ff5b03ace3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -33,13 +33,13 @@ #include "serial_api_hal.h" #if defined (TARGET_STM32F031K6) - #define UART_NUM (1) +#define UART_NUM (1) #elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6) - #define UART_NUM (2) +#define UART_NUM (2) #elif defined (TARGET_STM32F070RB) || defined (TARGET_STM32F072RB) - #define UART_NUM (4) +#define UART_NUM (4) #else - #define UART_NUM (8) // max value (TARGET_STM32F091RC) +#define UART_NUM (8) // max value (TARGET_STM32F091RC) #endif uint32_t serial_irq_ids[UART_NUM] = {0}; @@ -59,7 +59,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { @@ -100,45 +100,45 @@ static void uart3_8_irq(void) { #if defined(TARGET_STM32F091RC) #if defined(USART3_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) { - uart_irq(UART_3); - } + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) { + uart_irq(UART_3); + } #endif #if defined(USART4_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) { - uart_irq(UART_4); - } + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) { + uart_irq(UART_4); + } #endif #if defined(USART5_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) { - uart_irq(UART_5); - } + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) { + uart_irq(UART_5); + } #endif #if defined(USART6_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) { - uart_irq(UART_6); - } + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) { + uart_irq(UART_6); + } #endif #if defined(USART7_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) { - uart_irq(UART_7); - } + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) { + uart_irq(UART_7); + } #endif #if defined(USART8_BASE) - if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) { - uart_irq(UART_8); - } + if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) { + uart_irq(UART_8); + } #endif #else // TARGET_STM32F070RB, TARGET_STM32F072RB #if defined(USART3_BASE) - if (USART3->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) { - uart_irq(UART_3); - } + if (USART3->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) { + uart_irq(UART_3); + } #endif #if defined(USART4_BASE) - if (USART4->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) { - uart_irq(UART_4); - } + if (USART4->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) { + uart_irq(UART_4); + } #endif #endif } @@ -146,7 +146,7 @@ static void uart3_8_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -297,7 +297,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -317,7 +317,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -339,7 +339,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -347,9 +347,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -439,7 +439,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -453,28 +453,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -484,14 +484,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -512,18 +512,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -533,8 +533,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -546,10 +546,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -562,20 +562,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); } @@ -600,49 +602,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -650,7 +652,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -664,11 +666,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -678,17 +680,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -705,20 +707,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -748,9 +750,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -780,7 +782,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32F0/spi_api.c b/targets/TARGET_STM/TARGET_STM32F0/spi_api.c index d7dc4c10dd..7b8ff0323b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/spi_api.c @@ -37,17 +37,18 @@ #include "PeripheralPins.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { - /* SPI_1, SPI_2. Source CLK is PCKL1 */ +int spi_get_clock_freq(spi_t *obj) +{ + /* SPI_1, SPI_2. Source CLK is PCKL1 */ return HAL_RCC_GetPCLK1Freq(); } diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c index f6e440a008..5deb5abe5c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c @@ -172,12 +172,12 @@ const PinMap PinMap_SPI_SSEL[] = { const PinMap PinMap_CAN_RD[] = { {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, - {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)}, {NC, NC, 0} }; const PinMap PinMap_CAN_TD[] = { {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, - {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h index ae5bfa9220..07c0251794 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h @@ -45,7 +45,7 @@ typedef enum { } DACName; typedef enum { - UART_1 = (int)USART1_BASE, + UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, UART_3 = (int)USART3_BASE } UARTName; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h index fe1237a88c..c750ac77d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h @@ -174,13 +174,13 @@ typedef enum { SPI_CS = PB_12, PWM_OUT = PB_8, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PD_0, RCC_OSC_OUT = PD_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h index 493408b24f..5ddc595468 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h @@ -49,7 +49,7 @@ struct gpio_irq_s { struct port_s { PortName port; uint32_t mask; - PinDirection direction; + PinDirection direction; __IO uint32_t *reg_in; __IO uint32_t *reg_out; }; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c index a994b6305b..8cb87daa45 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c @@ -109,8 +109,8 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3 {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4 {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1 - {PB_0 , PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3 - {PB_1 , PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4 + {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4 {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 // Connected to SWO {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1 {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2 diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h index 4051832ced..c31048e9d7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h @@ -154,17 +154,17 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PD_0, RCC_OSC_OUT = PD_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c index 46c6040ae4..8c07436265 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c @@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, } } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) { address = address + MIN_PROG_SIZE; data = data + MIN_PROG_SIZE; } else { diff --git a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h index 01a6d7d60e..e431932180 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h @@ -58,40 +58,40 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af if (afnum > 0) { switch (afnum) { - case 1: // Remap SPI1 - __HAL_AFIO_REMAP_SPI1_ENABLE(); - break; - case 2: // Remap I2C1 - __HAL_AFIO_REMAP_I2C1_ENABLE(); - break; - case 3: // Remap USART1 - __HAL_AFIO_REMAP_USART1_ENABLE(); - break; - case 4: // Remap USART2 - __HAL_AFIO_REMAP_USART2_ENABLE(); - break; - case 5: // Partial Remap USART3 - __HAL_AFIO_REMAP_USART3_PARTIAL(); - break; - case 6: // Partial Remap TIM1 - __HAL_AFIO_REMAP_TIM1_PARTIAL(); - break; - case 7: // Partial Remap TIM3 - __HAL_AFIO_REMAP_TIM3_PARTIAL(); - break; - case 8: // Full Remap TIM2 - __HAL_AFIO_REMAP_TIM2_ENABLE(); - break; - case 9: // Full Remap TIM3 - __HAL_AFIO_REMAP_TIM3_ENABLE(); - break; + case 1: // Remap SPI1 + __HAL_AFIO_REMAP_SPI1_ENABLE(); + break; + case 2: // Remap I2C1 + __HAL_AFIO_REMAP_I2C1_ENABLE(); + break; + case 3: // Remap USART1 + __HAL_AFIO_REMAP_USART1_ENABLE(); + break; + case 4: // Remap USART2 + __HAL_AFIO_REMAP_USART2_ENABLE(); + break; + case 5: // Partial Remap USART3 + __HAL_AFIO_REMAP_USART3_PARTIAL(); + break; + case 6: // Partial Remap TIM1 + __HAL_AFIO_REMAP_TIM1_PARTIAL(); + break; + case 7: // Partial Remap TIM3 + __HAL_AFIO_REMAP_TIM3_PARTIAL(); + break; + case 8: // Full Remap TIM2 + __HAL_AFIO_REMAP_TIM2_ENABLE(); + break; + case 9: // Full Remap TIM3 + __HAL_AFIO_REMAP_TIM3_ENABLE(); + break; #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) - case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9 - __HAL_AFIO_REMAP_CAN1_2(); - break; + case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9 + __HAL_AFIO_REMAP_CAN1_2(); + break; #endif - default: - break; + default: + break; } } } @@ -102,19 +102,22 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 switch (pull_config) { case GPIO_PULLUP: - if (function == LL_GPIO_MODE_FLOATING) + if (function == LL_GPIO_MODE_FLOATING) { LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT); + } LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP); break; case GPIO_PULLDOWN: - if (function == LL_GPIO_MODE_FLOATING) + if (function == LL_GPIO_MODE_FLOATING) { LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT); + } LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN); break; default: /* Input+NoPull = Floating for F1 family */ - if (function == LL_GPIO_MODE_INPUT) + if (function == LL_GPIO_MODE_INPUT) { LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_FLOATING); + } break; } } diff --git a/targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c index 3331a660ca..ab311a1e8b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM1_BASE) {PWM_1, PWMOUT_ON_APB2}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c index 6f344e9f1f..5dd4e4a9d4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c @@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { @@ -97,7 +97,7 @@ static void uart3_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -214,7 +214,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -234,7 +234,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -256,7 +256,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -264,9 +264,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -313,7 +313,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -327,28 +327,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -358,14 +358,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -386,18 +386,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -407,8 +407,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -420,10 +420,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -436,20 +436,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { @@ -471,49 +473,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -521,7 +523,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -535,11 +537,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -549,17 +551,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -576,20 +578,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -619,9 +621,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -651,7 +653,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32F1/spi_api.c b/targets/TARGET_STM/TARGET_STM32F1/spi_api.c index 6cd4d8af9d..2ce1b6caa3 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/spi_api.c @@ -37,31 +37,32 @@ #include "PeripheralPins.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: - /* SPI_1. Source CLK is PCKL2 */ - spi_hz = HAL_RCC_GetPCLK2Freq(); - break; - case SPI_2: - /* SPI_2. Source CLK is PCKL1 */ - spi_hz = HAL_RCC_GetPCLK1Freq(); - break; - default: - error("CLK: SPI instance not set"); + /* SPI_1. Source CLK is PCKL2 */ + spi_hz = HAL_RCC_GetPCLK2Freq(); + break; + case SPI_2: + /* SPI_2. Source CLK is PCKL1 */ + spi_hz = HAL_RCC_GetPCLK1Freq(); + break; + default: + error("CLK: SPI instance not set"); break; } return spi_hz; diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h index f084629485..697dd02bc1 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = 0x00|ALT0, - PA_0_ALT1 = 0x00|ALT1, + PA_0_ALT0 = 0x00 | ALT0, + PA_0_ALT1 = 0x00 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = 0x03|ALT0, - PA_3_ALT1 = 0x03|ALT1, + PA_3_ALT0 = 0x03 | ALT0, + PA_3_ALT1 = 0x03 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = 0x04|ALT0, + PA_4_ALT0 = 0x04 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = 0x05|ALT0, + PA_5_ALT0 = 0x05 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = 0x06|ALT0, + PA_6_ALT0 = 0x06 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = 0x07|ALT0, - PA_7_ALT1 = 0x07|ALT1, - PA_7_ALT2 = 0x07|ALT2, + PA_7_ALT0 = 0x07 | ALT0, + PA_7_ALT1 = 0x07 | ALT1, + PA_7_ALT2 = 0x07 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,63 +76,63 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = 0x0F|ALT0, + PA_15_ALT0 = 0x0F | ALT0, PB_0 = 0x10, - PB_0_ALT0 = 0x10|ALT0, - PB_0_ALT1 = 0x10|ALT1, - PB_0_ALT2 = 0x10|ALT2, + PB_0_ALT0 = 0x10 | ALT0, + PB_0_ALT1 = 0x10 | ALT1, + PB_0_ALT2 = 0x10 | ALT2, PB_1 = 0x11, - PB_1_ALT0 = 0x11|ALT0, - PB_1_ALT1 = 0x11|ALT1, + PB_1_ALT0 = 0x11 | ALT0, + PB_1_ALT1 = 0x11 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = 0x13|ALT0, + PB_3_ALT0 = 0x13 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = 0x14|ALT0, + PB_4_ALT0 = 0x14 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = 0x15|ALT0, + PB_5_ALT0 = 0x15 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = 0x18|ALT0, + PB_8_ALT0 = 0x18 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = 0x19|ALT0, + PB_9_ALT0 = 0x19 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = 0x1F|ALT0, - PB_15_ALT1 = 0x1F|ALT1, + PB_15_ALT0 = 0x1F | ALT0, + PB_15_ALT1 = 0x1F | ALT1, PC_0 = 0x20, - PC_0_ALT0 = 0x20|ALT0, - PC_0_ALT1 = 0x20|ALT1, + PC_0_ALT0 = 0x20 | ALT0, + PC_0_ALT1 = 0x20 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = 0x22|ALT0, - PC_2_ALT1 = 0x22|ALT1, + PC_2_ALT0 = 0x22 | ALT0, + PC_2_ALT1 = 0x22 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = 0x23|ALT0, - PC_3_ALT1 = 0x23|ALT1, + PC_3_ALT0 = 0x23 | ALT0, + PC_3_ALT1 = 0x23 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = 0x26|ALT0, + PC_6_ALT0 = 0x26 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = 0x27|ALT0, + PC_7_ALT0 = 0x27 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = 0x28|ALT0, + PC_8_ALT0 = 0x28 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = 0x29|ALT0, + PC_9_ALT0 = 0x29 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -272,7 +272,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -296,7 +296,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -323,13 +323,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c index 3976d5b084..8bcdfe84d8 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c @@ -74,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) obj->handle.Instance = (DAC_TypeDef *)(obj->dac); obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c index 321647cf09..0c76349ad3 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c @@ -14,7 +14,7 @@ * limitations under the License. */ - #if DEVICE_FLASH +#if DEVICE_FLASH #include "flash_api.h" #include "flash_data.h" @@ -99,10 +99,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, return -1; } - /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, - you have to make sure that these data are rewritten before they are accessed during code - execution. If this cannot be done safely, it is recommended to flush the caches by setting the - DCRST and ICRST bits in the FLASH_CR register. */ + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ __HAL_FLASH_DATA_CACHE_DISABLE(); __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); @@ -171,13 +171,13 @@ static uint32_t GetSector(uint32_t address) } #endif if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize - sector += tmp >>14; + sector += tmp >> 14; } #if defined(ADDR_FLASH_SECTOR_5) else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size sector += FLASH_SECTOR_4; } else { - sector += 4 + (tmp >>17); + sector += 4 + (tmp >> 17); } #else // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one. @@ -197,16 +197,16 @@ static uint32_t GetSectorSize(uint32_t Sector) { uint32_t sectorsize = 0x00; #if defined(FLASH_SECTOR_16) - if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ - (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\ - (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { - sectorsize = 16 * 1024; - } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { + if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \ + (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \ + (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { + sectorsize = 16 * 1024; + } else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { #else -if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ - (Sector == FLASH_SECTOR_3)) { - sectorsize = 16 * 1024; - } else if(Sector == FLASH_SECTOR_4) { + if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \ + (Sector == FLASH_SECTOR_3)) { + sectorsize = 16 * 1024; + } else if (Sector == FLASH_SECTOR_4) { #endif sectorsize = 64 * 1024; } else { diff --git a/targets/TARGET_STM/TARGET_STM32F2/gpio_irq_device.h b/targets/TARGET_STM/TARGET_STM32F2/gpio_irq_device.h index 7b7af71e74..24fa8defb6 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/gpio_irq_device.h +++ b/targets/TARGET_STM/TARGET_STM32F2/gpio_irq_device.h @@ -39,27 +39,27 @@ extern "C" { // until then let's define locally the required functions __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->RTSR, ExtiLine); + SET_BIT(EXTI->RTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->RTSR, ExtiLine); + CLEAR_BIT(EXTI->RTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->FTSR, ExtiLine); + SET_BIT(EXTI->FTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->FTSR, ExtiLine); + CLEAR_BIT(EXTI->FTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->IMR, ExtiLine); + SET_BIT(EXTI->IMR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->IMR, ExtiLine); + CLEAR_BIT(EXTI->IMR, ExtiLine); } // Above lines shall be later defined in LL diff --git a/targets/TARGET_STM/TARGET_STM32F2/pin_device.h b/targets/TARGET_STM/TARGET_STM32F2/pin_device.h index 38aca54c3c..6b75ff657a 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F2/pin_device.h @@ -71,35 +71,35 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); } __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); } __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); } __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); } __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); } __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); } __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); } // Above lines shall be defined in LL when available @@ -126,14 +126,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32F2/pwmout_device.c index a1e131e998..49bae343a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index 93fba8f95e..d40cb72b0a 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { @@ -132,7 +132,7 @@ static void uart8_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -271,7 +271,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -291,7 +291,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -313,7 +313,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -321,9 +321,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -396,7 +396,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -410,28 +410,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -441,14 +441,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -469,18 +469,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -490,8 +490,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -503,10 +503,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -519,20 +519,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { @@ -554,49 +556,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -604,7 +606,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -618,11 +620,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -632,17 +634,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -659,20 +661,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear error flags - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -702,9 +704,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -734,7 +736,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32F2/spi_api.c b/targets/TARGET_STM/TARGET_STM32F2/spi_api.c index 39ffb1d152..505a930789 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F2/spi_api.c @@ -39,20 +39,21 @@ #include "mbed_error.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: #if defined SPI4_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h index 001787b4c0..85ca6c01bf 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h @@ -54,14 +54,14 @@ typedef enum { PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT0 = PA_7 | ALT0, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, + PA_11_ALT0 = PA_11 | ALT0, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, + PA_12_ALT0 = PA_12 | ALT0, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, @@ -81,10 +81,10 @@ typedef enum { PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -169,17 +169,17 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_4, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c index 56335d4c11..1dd610db02 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c @@ -67,7 +67,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -130,7 +130,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h index 5668db662c..c009c62bea 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h @@ -53,33 +53,33 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, + PA_11_ALT0 = PA_11 | ALT0, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, + PA_12_ALT0 = PA_12 | ALT0, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT0 = PB_1 | ALT0, PB_3 = 0x13, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PF_0 = 0x50, PF_1 = 0x51, @@ -148,11 +148,11 @@ typedef enum { SPI_CS = PA_11, PWM_OUT = PA_8, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c index 0fa2188388..bae8353633 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c @@ -67,7 +67,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -130,7 +130,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h index 1e3cec558b..b293c35340 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h @@ -51,88 +51,88 @@ typedef enum { PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, - PA_11_ALT1 = PA_11|ALT1, + PA_11_ALT0 = PA_11 | ALT0, + PA_11_ALT1 = PA_11 | ALT1, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, - PA_12_ALT1 = PA_12|ALT1, + PA_12_ALT0 = PA_12 | ALT0, + PA_12_ALT1 = PA_12 | ALT1, PA_13 = 0x0D, - PA_13_ALT0 = PA_13|ALT0, + PA_13_ALT0 = PA_13 | ALT0, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, - PB_6_ALT1 = PB_6|ALT1, + PB_6_ALT0 = PB_6 | ALT0, + PB_6_ALT1 = PB_6 | ALT1, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, - PB_7_ALT1 = PB_7|ALT1, + PB_7_ALT0 = PB_7 | ALT0, + PB_7_ALT1 = PB_7 | ALT1, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT0 = PC_0 | ALT0, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT0 = PC_1 | ALT0, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, + PC_2_ALT0 = PC_2 | ALT0, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, + PC_3_ALT0 = PC_3 | ALT0, PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -149,15 +149,15 @@ typedef enum { PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, - PD_10_ALT0 = PD_10|ALT0, + PD_10_ALT0 = PD_10 | ALT0, PD_11 = 0x3B, - PD_11_ALT0 = PD_11|ALT0, + PD_11_ALT0 = PD_11 | ALT0, PD_12 = 0x3C, - PD_12_ALT0 = PD_12|ALT0, + PD_12_ALT0 = PD_12 | ALT0, PD_13 = 0x3D, - PD_13_ALT0 = PD_13|ALT0, + PD_13_ALT0 = PD_13 | ALT0, PD_14 = 0x3E, - PD_14_ALT0 = PD_14|ALT0, + PD_14_ALT0 = PD_14 | ALT0, PD_15 = 0x3F, PE_0 = 0x40, @@ -169,7 +169,7 @@ typedef enum { PE_6 = 0x46, PE_7 = 0x47, PE_8 = 0x48, - PE_8_ALT0 = PE_8|ALT0, + PE_8_ALT0 = PE_8 | ALT0, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, @@ -181,7 +181,7 @@ typedef enum { PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, - PF_2_ALT0 = PF_2|ALT0, + PF_2_ALT0 = PF_2 | ALT0, PF_3 = 0x53, PF_4 = 0x54, PF_5 = 0x55, @@ -271,17 +271,17 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_4, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c index 5f1f5a3f07..0234b019ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c @@ -66,7 +66,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -129,7 +129,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h index 5040fb39e4..465cfa8176 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h @@ -51,89 +51,89 @@ typedef enum { PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, - PA_11_ALT1 = PA_11|ALT1, + PA_11_ALT0 = PA_11 | ALT0, + PA_11_ALT1 = PA_11 | ALT1, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, - PA_12_ALT1 = PA_12|ALT1, + PA_12_ALT0 = PA_12 | ALT0, + PA_12_ALT1 = PA_12 | ALT1, PA_13 = 0x0D, - PA_13_ALT0 = PA_13|ALT0, + PA_13_ALT0 = PA_13 | ALT0, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, - PB_6_ALT1 = PB_6|ALT1, + PB_6_ALT0 = PB_6 | ALT0, + PB_6_ALT1 = PB_6 | ALT1, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, - PB_7_ALT1 = PB_7|ALT1, + PB_7_ALT0 = PB_7 | ALT0, + PB_7_ALT1 = PB_7 | ALT1, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, - PB_11_ALT0 = PB_11|ALT0, + PB_11_ALT0 = PB_11 | ALT0, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT0 = PC_0 | ALT0, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT0 = PC_1 | ALT0, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, + PC_2_ALT0 = PC_2 | ALT0, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, + PC_3_ALT0 = PC_3 | ALT0, PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -213,17 +213,17 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_4, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c index b44c115f62..901da55421 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c @@ -62,7 +62,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h index 02772cf554..cdf4fcbbcd 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h @@ -59,7 +59,7 @@ typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE + SPI_4 = (int)SPI4_BASE } SPIName; @@ -78,7 +78,7 @@ typedef enum { PWM_15 = (int)TIM15_BASE, PWM_16 = (int)TIM16_BASE, PWM_17 = (int)TIM17_BASE, - PWM_20 = (int)TIM20_BASE + PWM_20 = (int)TIM20_BASE } PWMName; typedef enum { diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h index 92442d4a54..f4ec22d0ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h @@ -50,87 +50,87 @@ typedef enum { PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, - PA_11_ALT1 = PA_11|ALT1, + PA_11_ALT0 = PA_11 | ALT0, + PA_11_ALT1 = PA_11 | ALT1, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, - PA_12_ALT1 = PA_12|ALT1, + PA_12_ALT0 = PA_12 | ALT0, + PA_12_ALT1 = PA_12 | ALT1, PA_13 = 0x0D, - PA_13_ALT0 = PA_13|ALT0, + PA_13_ALT0 = PA_13 | ALT0, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, - PB_6_ALT1 = PB_6|ALT1, + PB_6_ALT0 = PB_6 | ALT0, + PB_6_ALT1 = PB_6 | ALT1, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, - PB_7_ALT1 = PB_7|ALT1, + PB_7_ALT0 = PB_7 | ALT0, + PB_7_ALT1 = PB_7 | ALT1, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, - PB_11_ALT0 = PB_11|ALT0, + PB_11_ALT0 = PB_11 | ALT0, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT0 = PC_0 | ALT0, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT0 = PC_1 | ALT0, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, + PC_2_ALT0 = PC_2 | ALT0, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, + PC_3_ALT0 = PC_3 | ALT0, PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -149,32 +149,32 @@ typedef enum { PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, - PD_10_ALT0 = PD_10|ALT0, + PD_10_ALT0 = PD_10 | ALT0, PD_11 = 0x3B, - PD_11_ALT0 = PD_11|ALT0, + PD_11_ALT0 = PD_11 | ALT0, PD_12 = 0x3C, - PD_12_ALT0 = PD_12|ALT0, + PD_12_ALT0 = PD_12 | ALT0, PD_13 = 0x3D, - PD_13_ALT0 = PD_13|ALT0, + PD_13_ALT0 = PD_13 | ALT0, PD_14 = 0x3E, - PD_14_ALT0 = PD_14|ALT0, + PD_14_ALT0 = PD_14 | ALT0, PD_15 = 0x3F, PE_0 = 0x40, PE_1 = 0x41, - PE_1_ALT0 = PE_1|ALT0, + PE_1_ALT0 = PE_1 | ALT0, PE_2 = 0x42, - PE_2_ALT0 = PE_2|ALT0, + PE_2_ALT0 = PE_2 | ALT0, PE_3 = 0x43, - PE_3_ALT0 = PE_3|ALT0, + PE_3_ALT0 = PE_3 | ALT0, PE_4 = 0x44, - PE_4_ALT0 = PE_4|ALT0, + PE_4_ALT0 = PE_4 | ALT0, PE_5 = 0x45, - PE_5_ALT0 = PE_5|ALT0, + PE_5_ALT0 = PE_5 | ALT0, PE_6 = 0x46, PE_7 = 0x47, PE_8 = 0x48, - PE_8_ALT0 = PE_8|ALT0, + PE_8_ALT0 = PE_8 | ALT0, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, @@ -186,7 +186,7 @@ typedef enum { PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, - PF_2_ALT0 = PF_2|ALT0, + PF_2_ALT0 = PF_2 | ALT0, PF_3 = 0x53, PF_4 = 0x54, PF_5 = 0x55, @@ -291,17 +291,17 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c index b44c115f62..901da55421 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c @@ -62,7 +62,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h index b197786615..3f8e9da6e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h @@ -53,42 +53,42 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, - PA_11_ALT1 = PA_11|ALT1, + PA_11_ALT0 = PA_11 | ALT0, + PA_11_ALT1 = PA_11 | ALT1, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, - PA_12_ALT1 = PA_12|ALT1, + PA_12_ALT0 = PA_12 | ALT0, + PA_12_ALT1 = PA_12 | ALT1, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, - PB_7_ALT1 = PB_7|ALT1, + PB_7_ALT0 = PB_7 | ALT0, + PB_7_ALT1 = PB_7 | ALT1, PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, @@ -96,10 +96,10 @@ typedef enum { PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_13 = 0x2D, PC_14 = 0x2E, @@ -174,13 +174,13 @@ typedef enum { SPI_CS = PA_4, PWM_OUT = PB_6, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c index 0fa2188388..bae8353633 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c @@ -67,7 +67,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -130,7 +130,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h index 05cfe5689c..d97c086d2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h @@ -53,42 +53,42 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, - PA_11_ALT0 = PA_11|ALT0, - PA_11_ALT1 = PA_11|ALT1, + PA_11_ALT0 = PA_11 | ALT0, + PA_11_ALT1 = PA_11 | ALT1, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, - PA_12_ALT1 = PA_12|ALT1, + PA_12_ALT0 = PA_12 | ALT0, + PA_12_ALT1 = PA_12 | ALT1, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, - PB_7_ALT1 = PB_7|ALT1, + PB_7_ALT0 = PB_7 | ALT0, + PB_7_ALT1 = PB_7 | ALT1, PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, @@ -96,19 +96,19 @@ typedef enum { PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT0 = PB_14 | ALT0, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT0 = PC_0 | ALT0, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT0 = PC_1 | ALT0, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, + PC_2_ALT0 = PC_2 | ALT0, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, + PC_3_ALT0 = PC_3 | ALT0, PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, @@ -191,13 +191,13 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_4, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PF_0, RCC_OSC_OUT = PF_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c index 0fa2188388..bae8353633 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c @@ -67,7 +67,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ @@ -130,7 +130,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c b/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c index dd447d90bf..fe82886354 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c @@ -170,8 +170,7 @@ uint16_t adc_read(analogin_t *obj) if ((ADCName)obj->handle.Instance == ADC_1) { sConfig.Channel = ADC_CHANNEL_VOPAMP1; sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5; - } - else { + } else { sConfig.Channel = ADC_CHANNEL_15; } break; @@ -179,8 +178,7 @@ uint16_t adc_read(analogin_t *obj) if ((ADCName)obj->handle.Instance == ADC_1) { sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5; - } - else { + } else { sConfig.Channel = ADC_CHANNEL_16; } break; diff --git a/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c index 97578ca061..cc263b2e07 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c @@ -39,7 +39,8 @@ static int pa4_used = 0; static int pa5_used = 0; -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object @@ -85,7 +86,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = (DAC_TypeDef *)(obj->dac); obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -115,10 +116,15 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ // Reset DAC and disable clock - if (obj->pin == PA_4) pa4_used = 0; - if (obj->pin == PA_5) pa5_used = 0; + if (obj->pin == PA_4) { + pa4_used = 0; + } + if (obj->pin == PA_5) { + pa5_used = 0; + } if ((pa4_used == 0) && (pa5_used == 0)) { __HAL_RCC_DAC1_FORCE_RESET(); diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c index 9a2d7c4c8e..169128d994 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, } } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) { address = address + MIN_PROG_SIZE; data = data + MIN_PROG_SIZE; } else { diff --git a/targets/TARGET_STM/TARGET_STM32F3/pin_device.h b/targets/TARGET_STM/TARGET_STM32F3/pin_device.h index 5d1325784e..7668871373 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F3/pin_device.h @@ -57,14 +57,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c index 939331a3fd..d112a29c4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c index 12fa338255..30f67023c3 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c @@ -33,9 +33,9 @@ #include "serial_api_hal.h" #if defined (TARGET_STM32F302x8) || defined (TARGET_STM32F303x8) || defined (TARGET_STM32F334x8) - #define UART_NUM (3) +#define UART_NUM (3) #else - #define UART_NUM (5) // max value +#define UART_NUM (5) // max value #endif uint32_t serial_irq_ids[UART_NUM] = {0}; @@ -55,12 +55,12 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); - } + irq_handler(serial_irq_ids[id], TxIrq); + } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) { @@ -115,7 +115,7 @@ static void uart5_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -246,7 +246,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -266,7 +266,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -288,7 +288,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -296,9 +296,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -356,7 +356,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -370,28 +370,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -401,14 +401,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -429,18 +429,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -450,8 +450,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -463,10 +463,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -479,20 +479,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); } @@ -517,49 +519,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -567,7 +569,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -581,11 +583,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -595,17 +597,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -622,20 +624,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -665,9 +667,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -697,7 +699,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32F3/spi_api.c b/targets/TARGET_STM/TARGET_STM32F3/spi_api.c index 661c6a8b29..b207992006 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/spi_api.c @@ -39,20 +39,21 @@ #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { #if defined SPI1_BASE case SPI_1: diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h index e9ee25c4e8..42fa8e5fa1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h @@ -169,7 +169,7 @@ typedef enum { SWCLK = PA_14, I2C1_SCL = PB_8, - I2C1_SDA = PB_9, + I2C1_SDA = PB_9, I2C3_SCL = PA_8, I2C3_SDA = PC_9, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c index ea532df442..82e623e28e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c @@ -35,7 +35,7 @@ static void press_power_button(int time_ms) void onboard_modem_init() { - //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed + //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed } void onboard_modem_deinit() @@ -59,7 +59,7 @@ void onboard_modem_power_down() * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 * seconds only */ - wait_ms(10*1000); + wait_ms(10 * 1000); } #endif //MODEM_ON_BOARD #endif //MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h index ca73457e6e..ef62f32322 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h @@ -162,7 +162,7 @@ typedef enum { // I2C1 and I2C3 are available on Arduino pins I2C1_SCL = D15, - I2C1_SDA = D14, + I2C1_SDA = D14, I2C3_SCL = D7, I2C3_SDA = A5, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c index ea532df442..82e623e28e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c @@ -35,7 +35,7 @@ static void press_power_button(int time_ms) void onboard_modem_init() { - //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed + //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed } void onboard_modem_deinit() @@ -59,7 +59,7 @@ void onboard_modem_power_down() * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 * seconds only */ - wait_ms(10*1000); + wait_ms(10 * 1000); } #endif //MODEM_ON_BOARD #endif //MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h index 45617a28d1..fb4e70c35b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h @@ -49,15 +49,15 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT0 = PA_7 | ALT0, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -66,25 +66,25 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT0 = PB_1 | ALT0, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_12 = 0x1C, PB_13 = 0x1D, @@ -184,20 +184,20 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c index f42278ce2c..9e6f62436f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c @@ -63,7 +63,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -120,7 +120,7 @@ void SetSysClock(void) { /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { - while(1) { + while (1) { // [TODO] Put something here to tell the user that a problem occured... } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h index 72c3b599ef..454ad2d685 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h @@ -49,15 +49,15 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT0 = PA_7 | ALT0, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -66,25 +66,25 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT0 = PB_1 | ALT0, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_12 = 0x1C, PB_13 = 0x1D, @@ -175,20 +175,20 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c index e0634da8b1..87344b0f20 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c @@ -65,7 +65,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c index 84ce6c598c..35d1ceee3b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c @@ -134,9 +134,9 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT0, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N @@ -194,7 +194,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {NC, NC, 0} }; - + MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h index 6e4266e516..1d57df7c29 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h @@ -38,23 +38,23 @@ extern "C" { #endif typedef enum { - ALT0 = 0x100, - ALT1 = 0x200 + ALT0 = 0x100, + ALT1 = 0x200 } ALTx; typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT0 = PA_7 | ALT0, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -63,25 +63,25 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT0 = PB_1 | ALT0, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_12 = 0x1C, PB_13 = 0x1D, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c index c39f4bcb2d..dfb96ca384 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c @@ -65,7 +65,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c index b078418091..9f8fce2306 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PeripheralPins.c @@ -76,8 +76,8 @@ const PinMap PinMap_DAC[] = { const PinMap PinMap_I2C_SDA[] = { {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_0 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_5 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, @@ -90,8 +90,8 @@ const PinMap PinMap_I2C_SCL[] = { {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PF_1 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PH_4 , I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {NC, NC, 0} }; @@ -136,12 +136,12 @@ const PinMap PinMap_PWM[] = { {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N - + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - + {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h index 41d2701c46..b301d6e317 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/PinNames.h @@ -239,9 +239,9 @@ typedef enum { LED2 = PD_8, LED3 = PD_9, LED4 = PD_10, - USBTX = STDIO_UART_TX, /* USART6 */ + USBTX = STDIO_UART_TX, /* USART6 */ USBRX = STDIO_UART_RX, - I2C_SCL = PB_8, /* I2C1 */ + I2C_SCL = PB_8, /* I2C1 */ I2C_SDA = PB_9, SPI_MOSI = PC_3, SPI_MISO = PC_2, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c index 9c33be421e..abb30fcd92 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -120,7 +120,7 @@ void SetSysClock(void) { /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { - while(1) { + while (1) { // [TODO] Put something here to tell the user that a problem occured... } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h index 3658b9caa5..4a96e2e438 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,70 +76,70 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -161,7 +161,7 @@ typedef enum { PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, - + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, @@ -178,7 +178,7 @@ typedef enum { PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, - + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, @@ -279,7 +279,7 @@ typedef enum { SERIAL_RX = STDIO_UART_RX, USBTX = STDIO_UART_TX, /* USART2 */ USBRX = STDIO_UART_RX, - I2C_SCL = PB_8, /* I2C1 */ + I2C_SCL = PB_8, /* I2C1 */ I2C_SDA = PB_9, SPI_MOSI = PA_7, SPI_MISO = PA_6, @@ -287,7 +287,7 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -311,7 +311,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -334,13 +334,13 @@ typedef enum { ETH_TX_CLK = PC_3, ETH_TX_EN = PB_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c index 18e823a491..dcabc3b843 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c @@ -65,7 +65,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -124,7 +124,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h index d0f283f022..16467b7c87 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/objects.h @@ -49,7 +49,7 @@ struct gpio_irq_s { struct port_s { PortName port; uint32_t mask; - PinDirection direction; + PinDirection direction; __IO uint32_t *reg_in; __IO uint32_t *reg_out; }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h index bcb5279375..00d7f11722 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/PinNames.h @@ -67,19 +67,19 @@ typedef enum { PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, - PB_10_ALT0 = PB_10|ALT0, + PB_10_ALT0 = PB_10 | ALT0, PB_11 = 0x1B, - PB_11_ALT0 = PB_11|ALT0, + PB_11_ALT0 = PB_11 | ALT0, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, @@ -169,13 +169,13 @@ typedef enum { SPI_CS = PB_12, PWM_OUT = PA_7, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c index a77d79be6b..9184ae4782 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c index 6bf66904cf..7d2eb4d6b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/PeripheralPins.c @@ -200,7 +200,7 @@ const PinMap PinMap_SPI_SCLK[] = { }; const PinMap PinMap_SPI_SSEL[] = { - // {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c index bffa88a663..017f8b5caa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c @@ -67,7 +67,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -124,7 +124,7 @@ void SetSysClock(void) { /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { - while(1) { + while (1) { // [TODO] Put something here to tell the user that a problem occured... } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h index 4d233b65db..5d1a4080f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/PinNames.h @@ -48,17 +48,17 @@ typedef enum { typedef enum { PA_0 = 0x00, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, + PA_1_ALT0 = PA_1 | ALT0, PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -67,36 +67,36 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_12 = 0x1C, - PB_12_ALT0 = PB_12|ALT0, + PB_12_ALT0 = PB_12 | ALT0, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, PB_15 = 0x1F, @@ -184,20 +184,20 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c index 0e303c6dec..5a81b4a673 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c @@ -57,7 +57,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -110,7 +110,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h index a078bc7b95..480bfa9152 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/PinNames.h @@ -167,7 +167,7 @@ typedef enum { LED3 = PH_1, LED4 = PC_4, LED_RED = LED1, - + // Standardized button names SW1 = PC_14, SW2 = PH_0, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c index 7be2a9fd72..c15d024fce 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h index 3f31b59516..09351253a8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/PinNames.h @@ -204,7 +204,7 @@ typedef enum { LED_RED = LED1, LED_BLUE = LED2, USER_BUTTON = PC_13, - + // Standardized button names BUTTON1 = USER_BUTTON, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c index 29e03519fa..362dba42c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) if (ret_HSIclk_status == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h index ad379e95f1..9bdac54021 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h @@ -49,21 +49,21 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -72,45 +72,45 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, - PB_10_ALT0 = PB_10|ALT0, + PB_10_ALT0 = PB_10 | ALT0, PB_11 = 0x1B, - PB_11_ALT0 = PB_11|ALT0, + PB_11_ALT0 = PB_11 | ALT0, PB_12 = 0x1C, - PB_12_ALT0 = PB_12|ALT0, + PB_12_ALT0 = PB_12 | ALT0, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -119,13 +119,13 @@ typedef enum { PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -153,26 +153,26 @@ typedef enum { PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, - PE_2_ALT0 = PE_2|ALT0, + PE_2_ALT0 = PE_2 | ALT0, PE_3 = 0x43, PE_4 = 0x44, - PE_4_ALT0 = PE_4|ALT0, + PE_4_ALT0 = PE_4 | ALT0, PE_5 = 0x45, - PE_5_ALT0 = PE_5|ALT0, + PE_5_ALT0 = PE_5 | ALT0, PE_6 = 0x46, - PE_6_ALT0 = PE_6|ALT0, + PE_6_ALT0 = PE_6 | ALT0, PE_7 = 0x47, PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_11_ALT0 = PE_11|ALT0, + PE_11_ALT0 = PE_11 | ALT0, PE_12 = 0x4C, - PE_12_ALT0 = PE_12|ALT0, + PE_12_ALT0 = PE_12 | ALT0, PE_13 = 0x4D, - PE_13_ALT0 = PE_13|ALT0, + PE_13_ALT0 = PE_13 | ALT0, PE_14 = 0x4E, - PE_14_ALT0 = PE_14|ALT0, + PE_14_ALT0 = PE_14 | ALT0, PE_15 = 0x4F, PF_0 = 0x50, @@ -274,20 +274,20 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c index f2843569d9..319fbc885b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -125,7 +125,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c index 29e03519fa..362dba42c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_USI_WM_BN_BM_22/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) if (ret_HSIclk_status == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h index a271aefdb5..22ad0b3f55 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralNames.h @@ -11,7 +11,7 @@ * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and - * limitations under the License. + * limitations under the License. */ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h index 4f1dc3c7aa..c207cc1b8c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PinNames.h @@ -49,64 +49,64 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, - PA_10_ALT0 = PA_10|ALT0, + PA_10_ALT0 = PA_10 | ALT0, PA_11 = 0x0B, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, + PA_12_ALT0 = PA_12 | ALT0, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, - PB_10_ALT0 = PB_10|ALT0, + PB_10_ALT0 = PB_10 | ALT0, PB_11 = 0x1B, PB_12 = 0x1C, - PB_12_ALT0 = PB_12|ALT0, + PB_12_ALT0 = PB_12 | ALT0, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -115,16 +115,16 @@ typedef enum { PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -150,26 +150,26 @@ typedef enum { PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, - PE_2_ALT0 = PE_2|ALT0, + PE_2_ALT0 = PE_2 | ALT0, PE_3 = 0x43, PE_4 = 0x44, - PE_4_ALT0 = PE_4|ALT0, + PE_4_ALT0 = PE_4 | ALT0, PE_5 = 0x45, - PE_5_ALT0 = PE_5|ALT0, + PE_5_ALT0 = PE_5 | ALT0, PE_6 = 0x46, - PE_6_ALT0 = PE_6|ALT0, + PE_6_ALT0 = PE_6 | ALT0, PE_7 = 0x47, PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_11_ALT0 = PE_11|ALT0, + PE_11_ALT0 = PE_11 | ALT0, PE_12 = 0x4C, - PE_12_ALT0 = PE_12|ALT0, + PE_12_ALT0 = PE_12 | ALT0, PE_13 = 0x4D, - PE_13_ALT0 = PE_13|ALT0, + PE_13_ALT0 = PE_13 | ALT0, PE_14 = 0x4E, - PE_14_ALT0 = PE_14|ALT0, + PE_14_ALT0 = PE_14 | ALT0, PE_15 = 0x4F, PF_0 = 0x50, @@ -270,20 +270,20 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c index 25448b7b7e..63a9146a9d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c @@ -65,7 +65,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h index a271aefdb5..22ad0b3f55 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralNames.h @@ -11,7 +11,7 @@ * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and - * limitations under the License. + * limitations under the License. */ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h index ffba71ed0b..1fba180f55 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h @@ -49,66 +49,66 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, - PA_10_ALT0 = PA_10|ALT0, + PA_10_ALT0 = PA_10 | ALT0, PA_11 = 0x0B, PA_12 = 0x0C, - PA_12_ALT0 = PA_12|ALT0, + PA_12_ALT0 = PA_12 | ALT0, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PA_4|ALT0, + PB_4_ALT0 = PA_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, - PB_10_ALT0 = PB_10|ALT0, + PB_10_ALT0 = PB_10 | ALT0, PB_11 = 0x1B, PB_12 = 0x1C, - PB_12_ALT0 = PB_12|ALT0, + PB_12_ALT0 = PB_12 | ALT0, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, PC_1 = 0x21, @@ -117,16 +117,16 @@ typedef enum { PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -152,26 +152,26 @@ typedef enum { PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, - PE_2_ALT0 = PE_2|ALT0, + PE_2_ALT0 = PE_2 | ALT0, PE_3 = 0x43, PE_4 = 0x44, - PE_4_ALT0 = PE_4|ALT0, + PE_4_ALT0 = PE_4 | ALT0, PE_5 = 0x45, - PE_5_ALT0 = PE_5|ALT0, + PE_5_ALT0 = PE_5 | ALT0, PE_6 = 0x46, - PE_6_ALT0 = PE_6|ALT0, + PE_6_ALT0 = PE_6 | ALT0, PE_7 = 0x47, PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, - PE_11_ALT0 = PE_11|ALT0, + PE_11_ALT0 = PE_11 | ALT0, PE_12 = 0x4C, - PE_12_ALT0 = PE_12|ALT0, + PE_12_ALT0 = PE_12 | ALT0, PE_13 = 0x4D, - PE_13_ALT0 = PE_13|ALT0, + PE_13_ALT0 = PE_13 | ALT0, PE_14 = 0x4E, - PE_14_ALT0 = PE_14|ALT0, + PE_14_ALT0 = PE_14 | ALT0, PE_15 = 0x4F, PF_0 = 0x50, @@ -273,20 +273,20 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c index 98e05a74d5..a209b693ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c @@ -65,7 +65,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h index 24e19c98f4..fdc35049d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/PinNames.h @@ -47,28 +47,28 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, - PA_5_ALT1 = PA_5|ALT1, + PA_5_ALT0 = PA_5 | ALT0, + PA_5_ALT1 = PA_5 | ALT1, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -77,66 +77,66 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -248,7 +248,7 @@ typedef enum { SPI_SCK = PA_5, SPI_CS = PB_6, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -272,7 +272,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -299,13 +299,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c index 3af0483faf..a6f4d7180a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c @@ -107,7 +107,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h index 1fb02a7315..ad1011aebe 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h @@ -47,28 +47,28 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, - PA_5_ALT1 = PA_5|ALT1, + PA_5_ALT0 = PA_5 | ALT0, + PA_5_ALT1 = PA_5 | ALT1, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -77,66 +77,66 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -275,7 +275,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -299,7 +299,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -326,13 +326,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c index 3af0483faf..a6f4d7180a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c @@ -107,7 +107,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c index 798ccd4100..55fff9ae38 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_clock.c @@ -61,7 +61,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -128,8 +128,8 @@ void SetSysClock(void) RCC_OscInitStruct.PLL.PLLQ = 7; HAL_RCC_OscConfig(&RCC_OscInitStruct); - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 - |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 + | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; @@ -170,8 +170,8 @@ void SetSysClock(void) HAL_RCC_OscConfig(&RCC_OscInitStruct); - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 - |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 + | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c index c299903bf8..9a197eed15 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c @@ -140,7 +140,7 @@ const PinMap PinMap_CAN_RD[] = { const PinMap PinMap_CAN_TD[] = { {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, - {PB_6 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h index 26e1426dfe..6de7fdb455 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h @@ -108,7 +108,7 @@ typedef enum { P_C16 = PF_7, // GPIO-7 P_C17 = PF_1, // I2C-SCL P_C18 = PF_0, // I2C-SDA - // D + // D P_D1 = PB_12, // RMII-TXD0 P_D2 = PB_13, // RMII-TXD1 P_D3 = PB_11, // RMII-TXEN @@ -141,7 +141,7 @@ typedef enum { // Standardized button names BUTTON1 = SW1, BUTTON2 = SW2, - + I2C_SDA = PF_0, I2C_SCL = PF_1, SPI0_MOSI = PE_14, @@ -149,7 +149,7 @@ typedef enum { SPI0_SCK = PE_12, SPI0_CS = PE_11, SPI1_CS = PE_9, - + SPI_MOSI = SPI0_MOSI, SPI_MISO = SPI0_MISO, SPI_SCK = SPI0_SCK, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h index 50d0386948..c61f4dd431 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h @@ -27,7 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ - + #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H @@ -162,16 +162,16 @@ typedef enum { // Standardized button names BUTTON1 = SW1, BUTTON2 = SW2, - + I2C_SDA = PF_0, I2C_SCL = PF_1, - + SPI0_MOSI = PE_14, SPI0_MISO = PE_13, SPI0_SCK = PE_12, SPI0_CS = PE_11, SPI1_CS = PE_9, - + SPI_MOSI = SPI0_MOSI, SPI_MISO = SPI0_MISO, SPI_SCK = SPI0_SCK, @@ -242,7 +242,7 @@ typedef enum { PWM2 = LED_GREEN, PWM1 = LED_BLUE, PWM0 = LED_RED, - + } PinName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h index f9c8638263..b876c11f1e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h @@ -108,7 +108,7 @@ typedef enum { P_C16 = PF_7, // GPIO-7 P_C17 = PF_1, // I2C-SCL P_C18 = PF_0, // I2C-SDA - // D + // D P_D1 = PB_12, // RMII-TXD0 P_D2 = PB_13, // RMII-TXD1 P_D3 = PB_11, // RMII-TXEN @@ -159,7 +159,7 @@ typedef enum { LED_BLUE = LED3, SW0 = PF_2, // Switch-0 SW1 = PB_6, // Green / Switch-1 - + I2C_SCL = D15, I2C_SDA = D14, SPI0_MOSI = D11, @@ -167,7 +167,7 @@ typedef enum { SPI0_SCK = D13, SPI0_CS = D10, SPI1_CS = D9, - + SPI_MOSI = SPI0_MOSI, SPI_MISO = SPI0_MISO, SPI_SCK = SPI0_SCK, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c index 718dc230d9..bf5cd658e6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/hal_overrides.c @@ -27,7 +27,7 @@ void HAL_MspInit(void) { __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); - + GPIO_InitTypeDef GPIO_InitDef; GPIO_InitDef.Pin = GPIO_PIN_6 | GPIO_PIN_8; @@ -35,10 +35,10 @@ void HAL_MspInit(void) GPIO_InitDef.Pull = GPIO_NOPULL; GPIO_InitDef.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOB, &GPIO_InitDef); - + GPIO_InitDef.Pin = GPIO_PIN_0; HAL_GPIO_Init(GPIOE, &GPIO_InitDef); - + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOB, GPIO_PIN_8, GPIO_PIN_SET); HAL_GPIO_WritePin(GPIOE, GPIO_PIN_0, GPIO_PIN_SET); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c index fd95ee825b..f926963737 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c @@ -54,7 +54,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -116,8 +116,8 @@ void SetSysClock(void) RCC_OscInitStruct.PLL.PLLQ = 7; HAL_RCC_OscConfig(&RCC_OscInitStruct); - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 - |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 + | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; @@ -156,8 +156,8 @@ void SetSysClock(void) HAL_PWREx_EnableOverDrive(); - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 - |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 + | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h index cae97e54c3..0b6a7f8103 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h @@ -47,28 +47,28 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, - PA_5_ALT1 = PA_5|ALT1, + PA_5_ALT0 = PA_5 | ALT0, + PA_5_ALT1 = PA_5 | ALT1, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -77,66 +77,66 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -275,7 +275,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -299,7 +299,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -326,13 +326,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c index 7a89610d4d..9a12df06e7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c @@ -62,7 +62,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -122,7 +122,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c index 87fb164e7a..115f568b5f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PeripheralPins.c @@ -110,10 +110,10 @@ MBED_WEAK const PinMap PinMap_DAC[] = { MBED_WEAK const PinMap PinMap_I2C_SDA[] = { // {PB_7, I2C_1 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // (pin used by LED2) - {PB_9, I2C_1 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14 - {PB_11, I2C_2 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_9, I2C_3 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, - {PF_0, I2C_2 , STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14 + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, {NC, NC, 0} }; @@ -161,8 +161,8 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates) - // HW solder bridge update : SB121 off, SB122 on - // SW : config from json files + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (pin used by LED2) // {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15 @@ -273,8 +273,8 @@ MBED_WEAK const PinMap PinMap_UART_CTS[] = { MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // pin used by ethernet when JP6 ON - ARDUINO D11 (default configuration) {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) - // HW solder bridge update : SB121 off, SB122 on - // SW : config from json files + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2 @@ -335,9 +335,9 @@ MBED_WEAK const PinMap PinMap_CAN_RD[] = { {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) - // HW solder bridge update : SB121 off, SB122 on - // SW : config from json files + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; @@ -346,7 +346,7 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = { {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_6 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h index 1c5cb30be0..c98766962a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/PinNames.h @@ -200,11 +200,11 @@ typedef enum { MDMDTR = PC_5, M_POWR = PE_9, -/* - MDMDCD = NC, // Data Carrier Detect - MDMDSR = NC, // Data Set Ready - MDMRI = NC, // Ring Indicator -*/ + /* + MDMDCD = NC, // Data Carrier Detect + MDMDSR = NC, // Data Set Ready + MDMRI = NC, // Ring Indicator + */ // Internal control signals RGB_POWR = PE_8, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/onboard_modem_api.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/onboard_modem_api.c index e4fd3fd144..23f7fb1985 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/onboard_modem_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/onboard_modem_api.c @@ -36,7 +36,7 @@ static void press_power_button(int time_ms) void onboard_modem_init() { gpio_t gpio; - // start with modem disabled + // start with modem disabled gpio_init_out_ex(&gpio, RESET_MODULE, 0); gpio_init_in_ex(&gpio, MDMSTAT, PullUp); gpio_init_out_ex(&gpio, MDMDTR, 0); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/system_clock.c index 7d7b8530bf..6dc371b794 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_WIO_3G/system_clock.c @@ -62,7 +62,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -122,7 +122,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c index 814227ea80..7eaa54bba7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PeripheralPins.c @@ -167,7 +167,7 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N @@ -175,7 +175,7 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 - + {NC, NC, 0} }; @@ -216,22 +216,22 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - // {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - // {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs +// {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - // {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 +// {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { - // {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - // {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - // {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // unsolder JP69 to use it - // {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // unsolder JP14 to use it - // {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 +// {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // unsolder JP69 to use it +// {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // unsolder JP14 to use it +// {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 {NC, NC, 0} }; //*** SPI *** @@ -300,19 +300,19 @@ MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { //*** CAN *** MBED_WEAK const PinMap PinMap_CAN_RD[] = { - // {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP73 to use it - // {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP36 to use it - // {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs - // {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, +// {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP73 to use it +// {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP36 to use it +// {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs +// {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_CAN_TD[] = { - // {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP74 to use it - // {PB_6 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP43 to use it - // {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs - // {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, +// {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // unsolder JP74 to use it +// {PB_6 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // unsolder JP43 to use it +// {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // connected to MEMs +// {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h index 0435b5d875..45960d47b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/PinNames.h @@ -121,7 +121,7 @@ typedef enum { PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, - + PH_0 = 0x70, PH_1 = 0x71, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c index ed57a5fa5d..9b98070028 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c @@ -66,7 +66,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -123,7 +123,7 @@ void SetSysClock(void) { /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { - while(1) { + while (1) { // [TODO] Put something here to tell the user that a problem occured... } } @@ -196,10 +196,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 1 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 16 MHz with xtal - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz with external clock (MCO) + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 16 MHz with xtal + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz with external clock (MCO) + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h index 0021165eca..dcbf64a0e9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PinNames.h @@ -47,23 +47,23 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -72,69 +72,69 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -207,7 +207,7 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -231,13 +231,13 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c index 8ae982a9e4..e26ff60b45 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c @@ -65,7 +65,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -119,7 +119,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -192,10 +192,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 1 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO) + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO) + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h index cfe07459cb..eb1d885320 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,66 +76,66 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -277,7 +277,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -301,13 +301,13 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c index 2da2adac35..c99a393223 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c @@ -68,7 +68,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -129,7 +129,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -203,10 +203,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 1 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO) + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO) + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h index a19a37f103..5d8187d616 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,64 +76,64 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -323,7 +323,7 @@ typedef enum { SPI_CS = PH_6, PWM_OUT = PA_1, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -349,7 +349,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PH_3, ETH_COL_ALT0 = PA_3, ETH_CRS = PH_2, @@ -381,13 +381,13 @@ typedef enum { ETH_TX_EN = PG_11, ETH_TX_EN_ALT0 = PB_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c index 7d4fe8e44d..ea9be4b2d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c @@ -68,7 +68,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -129,7 +129,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -202,10 +202,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 1 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO) + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO) + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c index da07ad678b..0f4e2c8bf5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c @@ -35,7 +35,8 @@ #include "stm32f4xx_hal.h" #include "PeripheralPins.h" -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object @@ -73,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = DAC; obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ } #endif // DEVICE_ANALOGOUT diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c index 5ba7fb9e49..8f94d39b46 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c @@ -94,7 +94,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; EraseInitStruct.Sector = FirstSector; EraseInitStruct.NbSectors = 1; - if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){ + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { status = -1; } @@ -115,10 +115,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, return -1; } - /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, - you have to make sure that these data are rewritten before they are accessed during code - execution. If this cannot be done safely, it is recommended to flush the caches by setting the - DCRST and ICRST bits in the FLASH_CR register. */ + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ __HAL_FLASH_DATA_CACHE_DISABLE(); __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); @@ -186,13 +186,13 @@ static uint32_t GetSector(uint32_t address) } #endif if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize - sector += tmp >>14; + sector += tmp >> 14; } #if defined(ADDR_FLASH_SECTOR_5) else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size sector += FLASH_SECTOR_4; } else { - sector += 4 + (tmp >>17); + sector += 4 + (tmp >> 17); } #else // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one. @@ -212,16 +212,16 @@ static uint32_t GetSectorSize(uint32_t Sector) { uint32_t sectorsize = 0x00; #if defined(FLASH_SECTOR_16) - if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ - (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\ - (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { - sectorsize = 16 * 1024; - } else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { + if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \ + (Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \ + (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { + sectorsize = 16 * 1024; + } else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { #else -if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\ - (Sector == FLASH_SECTOR_3)) { - sectorsize = 16 * 1024; - } else if(Sector == FLASH_SECTOR_4) { + if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \ + (Sector == FLASH_SECTOR_3)) { + sectorsize = 16 * 1024; + } else if (Sector == FLASH_SECTOR_4) { #endif sectorsize = 64 * 1024; } else { diff --git a/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.h b/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.h index 6f8f1ad4c4..b4e03680c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/gpio_irq_device.h @@ -39,27 +39,27 @@ extern "C" { // until then let's define locally the required functions __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->RTSR, ExtiLine); + SET_BIT(EXTI->RTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->RTSR, ExtiLine); + CLEAR_BIT(EXTI->RTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->FTSR, ExtiLine); + SET_BIT(EXTI->FTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->FTSR, ExtiLine); + CLEAR_BIT(EXTI->FTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->IMR, ExtiLine); + SET_BIT(EXTI->IMR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->IMR, ExtiLine); + CLEAR_BIT(EXTI->IMR, ExtiLine); } // Above lines shall be later defined in LL diff --git a/targets/TARGET_STM/TARGET_STM32F4/pin_device.h b/targets/TARGET_STM/TARGET_STM32F4/pin_device.h index 843580e4ef..b0b62a9530 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/pin_device.h @@ -71,34 +71,34 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); + MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); } __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); } __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); } __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); } __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); } __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); } __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); } // Above lines shall be defined in LL when available @@ -125,14 +125,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c index a1e131e998..49bae343a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index 37c11d090d..d97a223a49 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -33,15 +33,15 @@ #include "serial_api_hal.h" #if defined (TARGET_STM32F401xC) || defined (TARGET_STM32F401xE) || defined (TARGET_STM32F410xB) || defined (TARGET_STM32F411xE) - #define UART_NUM (3) +#define UART_NUM (3) #elif defined (TARGET_STM32F412xG) - #define UART_NUM (4) +#define UART_NUM (4) #elif defined (TARGET_STM32F407xG) || defined (TARGET_STM32F446xE) - #define UART_NUM (6) +#define UART_NUM (6) #elif defined (TARGET_STM32F429xI) || defined (TARGET_STM32F439xI) || defined (TARGET_STM32F437xG) || defined (TARGET_STM32F469xI) - #define UART_NUM (8) +#define UART_NUM (8) #else - #define UART_NUM (10) // max value // TARGET_STM32F413xH +#define UART_NUM (10) // max value // TARGET_STM32F413xH #endif uint32_t serial_irq_ids[UART_NUM] = {0}; @@ -61,7 +61,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { @@ -156,7 +156,7 @@ static void uart10_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -270,7 +270,7 @@ int serial_getc(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + while (!serial_readable(obj)); return (int)(huart->Instance->DR & 0x1FF); } @@ -279,7 +279,7 @@ void serial_putc(serial_t *obj, int c) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + while (!serial_writable(obj)); huart->Instance->DR = (uint32_t)(c & 0x1FF); } @@ -307,7 +307,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -327,7 +327,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -349,7 +349,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -357,9 +357,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -441,7 +441,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -455,28 +455,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -486,14 +486,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -514,18 +514,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -535,8 +535,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -548,10 +548,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -564,20 +564,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { @@ -599,49 +601,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -649,7 +651,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -663,11 +665,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -677,17 +679,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -704,20 +706,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -747,9 +749,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -779,7 +781,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32F4/spi_api.c b/targets/TARGET_STM/TARGET_STM32F4/spi_api.c index af4414c150..4b62c424ff 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/spi_api.c @@ -40,20 +40,21 @@ #include "PeripheralPins.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: #if defined SPI4_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h index 0f773e54b2..8874294d21 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,68 +76,68 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -332,7 +332,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -358,7 +358,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PH_3, ETH_COL_ALT0 = PA_3, ETH_CRS = PH_2, @@ -390,13 +390,13 @@ typedef enum { ETH_TX_EN = PG_11, ETH_TX_EN_ALT0 = PB_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c index 0421d6c58e..6a33c7fb08 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c @@ -63,7 +63,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -123,7 +123,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h index 8f4989055b..74f94f7894 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,66 +76,66 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -275,7 +275,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -299,7 +299,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -326,13 +326,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c index 96a8cb880b..c37256a1e1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -124,7 +124,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h index 8f4989055b..74f94f7894 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h @@ -47,27 +47,27 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -76,66 +76,66 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -275,7 +275,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -299,7 +299,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -326,13 +326,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c index d30b553672..fac353279c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c @@ -63,7 +63,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -123,7 +123,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h index a538657d17..89e4a8596f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h @@ -47,28 +47,28 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, - PA_4_ALT1 = PA_4|ALT1, + PA_4_ALT0 = PA_4 | ALT0, + PA_4_ALT1 = PA_4 | ALT1, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -77,70 +77,70 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, - PA_15_ALT1 = PA_15|ALT1, + PA_15_ALT0 = PA_15 | ALT0, + PA_15_ALT1 = PA_15 | ALT1, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, - PB_3_ALT1 = PB_3|ALT1, + PB_3_ALT0 = PB_3 | ALT0, + PB_3_ALT1 = PB_3 | ALT1, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, PC_11 = 0x2B, PC_12 = 0x2C, @@ -280,7 +280,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -304,7 +304,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PA_3, ETH_CRS = PA_0, ETH_CRS_DV = PA_7, @@ -331,13 +331,13 @@ typedef enum { ETH_TX_EN = PB_11, ETH_TX_EN_ALT0 = PG_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c index b8cee95e8e..f18c625110 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c @@ -64,7 +64,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -124,7 +124,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h index 425b03af82..df3fc26265 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PinNames.h @@ -47,28 +47,28 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, - PA_4_ALT1 = PA_4|ALT1, + PA_4_ALT0 = PA_4 | ALT0, + PA_4_ALT1 = PA_4 | ALT1, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -77,74 +77,74 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, - PA_15_ALT1 = PA_15|ALT1, + PA_15_ALT0 = PA_15 | ALT0, + PA_15_ALT1 = PA_15 | ALT1, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, - PB_3_ALT1 = PB_3|ALT1, + PB_3_ALT0 = PB_3 | ALT0, + PB_3_ALT1 = PB_3 | ALT1, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -339,7 +339,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -365,7 +365,7 @@ typedef enum { USB_OTG_HS_ULPI_STP = PC_0, USB_OTG_HS_VBUS = PB_13, -/**** ETHERNET pins ****/ + /**** ETHERNET pins ****/ ETH_COL = PH_3, ETH_COL_ALT0 = PA_3, ETH_CRS = PH_2, @@ -397,13 +397,13 @@ typedef enum { ETH_TX_EN = PG_11, ETH_TX_EN_ALT0 = PB_11, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c index 381007417f..c665b68673 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c @@ -63,7 +63,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ @@ -123,7 +123,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -180,7 +180,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; RCC_PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7; RCC_PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8; - if(HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { return 0; // FAIL } diff --git a/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c index d817d3d280..2242c6855e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c @@ -35,7 +35,8 @@ #include "stm32f7xx_hal.h" #include "PeripheralPins.h" -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object @@ -73,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = DAC; obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ } diff --git a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h index b3f02642c7..e479902f61 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h @@ -80,7 +80,7 @@ struct serial_s { PinName pin_rts; PinName pin_cts; #endif - }; +}; struct i2c_s { /* The 1st 2 members I2CName i2c diff --git a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c index c94caa3ab6..495a4f97b2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c @@ -49,14 +49,12 @@ int32_t flash_init(flash_t *obj) /* Allow Access to option bytes sector */ HAL_FLASH_OB_Lock(); #if MBED_CONF_TARGET_FLASH_DUAL_BANK - if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK) - { + if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_SINGLE_BANK) { error("The Dual Bank mode option byte (nDBANK) must be enabled (box unchecked)\n"); return -1; } #else // SINGLE BANK - if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK) - { + if ((OBInit.USERConfig & OB_NDBANK_SINGLE_BANK) == OB_NDBANK_DUAL_BANK) { error("The Dual Bank mode option byte (nDBANK) must be disabled (box checked)\n"); return -1; } @@ -111,10 +109,10 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return -1; } - /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, - you have to make sure that these data are rewritten before they are accessed during code - execution. If this cannot be done safely, it is recommended to flush the caches by setting the - DCRST and ICRST bits in the FLASH_CR register. */ + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ __HAL_FLASH_ART_DISABLE(); __HAL_FLASH_ART_RESET(); __HAL_FLASH_ART_ENABLE(); @@ -128,7 +126,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) EraseInitStruct.Sector = SectorId; EraseInitStruct.NbSectors = 1; - if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){ + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { status = -1; } @@ -138,7 +136,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) } int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, - uint32_t size) + uint32_t size) { int32_t status = 0; @@ -150,17 +148,17 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, return -1; } - /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, - you have to make sure that these data are rewritten before they are accessed during code - execution. If this cannot be done safely, it is recommended to flush the caches by setting the - DCRST and ICRST bits in the FLASH_CR register. */ + /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, + you have to make sure that these data are rewritten before they are accessed during code + execution. If this cannot be done safely, it is recommended to flush the caches by setting the + DCRST and ICRST bits in the FLASH_CR register. */ __HAL_FLASH_ART_DISABLE(); __HAL_FLASH_ART_RESET(); __HAL_FLASH_ART_ENABLE(); while ((size > 0) && (status == 0)) { if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, - address, (uint64_t)*data) != HAL_OK) { + address, (uint64_t)*data) != HAL_OK) { status = -1; } else { size--; @@ -219,8 +217,7 @@ static uint32_t GetSector(uint32_t address) sector += 12 + (tmp >> 14); } else if (address < ADDR_FLASH_SECTOR_17) { // Sector 16 sector += FLASH_SECTOR_16; - } - else { // Sectors 17 to 23 + } else { // Sectors 17 to 23 tmp = address - ADDR_FLASH_SECTOR_12; sector += 16 + (tmp >> 17); } @@ -245,24 +242,24 @@ static uint32_t GetSectorSize(uint32_t Sector) { uint32_t sectorsize = 0x00; #if (MBED_CONF_TARGET_FLASH_DUAL_BANK) && defined(FLASH_OPTCR_nDBANK) - if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) ||\ - (Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3) ||\ - (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\ - (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { - sectorsize = 16 * 1024; + if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || \ + (Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3) || \ + (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \ + (Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) { + sectorsize = 16 * 1024; } else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) { - sectorsize = 64 * 1024; + sectorsize = 64 * 1024; } else { - sectorsize = 128 * 1024; + sectorsize = 128 * 1024; } #else // SINGLE BANK - if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) ||\ - (Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3)) { - sectorsize = 32 * 1024; + if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || \ + (Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3)) { + sectorsize = 32 * 1024; } else if (Sector == FLASH_SECTOR_4) { - sectorsize = 128 * 1024; + sectorsize = 128 * 1024; } else { - sectorsize = 256 * 1024; + sectorsize = 256 * 1024; } #endif return sectorsize; diff --git a/targets/TARGET_STM/TARGET_STM32F7/gpio_irq_device.h b/targets/TARGET_STM/TARGET_STM32F7/gpio_irq_device.h index 55f798e83f..4de74d7b65 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/gpio_irq_device.h +++ b/targets/TARGET_STM/TARGET_STM32F7/gpio_irq_device.h @@ -39,27 +39,27 @@ extern "C" { // until then let's define locally the required functions __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->RTSR, ExtiLine); + SET_BIT(EXTI->RTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->RTSR, ExtiLine); + CLEAR_BIT(EXTI->RTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->FTSR, ExtiLine); + SET_BIT(EXTI->FTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->FTSR, ExtiLine); + CLEAR_BIT(EXTI->FTSR, ExtiLine); } __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) { - SET_BIT(EXTI->IMR, ExtiLine); + SET_BIT(EXTI->IMR, ExtiLine); } __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) { - CLEAR_BIT(EXTI->IMR, ExtiLine); + CLEAR_BIT(EXTI->IMR, ExtiLine); } // Above lines shall be later defined in LL diff --git a/targets/TARGET_STM/TARGET_STM32F7/pin_device.h b/targets/TARGET_STM/TARGET_STM32F7/pin_device.h index 6551d95483..0409682715 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F7/pin_device.h @@ -72,35 +72,35 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); + MODIFY_REG(GPIOx->AFR[0], (0xFU << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); } __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { - MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + MODIFY_REG(GPIOx->AFR[1], (0xFU << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); } __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); } __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) { - return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin)); } __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); } __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); } __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); } // Above lines shall be defined in LL when available @@ -127,14 +127,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c index a1e131e998..49bae343a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c index b9e5d6b096..1c5d11a57a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c @@ -50,7 +50,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { @@ -131,7 +131,7 @@ static void uart8_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -270,7 +270,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -290,7 +290,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -312,7 +312,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -320,9 +320,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -394,7 +394,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -408,16 +408,16 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; @@ -425,11 +425,11 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -439,14 +439,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -467,18 +467,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -488,8 +488,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -501,10 +501,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -517,20 +517,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_TCF); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); } @@ -555,49 +557,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -605,7 +607,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -619,11 +621,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -633,17 +635,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC); // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -660,23 +662,23 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -706,9 +708,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -738,7 +740,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32F7/spi_api.c b/targets/TARGET_STM/TARGET_STM32F7/spi_api.c index 6e54e2bf93..f7c8cdbc2c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/spi_api.c @@ -39,35 +39,36 @@ #include "mbed_error.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: - case SPI_4: - case SPI_5: - case SPI_6: - /* SPI_1, SPI_4, SPI_5 and SPI_6. Source CLK is PCKL2 */ - spi_hz = HAL_RCC_GetPCLK2Freq(); - break; - case SPI_2: - case SPI_3: - /* SPI_2 and SPI_3. Source CLK is PCKL1 */ - spi_hz = HAL_RCC_GetPCLK1Freq(); - break; - default: - error("CLK: SPI instance not set"); + case SPI_4: + case SPI_5: + case SPI_6: + /* SPI_1, SPI_4, SPI_5 and SPI_6. Source CLK is PCKL2 */ + spi_hz = HAL_RCC_GetPCLK2Freq(); + break; + case SPI_2: + case SPI_3: + /* SPI_2 and SPI_3. Source CLK is PCKL1 */ + spi_hz = HAL_RCC_GetPCLK1Freq(); + break; + default: + error("CLK: SPI instance not set"); break; } return spi_hz; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c index 57d2f8c5e6..7155c2f943 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c @@ -119,28 +119,28 @@ MBED_WEAK const PinMap PinMap_PWM[] = { //*** SERIAL *** MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX // {PA_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX - {PA_4, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_4, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // {PA_9, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // STDIO UART // {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to TCK - {PA_14, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TCK + {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TCK // {PB_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, // STDIO UART - {PB_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PB_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RX[] = { // {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, // STDIO UART - {PA_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // STDIO UART - {PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // {PA_10, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // STDIO UART - {PA_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TMS + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TMS {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX // {PB_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, // STDIO UART - {PB_7, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PB_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {NC, NC, 0} }; @@ -148,13 +148,13 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_12, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PA_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_11, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h index 5348ec6a37..f5d7e2cf7d 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h @@ -47,12 +47,12 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, + PA_0_ALT0 = PA_0 | ALT0, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, @@ -64,20 +64,20 @@ typedef enum { PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, - PA_14_ALT0 = PA_14|ALT0, + PA_14_ALT0 = PA_14 | ALT0, PA_15 = 0x0F, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT0 = PB_0 | ALT0, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PC_14 = 0x2E, PC_15 = 0x2F, @@ -139,11 +139,11 @@ typedef enum { SPI_CS = PA_11, PWM_OUT = PB_0, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_PVD_IN = PB_7, SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c index c716fc315e..7d02650756 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c @@ -117,19 +117,19 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX // {PA_9, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // STDIO UART // {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to TCK // STDIO UART - {PA_14, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TCK + {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TCK // {PB_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, // STDIO UART {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RX[] = { // {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // STDIO UART - {PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // {PA_10, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // STDIO UART - {PA_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TMS + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TMS {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX // {PB_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, // STDIO UART {NC, NC, 0} @@ -139,13 +139,13 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_12, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PA_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_11, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h index de88cdd842..910facf89a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h @@ -49,9 +49,9 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, @@ -63,7 +63,7 @@ typedef enum { PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, - PA_14_ALT0 = PA_14|ALT0, + PA_14_ALT0 = PA_14 | ALT0, PA_15 = 0x0F, PB_0 = 0x10, @@ -135,11 +135,11 @@ typedef enum { SPI_CS = PA_11, PWM_OUT = PB_0, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_PVD_IN = PB_7, SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralPins.c index ad501034d0..aed8b19cce 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralPins.c @@ -153,18 +153,18 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to TCK - {PA_14_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TCK + {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TCK {PB_3, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PC_4, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PC_4, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PC_10_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PC_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART5)}, {NC, NC, 0} }; @@ -172,18 +172,18 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_RX + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_RX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PA_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TMS + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to TMS {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PC_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PC_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PC_11_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PC_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, {NC, NC, 0} }; @@ -192,22 +192,22 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PB_14, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PD_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PD_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h index abbe3c2729..23f98d939e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h @@ -49,19 +49,19 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -69,7 +69,7 @@ typedef enum { PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, - PA_14_ALT0 = PA_14|ALT0, + PA_14_ALT0 = PA_14 | ALT0, PA_15 = 0x0F, PB_0 = 0x10, @@ -77,11 +77,11 @@ typedef enum { PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, @@ -100,15 +100,15 @@ typedef enum { PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -180,19 +180,19 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PC_9, USB_NOE_ALT0 = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_PVD_IN = PB_7, SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralPins.c index d085bf54a6..1a3a48f30a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PeripheralPins.c @@ -129,7 +129,7 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to STDIO_UART_TX {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to SWCLK {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to ePD1_PWR_ENn [ePaper_PowerOn] + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to ePD1_PWR_ENn [ePaper_PowerOn] {NC, NC, 0} }; @@ -138,24 +138,24 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to STDIO_UART_RX {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to ePD1_CS [ePaper_CS\#] {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to ePD1_D/C [ePaper_D/C\#] + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to ePD1_D/C [ePaper_D/C\#] {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to MFX_WAKEUP {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to USB1_DP - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to TSC_G3_IO3 - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, // Connected to NFC_NSS - {PB_14, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to NFC_MISO + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to TSC_G3_IO3 + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, // Connected to NFC_NSS + {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to NFC_MISO {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to B1 [Blue PushButton] - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to TSC_G2_IO3 + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to TSC_G2_IO3 {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to USB1_DM - {PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to NFC_SCK + {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to NFC_SCK {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h index eba650a6f5..4c9c9ca7d2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/PinNames.h @@ -143,18 +143,18 @@ typedef enum { SPI_CS = PB_12, PWM_OUT = PB_11, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_PVD_IN = PB_7, SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c index 4b02e4ca31..eb16b93d37 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c @@ -55,7 +55,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100U; @@ -112,7 +112,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralPins.c index 0b67180580..4704edb300 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PeripheralPins.c @@ -137,9 +137,9 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to TCK {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PC_4, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PC_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PC_4, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PC_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {NC, NC, 0} }; @@ -148,27 +148,27 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PC_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PC_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PC_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PC_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, - {PB_14, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PD_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, + {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PD_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h index 3fcf2a8f68..7aab48fd39 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/PinNames.h @@ -156,19 +156,19 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PC_9, USB_NOE_ALT0 = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_PVD_IN = PB_7, SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c index a1e0bd793d..1d39c676f3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c @@ -55,7 +55,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100U; @@ -112,7 +112,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -145,7 +145,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ } else { diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c index 7a17d7afd2..1a9fee696f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c @@ -146,12 +146,12 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { // {PA_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_14_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PB_3, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, // Connected to RADIO_SCLK {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to RADIO_ANT_SWITCH_TX_BOOST + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to RADIO_ANT_SWITCH_TX_BOOST {NC, NC, 0} }; @@ -160,13 +160,13 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX // {PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PA_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to RADIO_NSS {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, // Connected to RADIO_DIO_0 {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to RADIO_RESET + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to RADIO_RESET {NC, NC, 0} }; @@ -174,21 +174,21 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to RADIO_ANT_SWITCH_RX {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to RADIO_TCXO_VCC {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, // Connected to RADIO_NSS - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to RADIO_DIO_1 + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to RADIO_DIO_1 {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, // Connected to RADIO_SCLK {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, // Connected to SPI2_NSS - {PB_14, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to SPI2_MISO + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, // Connected to SPI2_NSS + {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to SPI2_MISO {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to RADIO_MISO + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to RADIO_MISO {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, // Connected to RADIO_DIO_0 {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, - {PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to SPI2_SCK + {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Connected to SPI2_SCK {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h index 36e9b4d129..b7e4deab38 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h @@ -49,15 +49,15 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT0 = PA_7 | ALT0, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -65,7 +65,7 @@ typedef enum { PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, - PA_14_ALT0 = PA_14|ALT0, + PA_14_ALT0 = PA_14 | ALT0, PA_15 = 0x0F, PB_0 = 0x10, @@ -73,9 +73,9 @@ typedef enum { PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, @@ -156,18 +156,18 @@ typedef enum { SPI_CS = D10, PWM_OUT = D13, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_PVD_IN = PB_7, SYS_SWCLK = PA_14, SYS_SWDIO = PA_13, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/system_clock.c index f8bd4e8548..9c648f116e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/TARGET_DISCO_L072CZ_LRWAN1/system_clock.c @@ -58,7 +58,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100U; @@ -115,7 +115,7 @@ void SetSysClock(void) if (SetSysClock_PLL_HSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -170,7 +170,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } - + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz @@ -200,8 +200,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose if (bypass == 0) { // Xtal used HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_2); // 16 MHz - } - else { // External clock used + } else { // External clock used HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_4); // 8 MHz } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h index a765122eb9..719c703050 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/PinNames.h @@ -80,7 +80,7 @@ typedef enum { PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, - + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, @@ -122,7 +122,7 @@ typedef enum { LCD_A0 = PB_2, LCD_RESET = PB_5, LCD_NCS = PB_6, - + LORA_SPI_MOSI = PA_7, LORA_SPI_MISO = PA_6, LORA_SPI_SCLK = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c index 13b5448d3f..741e3ea0aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c @@ -42,7 +42,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100U; @@ -84,9 +84,8 @@ void SystemInit (void) */ void SetSysClock(void) { - if (SetSysClock_PLL_HSI() == 0) - { - while(1) { + if (SetSysClock_PLL_HSI() == 0) { + while (1) { MBED_ASSERT(1); } } diff --git a/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c index 499008b73a..72875691cf 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c @@ -39,7 +39,8 @@ static int channel1_used = 0; static int channel2_used = 0; -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object @@ -76,7 +77,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = DAC; obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -96,11 +97,16 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ // Reset DAC and disable clock - if (obj->channel == DAC_CHANNEL_1) channel1_used = 0; + if (obj->channel == DAC_CHANNEL_1) { + channel1_used = 0; + } #if defined(DAC_CHANNEL_2) - if (obj->channel == DAC_CHANNEL_2) channel2_used = 0; + if (obj->channel == DAC_CHANNEL_2) { + channel2_used = 0; + } #endif if ((channel1_used == 0) && (channel2_used == 0)) { __DAC_FORCE_RESET(); diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c index bd4a411cb0..8277e72854 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c @@ -95,7 +95,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) } int32_t flash_program_page(flash_t *obj, uint32_t address, - const uint8_t *data, uint32_t size) + const uint8_t *data, uint32_t size) { uint32_t StartAddress = 0; int32_t status = 0; @@ -121,7 +121,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, if ((uint32_t) data % 4 != 0) { volatile uint32_t data32; while ((address < (StartAddress + size)) && (status == 0)) { - for (uint8_t i =0; i < 4; i++) { + for (uint8_t i = 0; i < 4; i++) { *(((uint8_t *) &data32) + i) = *(data + i); } @@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, } } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) { address = address + 4; data = data + 4; } else { @@ -148,7 +148,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return status; } -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; } else { @@ -157,16 +158,19 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { } } -uint32_t flash_get_page_size(const flash_t *obj) { +uint32_t flash_get_page_size(const flash_t *obj) +{ /* Page size is the minimum programable size, which 4 bytes */ return 4; } -uint32_t flash_get_start_address(const flash_t *obj) { +uint32_t flash_get_start_address(const flash_t *obj) +{ return FLASH_BASE; } -uint32_t flash_get_size(const flash_t *obj) { +uint32_t flash_get_size(const flash_t *obj) +{ return FLASH_SIZE; } diff --git a/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h b/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h index 70558b6702..ace2076fe1 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h @@ -68,9 +68,9 @@ static inline uint32_t get_i2c_timing(int hz) switch (hz) { case 100000: tim = 0x20602938; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; + break; case 400000: - tim = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns + tim = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns break; case 1000000: tim = 0x0030040E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns diff --git a/targets/TARGET_STM/TARGET_STM32L0/pin_device.h b/targets/TARGET_STM/TARGET_STM32L0/pin_device.h index 8e17d97c57..314de2c10c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32L0/pin_device.h @@ -56,14 +56,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32L0/pwmout_device.c index c91d83f902..eb2f0e0043 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c index dad4bef293..2434f67820 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c @@ -33,11 +33,11 @@ #include "serial_api_hal.h" #if defined (TARGET_STM32L011K4) || defined (TARGET_STM32L031K6) - #define UART_NUM (2) +#define UART_NUM (2) #elif defined (TARGET_STM32L053x8) - #define UART_NUM (3) +#define UART_NUM (3) #else - #define UART_NUM (5) +#define UART_NUM (5) #endif uint32_t serial_irq_ids[UART_NUM] = {0}; @@ -57,7 +57,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { @@ -117,7 +117,7 @@ static void lpuart1_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -240,7 +240,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -260,7 +260,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -282,7 +282,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -290,9 +290,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -350,7 +350,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -364,28 +364,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -395,14 +395,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -423,18 +423,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -444,8 +444,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -457,10 +457,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -473,14 +473,15 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); } @@ -496,58 +497,58 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); if (__HAL_UART_GET_IT(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -555,7 +556,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -569,11 +570,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -583,17 +584,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - + // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -610,20 +611,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -653,9 +654,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -685,7 +686,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32L0/spi_api.c b/targets/TARGET_STM/TARGET_STM32L0/spi_api.c index 44c422c9f2..f9940cb530 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/spi_api.c @@ -39,9 +39,9 @@ #include "PeripheralPins.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif @@ -49,24 +49,25 @@ * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: - /* SPI_1. Source CLK is PCKL2 */ - spi_hz = HAL_RCC_GetPCLK2Freq(); - break; + /* SPI_1. Source CLK is PCKL2 */ + spi_hz = HAL_RCC_GetPCLK2Freq(); + break; #if defined(SPI2_BASE) - case SPI_2: - /* SPI_2. Source CLK is PCKL1 */ - spi_hz = HAL_RCC_GetPCLK1Freq(); - break; + case SPI_2: + /* SPI_2. Source CLK is PCKL1 */ + spi_hz = HAL_RCC_GetPCLK1Freq(); + break; #endif - default: - error("CLK: SPI instance not set"); + default: + error("CLK: SPI instance not set"); break; } return spi_hz; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h index e6b07bb6c0..587db5e99c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PeripheralNames.h @@ -50,9 +50,9 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; - #define STDIO_UART_TX PA_2 - #define STDIO_UART_RX PA_3 - #define STDIO_UART UART_2 +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 typedef enum { SPI_1 = (int)SPI1_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h index ef4e0c857f..cd2a07cb6d 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/PinNames.h @@ -234,7 +234,7 @@ typedef enum { I2C_SCL = I2C0_SCL, I2C_SDA = I2C0_SDA, - + } PinName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c index 6d24526b42..e241fcd67c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.c @@ -34,13 +34,13 @@ #define XDOT_EEPROM_SIZE 0x00002000 typedef union { - uint32_t* w; - uint8_t* b; + uint32_t *w; + uint8_t *b; } b2w; typedef union { - uint16_t* hw; - uint8_t* b; + uint16_t *hw; + uint8_t *b; } b2hw; enum { @@ -49,7 +49,8 @@ enum { word_write }; -static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) { +static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) +{ if (addr > XDOT_EEPROM_SIZE - 1) { return -1; } @@ -61,7 +62,8 @@ static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) { } } -static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) { +static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) +{ if (addr > XDOT_EEPROM_SIZE - 2) { return -1; } @@ -73,7 +75,8 @@ static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) { } } -static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) { +static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) +{ if (addr > XDOT_EEPROM_SIZE - 4) { return -1; } @@ -85,18 +88,20 @@ static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) { } } -static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) { +static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data) +{ if (addr > XDOT_EEPROM_SIZE - 1) { return -1; } - *data = (*((uint8_t*)(XDOT_EEPROM_START + addr))); + *data = (*((uint8_t *)(XDOT_EEPROM_START + addr))); return 0; } -int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { +int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size) +{ uint32_t bytes_written = 0; if (addr + size > XDOT_EEPROM_SIZE) { @@ -133,7 +138,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { } //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); } - if (! (mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) { + if (!(mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) { //printf("all match - no write necessary\r\n"); bytes_written += 4; continue; @@ -180,7 +185,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { } //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); } - if (! (mismatch[0] || mismatch[1])) { + if (!(mismatch[0] || mismatch[1])) { //printf("all match - no write necessary\r\n"); bytes_written += 2; continue; @@ -261,7 +266,8 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { return 0; } -int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size) { +int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size) +{ if (addr + size > XDOT_EEPROM_SIZE) { return -1; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h index e0ba7fa159..76bed5aa12 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_eeprom.h @@ -46,7 +46,7 @@ extern "C" { * valid addresses are 0x0000 - 0x1FFF * returns 0 if all data was successfully written otherwise -1 */ -int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size); +int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size); /* xdot_eeprom_read_buf * attempts to read size bytes into buf starting at addr @@ -54,7 +54,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size); * valid addresses are 0x0000 - 0x1FFF * returns 0 if all data was successfully read otherwise -1 */ -int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size); +int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size); #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c index 6910c01b46..7ac5efd4e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/xdot_low_power.c @@ -37,15 +37,18 @@ static uint32_t portB[6]; static uint32_t portC[6]; static uint32_t portH[6]; -void xdot_disable_systick_int() { +void xdot_disable_systick_int() +{ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; } -void xdot_enable_systick_int() { +void xdot_enable_systick_int() +{ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; } -void xdot_save_gpio_state() { +void xdot_save_gpio_state() +{ portA[0] = GPIOA->MODER; portA[1] = GPIOA->OTYPER; portA[2] = GPIOA->OSPEEDR; @@ -75,7 +78,8 @@ void xdot_save_gpio_state() { portH[5] = GPIOH->AFR[1]; } -void xdot_restore_gpio_state() { +void xdot_restore_gpio_state() +{ GPIOA->MODER = portA[0]; GPIOA->OTYPER = portA[1]; GPIOA->OSPEEDR = portA[2]; @@ -105,7 +109,8 @@ void xdot_restore_gpio_state() { GPIOH->AFR[1] = portH[5]; } -void xdot_enter_stop_mode() { +void xdot_enter_stop_mode() +{ GPIO_InitTypeDef GPIO_InitStruct; // disable ADC and DAC - they can consume power in stop mode @@ -224,8 +229,8 @@ void xdot_enter_stop_mode() { HSERCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; HSERCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */ HSERCC_OscInitStruct.HSIState = RCC_HSI_OFF; - // SYSCLK = 32 MHz ((24 MHz * 4) / 3) - // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK + // SYSCLK = 32 MHz ((24 MHz * 4) / 3) + // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK HSERCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; HSERCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; @@ -249,12 +254,12 @@ void xdot_enter_stop_mode() { /* Enable the HSI for ADC peripherals */ RCC_OscInitTypeDef HSIRCC_OscInitStruct; HAL_RCC_GetOscConfig(&HSIRCC_OscInitStruct); - if ( HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON ) { + if (HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON) { HSIRCC_OscInitStruct.HSIState = RCC_HSI_ON; HSIRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct); - if ( ret != HAL_OK ) { + if (ret != HAL_OK) { debug("HSI initialization failed - ADC will not function properly\r\n"); } } @@ -271,18 +276,22 @@ void xdot_enter_stop_mode() { DAC->CR |= DAC_CR_EN2; } -void xdot_enter_standby_mode() { +void xdot_enter_standby_mode() +{ // enable ULP and enable fast wakeup HAL_PWREx_EnableUltraLowPower(); HAL_PWREx_EnableFastWakeUp(); // disable HSI, MSI, and LSI if they are running - if (RCC->CR & RCC_CR_HSION) + if (RCC->CR & RCC_CR_HSION) { RCC->CR &= ~RCC_CR_HSION; - if (RCC->CR & RCC_CR_MSION) + } + if (RCC->CR & RCC_CR_MSION) { RCC->CR &= ~RCC_CR_MSION; - if (RCC->CSR & RCC_CSR_LSION) + } + if (RCC->CSR & RCC_CSR_LSION) { RCC->CSR &= ~RCC_CSR_LSION; + } // make sure wakeup and standby flags are cleared @@ -293,10 +302,12 @@ void xdot_enter_standby_mode() { HAL_PWR_EnterSTANDBYMode(); } -void xdot_enable_standby_wake_pin() { +void xdot_enable_standby_wake_pin() +{ HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1); } -void xdot_disable_standby_wake_pin() { +void xdot_disable_standby_wake_pin() +{ HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1); } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h index 8bb324361e..3550637433 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h @@ -94,7 +94,7 @@ typedef enum { SPI_RF_MISO = PA_6, SPI_RF_SCK = PA_5, SPI_RF_CS = PB_0, - SPI_RF_RESET= PB_13, + SPI_RF_RESET = PB_13, DIO0 = PA_11, DIO1 = PB_1, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h index a387f984e9..714b876540 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h @@ -48,19 +48,19 @@ typedef enum { typedef enum { PA_0 = 0x00, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -69,27 +69,27 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, PB_7 = 0x17, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, @@ -108,9 +108,9 @@ typedef enum { PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -181,17 +181,17 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_TRACESWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h index d193ae9f0b..dd0c1e0ecc 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PeripheralNames.h @@ -51,20 +51,20 @@ typedef enum { } UARTName; #if (MX_DEFAULT_SERIAL_PINS == 0) - //Use B10/B11 as default serial port - #define STDIO_UART_TX PB_10 - #define STDIO_UART_RX PB_11 - #define STDIO_UART UART_3 +//Use B10/B11 as default serial port +#define STDIO_UART_TX PB_10 +#define STDIO_UART_RX PB_11 +#define STDIO_UART UART_3 #elif (MX_DEFAULT_SERIAL_PINS == 1) - //Use A2/A3 as default serial port - #define STDIO_UART_TX PA_2 - #define STDIO_UART_RX PA_3 - #define STDIO_UART UART_2 +//Use A2/A3 as default serial port +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 #else - //Use A2/A3 as default serial port - #define STDIO_UART_TX PA_2 - #define STDIO_UART_RX PA_3 - #define STDIO_UART UART_2 +//Use A2/A3 as default serial port +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 #endif typedef enum { diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralNames.h index e6b07bb6c0..587db5e99c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PeripheralNames.h @@ -50,9 +50,9 @@ typedef enum { UART_3 = (int)USART3_BASE } UARTName; - #define STDIO_UART_TX PA_2 - #define STDIO_UART_RX PA_3 - #define STDIO_UART UART_2 +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 typedef enum { SPI_1 = (int)SPI1_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h index 4bf3b2f446..03d7d6c9cb 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h @@ -151,7 +151,7 @@ typedef enum { I2C_SCL = I2C1_SCL, I2C_SDA = I2C1_SDA, - + // LoRa LORA_RESET = PA_1, LORA_MOSI = PB_5, diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.c index 6a8bd65764..07fc54362c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.c @@ -34,13 +34,13 @@ #define XDOT_EEPROM_SIZE 0x00002000 typedef union { - uint32_t* w; - uint8_t* b; + uint32_t *w; + uint8_t *b; } b2w; typedef union { - uint16_t* hw; - uint8_t* b; + uint16_t *hw; + uint8_t *b; } b2hw; enum { @@ -49,7 +49,8 @@ enum { word_write }; -static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) { +static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) +{ if (addr > XDOT_EEPROM_SIZE - 1) { return -1; } @@ -61,7 +62,8 @@ static int xdot_eeprom_write_byte(uint32_t addr, uint8_t data) { } } -static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) { +static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) +{ if (addr > XDOT_EEPROM_SIZE - 2) { return -1; } @@ -73,7 +75,8 @@ static int xdot_eeprom_write_hword(uint32_t addr, uint16_t data) { } } -static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) { +static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) +{ if (addr > XDOT_EEPROM_SIZE - 4) { return -1; } @@ -85,18 +88,20 @@ static int xdot_eeprom_write_word(uint32_t addr, uint32_t data) { } } -static int xdot_eeprom_read_byte(uint32_t addr, uint8_t* data) { +static int xdot_eeprom_read_byte(uint32_t addr, uint8_t *data) +{ if (addr > XDOT_EEPROM_SIZE - 1) { return -1; } - *data = (*((uint8_t*)(XDOT_EEPROM_START + addr))); + *data = (*((uint8_t *)(XDOT_EEPROM_START + addr))); return 0; } -int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { +int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size) +{ uint32_t bytes_written = 0; if (addr + size > XDOT_EEPROM_SIZE) { @@ -133,7 +138,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { } //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); } - if (! (mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) { + if (!(mismatch[0] || mismatch[1] || mismatch[2] || mismatch[3])) { //printf("all match - no write necessary\r\n"); bytes_written += 4; continue; @@ -180,7 +185,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { } //printf("%smatch\r\n", mismatch[i] ? "mis" : ""); } - if (! (mismatch[0] || mismatch[1])) { + if (!(mismatch[0] || mismatch[1])) { //printf("all match - no write necessary\r\n"); bytes_written += 2; continue; @@ -261,7 +266,8 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size) { return 0; } -int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size) { +int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size) +{ if (addr + size > XDOT_EEPROM_SIZE) { return -1; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.h index 16bd1824e3..60f1f007c2 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_eeprom.h @@ -46,7 +46,7 @@ extern "C" { * valid addresses are 0x0000 - 0x1FFF * returns 0 if all data was successfully written otherwise -1 */ -int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size); +int xdot_eeprom_write_buf(uint32_t addr, uint8_t *buf, uint32_t size); /* xdot_eeprom_read_buf * attempts to read size bytes into buf starting at addr @@ -54,7 +54,7 @@ int xdot_eeprom_write_buf(uint32_t addr, uint8_t* buf, uint32_t size); * valid addresses are 0x0000 - 0x1FFF * returns 0 if all data was successfully read otherwise -1 */ -int xdot_eeprom_read_buf(uint32_t addr, uint8_t* buf, uint32_t size); +int xdot_eeprom_read_buf(uint32_t addr, uint8_t *buf, uint32_t size); #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c index 437a576ecb..10fef98e15 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c @@ -37,15 +37,18 @@ static uint32_t portB[6]; static uint32_t portC[6]; static uint32_t portH[6]; -void xdot_disable_systick_int() { +void xdot_disable_systick_int() +{ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; } -void xdot_enable_systick_int() { +void xdot_enable_systick_int() +{ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; } -void xdot_save_gpio_state() { +void xdot_save_gpio_state() +{ portA[0] = GPIOA->MODER; portA[1] = GPIOA->OTYPER; portA[2] = GPIOA->OSPEEDR; @@ -75,7 +78,8 @@ void xdot_save_gpio_state() { portH[5] = GPIOH->AFR[1]; } -void xdot_restore_gpio_state() { +void xdot_restore_gpio_state() +{ GPIOA->MODER = portA[0]; GPIOA->OTYPER = portA[1]; GPIOA->OSPEEDR = portA[2]; @@ -105,7 +109,8 @@ void xdot_restore_gpio_state() { GPIOH->AFR[1] = portH[5]; } -void xdot_enter_stop_mode() { +void xdot_enter_stop_mode() +{ GPIO_InitTypeDef GPIO_InitStruct; // disable ADC and DAC - they can consume power in stop mode @@ -224,8 +229,8 @@ void xdot_enter_stop_mode() { HSERCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; HSERCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */ HSERCC_OscInitStruct.HSIState = RCC_HSI_OFF; - // SYSCLK = 32 MHz ((24 MHz * 4) / 3) - // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK + // SYSCLK = 32 MHz ((24 MHz * 4) / 3) + // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK HSERCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; HSERCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; @@ -249,12 +254,12 @@ void xdot_enter_stop_mode() { /* Enable the HSI for ADC peripherals */ RCC_OscInitTypeDef HSIRCC_OscInitStruct; HAL_RCC_GetOscConfig(&HSIRCC_OscInitStruct); - if ( HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON ) { + if (HSIRCC_OscInitStruct.HSIState != RCC_HSI_ON) { HSIRCC_OscInitStruct.HSIState = RCC_HSI_ON; HSIRCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct); - if ( ret != HAL_OK ) { + if (ret != HAL_OK) { debug("HSI initialization failed - ADC will not function properly\r\n"); } } @@ -271,18 +276,22 @@ void xdot_enter_stop_mode() { DAC->CR |= DAC_CR_EN2; } -void xdot_enter_standby_mode() { +void xdot_enter_standby_mode() +{ // enable ULP and enable fast wakeup HAL_PWREx_EnableUltraLowPower(); HAL_PWREx_EnableFastWakeUp(); // disable HSI, MSI, and LSI if they are running - if (RCC->CR & RCC_CR_HSION) + if (RCC->CR & RCC_CR_HSION) { RCC->CR &= ~RCC_CR_HSION; - if (RCC->CR & RCC_CR_MSION) + } + if (RCC->CR & RCC_CR_MSION) { RCC->CR &= ~RCC_CR_MSION; - if (RCC->CSR & RCC_CSR_LSION) + } + if (RCC->CSR & RCC_CSR_LSION) { RCC->CSR &= ~RCC_CSR_LSION; + } // make sure wakeup and standby flags are cleared @@ -293,11 +302,13 @@ void xdot_enter_standby_mode() { HAL_PWR_EnterSTANDBYMode(); } -void xdot_enable_standby_wake_pin() { +void xdot_enable_standby_wake_pin() +{ HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1); } -void xdot_disable_standby_wake_pin() { +void xdot_disable_standby_wake_pin() +{ HAL_PWR_DisableWakeUpPin(PWR_WAKEUP_PIN1); } diff --git a/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c index 2220b7d592..a72087b96c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c @@ -39,7 +39,8 @@ static int pa4_used = 0; static int pa5_used = 0; -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object @@ -70,7 +71,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = DAC; obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -94,10 +95,15 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ // Reset DAC and disable clock - if (obj->pin == PA_4) pa4_used = 0; - if (obj->pin == PA_5) pa5_used = 0; + if (obj->pin == PA_4) { + pa4_used = 0; + } + if (obj->pin == PA_5) { + pa5_used = 0; + } if ((pa4_used == 0) && (pa5_used == 0)) { __DAC_FORCE_RESET(); __DAC_RELEASE_RESET(); diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c index 5e6932071f..2b6389440d 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c @@ -93,7 +93,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) } int32_t flash_program_page(flash_t *obj, uint32_t address, - const uint8_t *data, uint32_t size) + const uint8_t *data, uint32_t size) { uint32_t StartAddress = 0; int32_t status = 0; @@ -119,7 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, if ((uint32_t) data % 4 != 0) { volatile uint32_t data32; while (address < (StartAddress + size) && (status == 0)) { - for (uint8_t i =0; i < 4; i++) { + for (uint8_t i = 0; i < 4; i++) { *(((uint8_t *) &data32) + i) = *(data + i); } @@ -132,7 +132,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, } } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { - if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) { address = address + 4; data = data + 4; } else { @@ -146,7 +146,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return status; } -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; @@ -161,12 +161,12 @@ uint32_t flash_get_page_size(const flash_t *obj) return 4; } -uint32_t flash_get_start_address(const flash_t *obj) +uint32_t flash_get_start_address(const flash_t *obj) { return FLASH_BASE; } -uint32_t flash_get_size(const flash_t *obj) +uint32_t flash_get_size(const flash_t *obj) { return FLASH_SIZE; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/pin_device.h b/targets/TARGET_STM/TARGET_STM32L1/pin_device.h index d81e5a5e90..bc8ed8475f 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32L1/pin_device.h @@ -56,14 +56,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32L1/pwmout_device.c index 1b9580f2ea..3a73793727 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c index 5d85a0a9c0..e46baaeb2e 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c @@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { @@ -111,7 +111,7 @@ static void uart5_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -240,7 +240,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -260,7 +260,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -282,7 +282,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -290,9 +290,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -349,7 +349,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -363,28 +363,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -394,14 +394,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -422,18 +422,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -443,8 +443,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -456,10 +456,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -472,20 +472,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { @@ -507,49 +509,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } -} + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -557,7 +559,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -570,12 +572,12 @@ int serial_irq_handler_asynch(serial_t *obj) } } } + } + + return return_event; } - return return_event; -} - -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -585,17 +587,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - + // reset states huart->TxXferCount = 0; // update handle state - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->State == HAL_UART_STATE_BUSY_TX_RX) { huart->State = HAL_UART_STATE_BUSY_RX; } else { huart->State = HAL_UART_STATE_READY; @@ -612,20 +614,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->State == HAL_UART_STATE_BUSY_TX_RX) { huart->State = HAL_UART_STATE_BUSY_TX; } else { huart->State = HAL_UART_STATE_READY; @@ -655,9 +657,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -687,7 +689,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32L1/spi_api.c b/targets/TARGET_STM/TARGET_STM32L1/spi_api.c index da5d93542c..b2e0d8646a 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/spi_api.c @@ -39,34 +39,35 @@ #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: - /* SPI_1. Source CLK is PCKL2 */ - spi_hz = HAL_RCC_GetPCLK2Freq(); - break; - case SPI_2: + /* SPI_1. Source CLK is PCKL2 */ + spi_hz = HAL_RCC_GetPCLK2Freq(); + break; + case SPI_2: #ifdef SPI_3 case SPI_3: #endif - /* SPI_2, SPI_3. Source CLK is PCKL1 */ - spi_hz = HAL_RCC_GetPCLK1Freq(); - break; - default: - error("CLK: SPI instance not set"); + /* SPI_2, SPI_3. Source CLK is PCKL1 */ + spi_hz = HAL_RCC_GetPCLK1Freq(); + break; + default: + error("CLK: SPI instance not set"); break; } return spi_hz; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c index dc274d7e90..cb5bbaff5b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c @@ -145,14 +145,14 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h index 1376f3606c..c7842cff3a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h @@ -46,70 +46,70 @@ typedef enum { } ALTx; typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, - PA_5 = 0x05, - PA_6 = 0x06, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, - PB_0 = 0x10, - PB_1 = 0x11, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_6 = 0x16, - PB_7 = 0x17, + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_6 = 0x16, + PB_7 = 0x17, - PC_14 = 0x2E, - PC_15 = 0x2F, + PC_14 = 0x2E, + PC_15 = 0x2F, - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, - // Arduino connector namings - A0 = PA_0, - A1 = PA_1, - A2 = PA_3, - A3 = PA_4, - A4 = PA_5, - A5 = PA_6, - A6 = PA_7, - A7 = PA_2, - D0 = PA_10, - D1 = PA_9, - D2 = PA_12, - D3 = PB_0, - D4 = PB_7, - D5 = PB_6, - D6 = PB_1, - D7 = PC_14, - D8 = PC_15, - D9 = PA_8, - D10 = PA_11, - D11 = PB_5, - D12 = PB_4, - D13 = PB_3, + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_3, + A3 = PA_4, + A4 = PA_5, + A5 = PA_6, + A6 = PA_7, + A7 = PA_2, + D0 = PA_10, + D1 = PA_9, + D2 = PA_12, + D3 = PB_0, + D4 = PB_7, + D5 = PB_6, + D6 = PB_1, + D7 = PC_14, + D8 = PC_15, + D9 = PA_8, + D10 = PA_11, + D11 = PB_5, + D12 = PB_4, + D13 = PB_3, // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX @@ -123,33 +123,33 @@ typedef enum { STDIO_UART_RX = PA_15, #endif - // Generic signals namings - LED1 = PB_3, - LED2 = PB_3, - LED3 = PB_3, - LED4 = PB_3, - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - I2C_SCL = PB_6, - I2C_SDA = PB_7, - SPI_MOSI = PB_5, - SPI_MISO = PB_4, - SPI_SCK = PB_3, - SPI_CS = PA_11, - PWM_OUT = PB_0, + // Generic signals namings + LED1 = PB_3, + LED2 = PB_3, + LED3 = PB_3, + LED4 = PB_3, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + I2C_SCL = PB_6, + I2C_SDA = PB_7, + SPI_MOSI = PB_5, + SPI_MISO = PB_4, + SPI_SCK = PB_3, + SPI_CS = PA_11, + PWM_OUT = PB_0, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c index 59bc3ee8e4..e6b3380007 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c @@ -85,7 +85,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -139,7 +139,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -147,7 +147,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -232,10 +232,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c index 74b95de8b0..405e6778ad 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c @@ -150,12 +150,12 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Only STM32L433RC, not STM32L433RC-P {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, @@ -164,13 +164,13 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Only STM32L433RC, not STM32L433RC-P {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} @@ -181,9 +181,9 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Only STM32L433RC, not STM32L433RC-P {NC, NC, 0} @@ -192,11 +192,11 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK] - {PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK] + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK] {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD4 [green Led] - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD4 [green Led] + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD4 [green Led] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h index ba78823b10..9cc9fcf3de 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h @@ -46,143 +46,143 @@ typedef enum { } ALTx; typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, - PA_5 = 0x05, - PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_0 = 0x00, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, - PB_0 = 0x10, - PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, + PB_0 = 0x10, + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13 | ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, #ifndef STM32L433_48PINS // 48 pin versions don't have PC0-PC15 pins - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, #endif - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, - PD_2 = 0x32, + PD_2 = 0x32, #ifdef STM32L433_100PINS // LQFP100 or UFBGA100 versions - PD_0 = 0x30, - PD_1 = 0x31, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_7 = 0x37, - PD_8 = 0x38, - PD_9 = 0x39, - PD_10 = 0x3A, - PD_11 = 0x3B, - PD_12 = 0x3C, - PD_13 = 0x3D, - PD_14 = 0x3E, - PD_15 = 0x3F, - - PE_0 = 0x40, - PE_1 = 0x41, - PE_2 = 0x42, - PE_3 = 0x43, - PE_4 = 0x44, - PE_5 = 0x45, - PE_6 = 0x46, - PE_7 = 0x47, - PE_8 = 0x48, - PE_9 = 0x49, - PE_10 = 0x4A, - PE_11 = 0x4B, - PE_12 = 0x4C, - PE_13 = 0x4D, - PE_14 = 0x4E, - PE_15 = 0x4F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, #endif - PH_0 = 0x70, - PH_1 = 0x71, + PH_0 = 0x70, + PH_1 = 0x71, - PH_3 = 0x73, + PH_3 = 0x73, - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, - // Arduino connector namings - A0 = PA_0, - A1 = PA_1, - A2 = PC_3, - A3 = PC_2, - A4 = PC_1, - A5 = PC_0, - D0 = PA_2, - D1 = PA_3, - D2 = PA_12, - D3 = PB_3, - D4 = PB_5, - D5 = PA_15, - D6 = PB_10, - D7 = PC_7, - D8 = PB_6, - D9 = PA_8, - D10 = PA_11, - D11 = PB_15, - D12 = PB_14, - D13 = PB_13, - D14 = PB_7, - D15 = PB_8, + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PC_3, + A3 = PC_2, + A4 = PC_1, + A5 = PC_0, + D0 = PA_2, + D1 = PA_3, + D2 = PA_12, + D3 = PB_3, + D4 = PB_5, + D5 = PA_15, + D6 = PB_10, + D7 = PC_7, + D8 = PB_6, + D9 = PA_8, + D10 = PA_11, + D11 = PB_15, + D12 = PB_14, + D13 = PB_13, + D14 = PB_7, + D15 = PB_8, - // STDIO for console print + // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, #else @@ -194,38 +194,38 @@ typedef enum { STDIO_UART_RX = PA_3, #endif - // Generic signals namings - LED1 = PB_13, - LED2 = PB_13, - LED3 = PB_13, - LED4 = PB_13, - USER_BUTTON = PC_13, - BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = STDIO_UART_TX, - USBRX = STDIO_UART_RX, - I2C_SCL = PB_8, - I2C_SDA = PB_7, - SPI_MOSI = D11, - SPI_MISO = D12, - SPI_SCK = D13, - SPI_CS = D10, - PWM_OUT = D9, + // Generic signals namings + LED1 = PB_13, + LED2 = PB_13, + LED3 = PB_13, + LED4 = PB_13, + USER_BUTTON = PC_13, + BUTTON1 = USER_BUTTON, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + I2C_SCL = PB_8, + I2C_SDA = PB_7, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PC_9, USB_NOE_ALT0 = PA_13, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c index 59bc3ee8e4..e6b3380007 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c @@ -85,7 +85,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -139,7 +139,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -147,7 +147,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -232,10 +232,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PeripheralPins.c index c216bc2790..c0d4adb1f6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PeripheralPins.c @@ -71,7 +71,7 @@ __weak const PinMap PinMap_ADC[] = { {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 {NC, NC, 0} }; @@ -160,7 +160,7 @@ __weak const PinMap PinMap_UART_TX[] = { {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; @@ -174,7 +174,7 @@ __weak const PinMap PinMap_UART_RX[] = { {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; @@ -188,7 +188,7 @@ __weak const PinMap PinMap_UART_RTS[] = { {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PinNames.h index 9f9cac5c9e..8d19d14560 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/PinNames.h @@ -38,175 +38,175 @@ extern "C" { #endif typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 } ALTx; typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, - PA_5 = 0x05, - PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, - PA_7 = 0x07, - PA_8 = 0x08, - PA_9 = 0x09, - PA_10 = 0x0A, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_0 = 0x00, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, - PB_0 = 0x10, - PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_2 = 0x12, - PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, - PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_6 = 0x16, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, + PB_0 = 0x10, + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13 | ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_5 = 0x25, - PC_6 = 0x26, - PC_7 = 0x27, - PC_8 = 0x28, - PC_9 = 0x29, - PC_10 = 0x2A, - PC_11 = 0x2B, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, - - PD_2 = 0x32, + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, - PH_0 = 0x70, - PH_1 = 0x71, + PD_2 = 0x32, - PH_3 = 0x73, + PH_0 = 0x70, + PH_1 = 0x71, - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, + PH_3 = 0x73, - // Module's signals on M.2 connector - USB_DP = PA_12, - USB_DM = PA_11, + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, - UART3_RX = PB_11, - UART3_TX = PC_4, - UART3_CTS = PB_13, - UART3_RTS = PB_1, + // Module's signals on M.2 connector + USB_DP = PA_12, + USB_DM = PA_11, - CB_NRESET_OUT = PC_6, - CB_POWER_ON = PC_9, + UART3_RX = PB_11, + UART3_TX = PC_4, + UART3_CTS = PB_13, + UART3_RTS = PB_1, - GPIO0 = PA_8, - GPIO1 = PC_8, - GPIO2 = PC_7, - GPIO3 = PC_5, - GPIO4 = PB_0, - GPIO5 = PA_3, - GPIO6 = PA_2, - GPIO7 = PB_6, + CB_NRESET_OUT = PC_6, + CB_POWER_ON = PC_9, - PWM0 = PA_5, + GPIO0 = PA_8, + GPIO1 = PC_8, + GPIO2 = PC_7, + GPIO3 = PC_5, + GPIO4 = PB_0, + GPIO5 = PA_3, + GPIO6 = PA_2, + GPIO7 = PB_6, - ADC0 = PA_7, - ADC2 = PA_6, - ADC3 = PA_4, - ADC4 = PA_0, + PWM0 = PA_5, - BACKUP = PA_1, - W_DISABLE = PC_2, - WAKE = PC_3, + ADC0 = PA_7, + ADC2 = PA_6, + ADC3 = PA_4, + ADC4 = PA_0, - I2C_SCL = PC_0, - I2C_SDA = PC_1, + BACKUP = PA_1, + W_DISABLE = PC_2, + WAKE = PC_3, - SPI_MOSI = PB_15, - SPI_MISO = PB_14, - SPI_SCK = PB_10, - SPI_CS0 = PB_12, - SPI_CS1 = PB_9, + I2C_SCL = PC_0, + I2C_SDA = PC_1, - // internal & debug assumed from WISE-1511 - UART1_TX = PA_9, - UART1_RX = PA_10, + SPI_MOSI = PB_15, + SPI_MISO = PB_14, + SPI_SCK = PB_10, + SPI_CS0 = PB_12, + SPI_CS1 = PB_9, - SPI_RF_MOSI = PB_5, - SPI_RF_MISO = PB_4, - SPI_RF_SCK = PB_3, - SPI_RF_CS = PA_15, - SPI_RF_RESET= PC_14, + // internal & debug assumed from WISE-1511 + UART1_TX = PA_9, + UART1_RX = PA_10, - DIO0 = PC_13, - DIO1 = PB_8, - DIO2 = PB_7, - DIO3 = PD_2, - DIO4 = PC_11, - DIO5 = PC_10, + SPI_RF_MOSI = PB_5, + SPI_RF_MISO = PB_4, + SPI_RF_SCK = PB_3, + SPI_RF_CS = PA_15, + SPI_RF_RESET = PC_14, - ANT_SWITCH = PC_15, + DIO0 = PC_13, + DIO1 = PB_8, + DIO2 = PB_7, + DIO3 = PD_2, + DIO4 = PC_11, + DIO5 = PC_10, - // Generic signals namings - LED1 = PWM0, - LED2 = GPIO2, - LED3 = GPIO4, + ANT_SWITCH = PC_15, + + // Generic signals namings + LED1 = PWM0, + LED2 = GPIO2, + LED3 = GPIO4, #ifdef MBED_CONF_TARGET_STDIO_UART_TX - STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, #else - STDIO_UART_TX = UART3_TX, + STDIO_UART_TX = UART3_TX, #endif #ifdef MBED_CONF_TARGET_STDIO_UART_RX - STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, #else - STDIO_UART_RX = UART3_RX, + STDIO_UART_RX = UART3_RX, #endif - SERIAL_TX = STDIO_UART_TX, - SERIAL_RX = STDIO_UART_RX, - USBTX = SERIAL_TX, - USBRX = SERIAL_RX, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, - UART_TXD = UART1_TX, - UART_RXD = UART1_RX, + UART_TXD = UART1_TX, + UART_RXD = UART1_RX, - // Not connected - NC = (int)0xFFFFFFFF + // Not connected + NC = (int)0xFFFFFFFF } PinName; #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c index 59bc3ee8e4..e6b3380007 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L443xC/TARGET_MTB_ADV_WISE_1510/system_clock.c @@ -85,7 +85,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -139,7 +139,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -147,7 +147,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -232,10 +232,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c index 2708f51ea2..a21e78ce22 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PeripheralPins.c @@ -218,8 +218,8 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS [STMPS2141STR_OUT] {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A4 [ADC] + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A4 [ADC] {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A1 [ADC] {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to INTERNAL_SPI3_SCK [BT module_SPI_SCLK] @@ -234,9 +234,9 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ARD_D4 {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_ID {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to INTERNAL_I2C2_SCL [VL53L0X_SCL] {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_I2C2_SDA [VL53L0X_SDA] - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A5 [ADC] + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A5 [ADC] {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A0 [ADC] {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to INTERNAL_SPI3_MISO [BT module_SPI_MISO] @@ -253,7 +253,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_D6 [ADC1_IN6] {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_BOOT0 [ISM43362_BOOT] + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_BOOT0 [ISM43362_BOOT] {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED2 [LED_GREEN] {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD_IRQ_EXTI12 {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_RTS @@ -269,7 +269,7 @@ MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS] {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to STDIO_UART_RX {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ISM43362_WAKEUP [ISM43362_WKUP] {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD_UART2_CTS {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LSM6DSL_INT1_EXTI11 [LSM6DSL_INT1] {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h index 0333240ca0..6bc541ec78 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/PinNames.h @@ -47,23 +47,23 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, + PA_0_ALT0 = PA_0 | ALT0, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, + PA_1_ALT0 = PA_1 | ALT0, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -72,69 +72,69 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -241,7 +241,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -250,13 +250,13 @@ typedef enum { USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c index ee5ac4b40c..6e959a9da5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c index 770d94ef6c..1207a19095 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PeripheralPins.c @@ -218,8 +218,8 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to COM1 [GH08172T_COM1] {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SCL [SSM-104-L-DH_SCL] {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL] - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA] - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MAG_INT [LSM303CTR_MAG_INT] + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA] + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MAG_INT [LSM303CTR_MAG_INT] {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG22 [GH08172T_SEG22] {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to OTG_FS_OverCurrent [STMPS2141STR_FAULT] {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to OTG_FS_OverCurrent [STMPS2141STR_FAULT] @@ -234,9 +234,9 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to JOY_UP [MT-008A_UP] {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to COM2 [GH08172T_COM2] {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SDA [SSM-104-L-DH_SDA] - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL] + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to MFX_I2C_SLC [MFX_V2_I2C_SCL] {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to MFX_I2C_SDA [MFX_V2_I2C_SDA] - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to GPIO_Input + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to GPIO_Input {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG1 [GH08172T_SEG1] {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to OTG_FS_VBUS [EMIF02-USB03F2_Vbus] {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to OTG_FS_VBUS [EMIF02-USB03F2_Vbus] @@ -253,7 +253,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG2 [GH08172T_SEG2] {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SEG20 [GH08172T_SEG20] + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SEG20 [GH08172T_SEG20] {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG19 [GH08172T_SEG19] {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to GYRO_INT1 [L3GD20_INT1] {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_MOSI [L3GD20_SDA/SDI/SDO] @@ -269,7 +269,7 @@ MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SEG12 [GH08172T_SEG12] {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to I2C1_SDA [SSM-104-L-DH_SDA] {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG3 [GH08172T_SEG3] - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SEG3 [GH08172T_SEG3] + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SEG3 [GH08172T_SEG3] {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_MISO [L3GD20_SA0/SDO] {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SEG6 [GH08172T_SEG6] {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h index 9d7c42bb31..8fe525f639 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/PinNames.h @@ -47,23 +47,23 @@ typedef enum { typedef enum { PA_0 = 0x00, // On P1/P2 connectors - PA_0_ALT0 = PA_0|ALT0, + PA_0_ALT0 = PA_0 | ALT0, PA_1 = 0x01, // On P1/P2 connectors - PA_1_ALT0 = PA_1|ALT0, + PA_1_ALT0 = PA_1 | ALT0, PA_2 = 0x02, // On P1/P2 connectors - PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT0 = PA_2 | ALT0, PA_3 = 0x03, // On P1/P2 connectors - PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT0 = PA_3 | ALT0, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, // On P1/P2 connectors - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -72,69 +72,69 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, // On P1/P2 connectors PB_3 = 0x13, // On P1/P2 connectors - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, // On P1/P2 connectors - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, // On P1/P2 connectors - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, // On P1/P2 connectors @@ -209,7 +209,7 @@ typedef enum { BUTTON1 = USER_BUTTON, BUTTON2 = JOYSTICK_LEFT, BUTTON3 = JOYSTICK_RIGHT, - BUTTON4 = JOYSTICK_UP, + BUTTON4 = JOYSTICK_UP, BUTTON5 = JOYSTICK_DOWN, SERIAL_TX = STDIO_UART_TX, @@ -225,7 +225,7 @@ typedef enum { SPI_CS = PA_4, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -234,13 +234,13 @@ typedef enum { USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c index ee5ac4b40c..6e959a9da5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_DISCO_L476VG/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c index 35ad43a03b..008265a2ac 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c @@ -201,8 +201,8 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, @@ -215,9 +215,9 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, @@ -232,7 +232,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} @@ -246,7 +246,7 @@ MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h index e3ed27590b..8e2bf1d467 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PinNames.h @@ -47,23 +47,23 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -72,73 +72,73 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -210,7 +210,7 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -219,13 +219,13 @@ typedef enum { USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c index ee5ac4b40c..6e959a9da5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c index b2cf6b0af1..aa859f6379 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c @@ -201,13 +201,13 @@ const PinMap PinMap_UART_RTS[] = { // {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 {NC, NC, 0} }; - + const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, -// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, +// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 {NC, NC, 0} @@ -257,13 +257,13 @@ const PinMap PinMap_SPI_SSEL[] = { }; const PinMap PinMap_CAN_RD[] = { - {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; const PinMap PinMap_CAN_TD[] = { - {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c index ee5ac4b40c..6e959a9da5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/PeripheralPins.c index b47e64ddac..fbdf0674ce 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/PeripheralPins.c @@ -100,7 +100,7 @@ const PinMap PinMap_UART_RTS[] = { {UART_RTS, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; - + const PinMap PinMap_UART_CTS[] = { {UART_CTS, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c index ab36318872..6d9e310be4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_MTB_ADV_WISE_1570/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -231,10 +231,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c index 35ad43a03b..008265a2ac 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PeripheralPins.c @@ -201,8 +201,8 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, @@ -215,9 +215,9 @@ MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, @@ -232,7 +232,7 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} @@ -246,7 +246,7 @@ MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h index e3ed27590b..8e2bf1d467 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/PinNames.h @@ -47,23 +47,23 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, - PA_0_ALT1 = PA_0|ALT1, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, PA_3 = 0x03, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -72,73 +72,73 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, - PB_4_ALT1 = PB_4|ALT1, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, - PB_5_ALT1 = PB_5|ALT1, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, - PB_8_ALT1 = PB_8|ALT1, + PB_8_ALT0 = PB_8 | ALT0, + PB_8_ALT1 = PB_8 | ALT1, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, - PB_9_ALT1 = PB_9|ALT1, + PB_9_ALT0 = PB_9 | ALT0, + PB_9_ALT1 = PB_9 | ALT1, PB_10 = 0x1A, PB_11 = 0x1B, PB_12 = 0x1C, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -210,7 +210,7 @@ typedef enum { SPI_CS = PB_6, PWM_OUT = PB_3, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -219,13 +219,13 @@ typedef enum { USB_OTG_FS_SOF = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c index 6bdfc8669f..ba758b2bc7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/TARGET_NUCLEO_L486RG/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -219,10 +219,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c index d8e89cf765..185aa4f699 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c @@ -257,19 +257,19 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to STMOD_PWM {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_VBUS {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USART1_TX {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SAI1_SCK_A - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS] - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ADCx_IN2 + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS] + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ADCx_IN2 {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ARD_A0 {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D2 {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D2 {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CLK {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to WE [WE_IS66WV51216EBLL] {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13 [D13_IS66WV51216EBLL] - {PG_7, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D1 + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D1 {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to PSRAM_NE [CS1_IS66WV51216EBLL] {NC, NC, 0} }; @@ -277,20 +277,20 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ARD_A4 {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to QSPI_CLK [MX25R6435FM2IL0_SCLK] - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_CLK [MX25R6435FM2IL0_SCLK] + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_CLK [MX25R6435FM2IL0_SCLK] {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_ID {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to I2C1_SDA - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SAI1_SCK_A + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SAI1_SCK_A {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to QSPI_BK1_NCS [MX25R6435FM2IL0_CS] - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A5 + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_A5 {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to MFX_IRQ_OUT {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_D3 {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to uSD_D3 {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to uSD_CMD {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D14 [D14_IS66WV51216EBLL] - {PG_8, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D0 + {PG_8, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to ARD_D0 {PG_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to UART1_RX [STMOD+_UART] {NC, NC, 0} }; @@ -301,15 +301,15 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to QSPI_BK1_IO0 [MX25R6435FM2IL0_SIO0] - {PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK1_IO0 [MX25R6435FM2IL0_SIO0] + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK1_IO0 [MX25R6435FM2IL0_SIO0] {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to DFDATIN1 + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to DFDATIN1 {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to I2C2_SDA [CS42L51_SDA] {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to uSD_CMD {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to OE [OE_IS66WV51216EBLL] {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A17 [A17_IS66WV51216EBLL] - {PG_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to UART1_RTS [STMOD+_UART] {NC, NC, 0} }; @@ -317,16 +317,16 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STMOD_PWM {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to QSPI_BK1_IO3 [MX25R6435FM2IL0_SIO3] - {PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK1_IO3 [MX25R6435FM2IL0_SIO3] + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to QSPI_BK1_IO3 [MX25R6435FM2IL0_SIO3] {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTGFS_DM {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to ARD_D11 {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to I2C1_SDA {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED1 - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LED1 + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LED1 {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PSRAM_A16 [A16_IS66WV51216EBLL] - {PG_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to PSRAM_A15 [A15_IS66WV51216EBLL] + {PG_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to PSRAM_A15 [A15_IS66WV51216EBLL] {PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to UART1_CTS [STMOD+_UART] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h index 1c22a42a89..371a5c249e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h @@ -47,26 +47,26 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, + PA_0_ALT0 = PA_0 | ALT0, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -75,71 +75,71 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, - PB_10_ALT0 = PB_10|ALT0, + PB_10_ALT0 = PB_10 | ALT0, PB_11 = 0x1B, - PB_11_ALT0 = PB_11|ALT0, + PB_11_ALT0 = PB_11 | ALT0, PB_12 = 0x1C, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -253,8 +253,8 @@ typedef enum { A1 = PC_1, A2 = PC_3, A3 = PF_10, - A4 = PA_1, - A5 = PC_0, + A4 = PA_1, + A5 = PC_0, D0 = PG_8, D1 = PG_7, D2 = PG_13, @@ -291,11 +291,11 @@ typedef enum { LED4 = LED1, USER_BUTTON = PC_13, // Joystick Center BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port SERIAL_RX = STDIO_UART_RX, // Virtual Com Port USBTX = STDIO_UART_TX, // Virtual Com Port USBRX = STDIO_UART_RX, // Virtual Com Port - I2C_SCL = D15, + I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, SPI_MISO = D12, @@ -303,7 +303,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -313,13 +313,13 @@ typedef enum { USB_OTG_FS_SOF_ALT0 = PA_8, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c index e8d5be0049..2943dc51cc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -226,10 +226,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c index b9dc0febcf..c1d0424246 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c @@ -251,19 +251,19 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Only STM32L496ZG, not STM32L496ZG-P - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Only STM32L496ZG, not STM32L496ZG-P + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_7, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {NC, NC, 0} }; @@ -271,20 +271,20 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue] - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Only STM32L496ZG, not STM32L496ZG-P - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_8, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX + {PG_8, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX {PG_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SMPS_V1 [D0_D1_ST1PS02D1QTR] {NC, NC, 0} }; @@ -295,15 +295,15 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red] {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] + {PG_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_PowerSwitchOn [STMPS2151STR_EN] {PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SMPS_PG [PG_ST1PS02D1QTR] {NC, NC, 0} }; @@ -311,16 +311,16 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD2 [Blue] {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PG_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_OverCurrent [STMPS2151STR_FAULT] + {PG_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_OverCurrent [STMPS2151STR_FAULT] {PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SMPS_EN [EN_ST1PS20D1QTR] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h index 825bc26d88..e828b5e57e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h @@ -47,26 +47,26 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0_ALT0 = PA_0|ALT0, + PA_0_ALT0 = PA_0 | ALT0, PA_1 = 0x01, - PA_1_ALT0 = PA_1|ALT0, - PA_1_ALT1 = PA_1|ALT1, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, PA_2 = 0x02, - PA_2_ALT0 = PA_2|ALT0, - PA_2_ALT1 = PA_2|ALT1, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, PA_3 = 0x03, - PA_3_ALT0 = PA_3|ALT0, - PA_3_ALT1 = PA_3|ALT1, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, PA_4 = 0x04, - PA_4_ALT0 = PA_4|ALT0, + PA_4_ALT0 = PA_4 | ALT0, PA_5 = 0x05, - PA_5_ALT0 = PA_5|ALT0, + PA_5_ALT0 = PA_5 | ALT0, PA_6 = 0x06, - PA_6_ALT0 = PA_6|ALT0, + PA_6_ALT0 = PA_6 | ALT0, PA_7 = 0x07, - PA_7_ALT0 = PA_7|ALT0, - PA_7_ALT1 = PA_7|ALT1, - PA_7_ALT2 = PA_7|ALT2, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -75,71 +75,71 @@ typedef enum { PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, - PA_15_ALT0 = PA_15|ALT0, + PA_15_ALT0 = PA_15 | ALT0, PB_0 = 0x10, - PB_0_ALT0 = PB_0|ALT0, - PB_0_ALT1 = PB_0|ALT1, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, PB_1 = 0x11, - PB_1_ALT0 = PB_1|ALT0, - PB_1_ALT1 = PB_1|ALT1, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, PB_2 = 0x12, PB_3 = 0x13, - PB_3_ALT0 = PB_3|ALT0, + PB_3_ALT0 = PB_3 | ALT0, PB_4 = 0x14, - PB_4_ALT0 = PB_4|ALT0, + PB_4_ALT0 = PB_4 | ALT0, PB_5 = 0x15, - PB_5_ALT0 = PB_5|ALT0, + PB_5_ALT0 = PB_5 | ALT0, PB_6 = 0x16, - PB_6_ALT0 = PB_6|ALT0, + PB_6_ALT0 = PB_6 | ALT0, PB_7 = 0x17, - PB_7_ALT0 = PB_7|ALT0, + PB_7_ALT0 = PB_7 | ALT0, PB_8 = 0x18, - PB_8_ALT0 = PB_8|ALT0, + PB_8_ALT0 = PB_8 | ALT0, PB_9 = 0x19, - PB_9_ALT0 = PB_9|ALT0, + PB_9_ALT0 = PB_9 | ALT0, PB_10 = 0x1A, - PB_10_ALT0 = PB_10|ALT0, + PB_10_ALT0 = PB_10 | ALT0, PB_11 = 0x1B, - PB_11_ALT0 = PB_11|ALT0, + PB_11_ALT0 = PB_11 | ALT0, PB_12 = 0x1C, PB_13 = 0x1D, - PB_13_ALT0 = PB_13|ALT0, + PB_13_ALT0 = PB_13 | ALT0, PB_14 = 0x1E, - PB_14_ALT0 = PB_14|ALT0, - PB_14_ALT1 = PB_14|ALT1, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, PB_15 = 0x1F, - PB_15_ALT0 = PB_15|ALT0, - PB_15_ALT1 = PB_15|ALT1, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, PC_0 = 0x20, - PC_0_ALT0 = PC_0|ALT0, - PC_0_ALT1 = PC_0|ALT1, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, PC_1 = 0x21, - PC_1_ALT0 = PC_1|ALT0, - PC_1_ALT1 = PC_1|ALT1, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, PC_2 = 0x22, - PC_2_ALT0 = PC_2|ALT0, - PC_2_ALT1 = PC_2|ALT1, + PC_2_ALT0 = PC_2 | ALT0, + PC_2_ALT1 = PC_2 | ALT1, PC_3 = 0x23, - PC_3_ALT0 = PC_3|ALT0, - PC_3_ALT1 = PC_3|ALT1, + PC_3_ALT0 = PC_3 | ALT0, + PC_3_ALT1 = PC_3 | ALT1, PC_4 = 0x24, - PC_4_ALT0 = PC_4|ALT0, + PC_4_ALT0 = PC_4 | ALT0, PC_5 = 0x25, - PC_5_ALT0 = PC_5|ALT0, + PC_5_ALT0 = PC_5 | ALT0, PC_6 = 0x26, - PC_6_ALT0 = PC_6|ALT0, + PC_6_ALT0 = PC_6 | ALT0, PC_7 = 0x27, - PC_7_ALT0 = PC_7|ALT0, + PC_7_ALT0 = PC_7 | ALT0, PC_8 = 0x28, - PC_8_ALT0 = PC_8|ALT0, + PC_8_ALT0 = PC_8 | ALT0, PC_9 = 0x29, - PC_9_ALT0 = PC_9|ALT0, + PC_9_ALT0 = PC_9 | ALT0, PC_10 = 0x2A, - PC_10_ALT0 = PC_10|ALT0, + PC_10_ALT0 = PC_10 | ALT0, PC_11 = 0x2B, - PC_11_ALT0 = PC_11|ALT0, + PC_11_ALT0 = PC_11 | ALT0, PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, @@ -189,7 +189,7 @@ typedef enum { PF_7 = 0x57, PF_8 = 0x58, PF_9 = 0x59, - PF_9_ALT0 = PF_9|ALT0, + PF_9_ALT0 = PF_9 | ALT0, PF_10 = 0x5A, PF_11 = 0x5B, PF_12 = 0x5C, @@ -227,8 +227,8 @@ typedef enum { A1 = PC_0, A2 = PC_3, A3 = PC_1, - A4 = PC_4, - A5 = PC_5, + A4 = PC_4, + A5 = PC_5, D0 = PD_9, D1 = PD_8, D2 = PF_15, @@ -267,11 +267,11 @@ typedef enum { // Standardized button names BUTTON1 = USER_BUTTON, - SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port SERIAL_RX = STDIO_UART_RX, // Virtual Com Port USBTX = STDIO_UART_TX, // Virtual Com Port USBRX = STDIO_UART_RX, // Virtual Com Port - I2C_SCL = D15, + I2C_SCL = D15, I2C_SDA = D14, SPI_MOSI = D11, SPI_MISO = D12, @@ -279,7 +279,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, -/**** USB pins ****/ + /**** USB pins ****/ USB_OTG_FS_DM = PA_11, USB_OTG_FS_DP = PA_12, USB_OTG_FS_ID = PA_10, @@ -289,13 +289,13 @@ typedef enum { USB_OTG_FS_SOF_ALT0 = PA_14, USB_OTG_FS_VBUS = PA_9, -/**** OSCILLATOR pins ****/ + /**** OSCILLATOR pins ****/ RCC_OSC32_IN = PC_14, RCC_OSC32_OUT = PC_15, RCC_OSC_IN = PH_0, RCC_OSC_OUT = PH_1, -/**** DEBUG pins ****/ + /**** DEBUG pins ****/ SYS_JTCK_SWCLK = PA_14, SYS_JTDI = PA_15, SYS_JTDO_SWO = PB_3, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c index e8d5be0049..2943dc51cc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c @@ -72,7 +72,7 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ @@ -126,7 +126,7 @@ void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSI) /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI()==0) + if (SetSysClock_PLL_HSI() == 0) #endif { #if ((CLOCK_SOURCE) & USE_PLL_MSI) @@ -134,7 +134,7 @@ void SetSysClock(void) if (SetSysClock_PLL_MSI() == 0) #endif { - while(1) { + while (1) { MBED_ASSERT(1); } } @@ -226,10 +226,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // Output clock on MCO1 pin(PA8) for debugging purpose #if DEBUG_MCO == 2 - if (bypass == 0) - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - else - HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + if (bypass == 0) { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + } else { + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + } #endif return 1; // OK diff --git a/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c index 92386ab594..131e994c56 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c @@ -39,7 +39,8 @@ static int channel1_used = 0; static int channel2_used = 0; -void analogout_init(dac_t *obj, PinName pin) { +void analogout_init(dac_t *obj, PinName pin) +{ DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object @@ -77,7 +78,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->handle.Instance = DAC; obj->handle.State = HAL_DAC_STATE_RESET; - if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { + if (HAL_DAC_Init(&obj->handle) != HAL_OK) { error("HAL_DAC_Init failed"); } @@ -100,11 +101,16 @@ void analogout_init(dac_t *obj, PinName pin) { analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) { +void analogout_free(dac_t *obj) +{ // Reset DAC and disable clock - if (obj->channel == DAC_CHANNEL_1) channel1_used = 0; + if (obj->channel == DAC_CHANNEL_1) { + channel1_used = 0; + } #if defined(DAC_CHANNEL_2) - if (obj->channel == DAC_CHANNEL_2) channel2_used = 0; + if (obj->channel == DAC_CHANNEL_2) { + channel2_used = 0; + } #endif if ((channel1_used == 0) && (channel2_used == 0)) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c index 4904e93317..ff6417f7bf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c @@ -137,7 +137,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return -1; } - /* Clear OPTVERR bit set on virgin samples */ + /* Clear OPTVERR bit set on virgin samples */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); /* Get the 1st page to erase */ FirstPage = GetPage(address); @@ -176,7 +176,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) * @return 0 for success, -1 for error */ int32_t flash_program_page(flash_t *obj, uint32_t address, - const uint8_t *data, uint32_t size) + const uint8_t *data, uint32_t size) { uint32_t StartAddress = 0; int32_t status = 0; @@ -202,7 +202,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, if ((uint32_t) data % 4 != 0) { volatile uint64_t data64; while ((address < (StartAddress + size)) && (status == 0)) { - for (uint8_t i =0; i < 8; i++) { + for (uint8_t i = 0; i < 8; i++) { *(((uint8_t *) &data64) + i) = *(data + i); } @@ -217,7 +217,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, } else { /* case where data is aligned, so let's avoid any copy */ while ((address < (StartAddress + size)) && (status == 0)) { if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, - *((uint64_t*) data)) + *((uint64_t *) data)) == HAL_OK) { address = address + 8; data = data + 8; @@ -238,7 +238,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, * @param address The sector starting address * @return The size of a sector */ -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ /* considering 1 sector = 1 page */ if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; @@ -253,7 +254,8 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { * @param address The page starting address * @return The size of a page */ -uint32_t flash_get_page_size(const flash_t *obj) { +uint32_t flash_get_page_size(const flash_t *obj) +{ /* Page size is the minimum programable size, which 8 bytes */ return 8; } @@ -263,7 +265,8 @@ uint32_t flash_get_page_size(const flash_t *obj) { * @param obj The flash object * @return The start address for the flash region */ -uint32_t flash_get_start_address(const flash_t *obj) { +uint32_t flash_get_start_address(const flash_t *obj) +{ return FLASH_BASE; } @@ -272,7 +275,8 @@ uint32_t flash_get_start_address(const flash_t *obj) { * @param obj The flash object * @return The flash region size */ -uint32_t flash_get_size(const flash_t *obj) { +uint32_t flash_get_size(const flash_t *obj) +{ return FLASH_SIZE; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c index 5a92e60288..c80d087a73 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c +++ b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c @@ -3,7 +3,7 @@ * @file l4_retarget.c * @author MCD Application Team * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for STM32L475xG - ****************************************************************************** + ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2018 STMicroelectronics

@@ -30,8 +30,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ #if (defined(TWO_RAM_REGIONS) && defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION)) #include #include "stm32l4xx.h" @@ -41,10 +41,10 @@ extern uint32_t __mbed_krbs_start; #define STM32L4_HEAP_ALIGN 32 #define STM32L4_ALIGN_UP(X, ALIGN) (((X) + (ALIGN) - 1) & ~((ALIGN) - 1)) /** - * The default implementation of _sbrk() (in platform/mbed_retarget.cpp) for GCC_ARM requires one-region model (heap and - * stack share one region), which doesn't fit two-region model (heap and stack are two distinct regions), for example, - * STM32L475xG locates heap on SRAM1 and stack on SRAM2. - * Define __wrap__sbrk() to override the default _sbrk(). It is expected to get called through gcc + * The default implementation of _sbrk() (in platform/mbed_retarget.cpp) for GCC_ARM requires one-region model (heap and + * stack share one region), which doesn't fit two-region model (heap and stack are two distinct regions), for example, + * STM32L475xG locates heap on SRAM1 and stack on SRAM2. + * Define __wrap__sbrk() to override the default _sbrk(). It is expected to get called through gcc * hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk(). */ void *__wrap__sbrk(int incr) @@ -52,14 +52,14 @@ void *__wrap__sbrk(int incr) static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start; uint32_t heap_ind_old = STM32L4_ALIGN_UP(heap_ind, STM32L4_HEAP_ALIGN); uint32_t heap_ind_new = STM32L4_ALIGN_UP(heap_ind_old + incr, STM32L4_HEAP_ALIGN); - + if (heap_ind_new > &__mbed_krbs_start) { errno = ENOMEM; - return (void *) -1; - } - + return (void *) - 1; + } + heap_ind = heap_ind_new; - + return (void *) heap_ind_old; } #endif /* GCC_ARM toolchain && TWO_RAM_REGIONS*/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/pin_device.h b/targets/TARGET_STM/TARGET_STM32L4/pin_device.h index b45c56d2ac..d612b5def2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32L4/pin_device.h @@ -56,14 +56,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3 } } -static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) +static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum) { uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; - if (STM_PIN(pin) > 7) + if (STM_PIN(pin) > 7) { LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum); - else + } else { LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum); + } } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c index 708d30534a..d4a805ec19 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/pwmout_device.c @@ -33,8 +33,7 @@ #ifdef DEVICE_PWMOUT -const pwm_apb_map_t pwm_apb_map_table[] = -{ +const pwm_apb_map_t pwm_apb_map_table[] = { #if defined(TIM2_BASE) {PWM_2, PWMOUT_ON_APB1}, #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index ac9bc85d1f..6ea4595017 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -33,11 +33,11 @@ #include "serial_api_hal.h" #if defined (TARGET_STM32L432xC) - #define UART_NUM (3) +#define UART_NUM (3) #elif defined (TARGET_STM32L433xC) - #define UART_NUM (4) +#define UART_NUM (4) #else - #define UART_NUM (6) // max value (TARGET_STM32L475xG / TARGET_STM32L476xG / TARGET_STM32L486xG / TARGET_STM32L496xG) +#define UART_NUM (6) // max value (TARGET_STM32L475xG / TARGET_STM32L476xG / TARGET_STM32L486xG / TARGET_STM32L496xG) #endif uint32_t serial_irq_ids[UART_NUM] = {0}; @@ -57,7 +57,7 @@ static void uart_irq(UARTName uart_name) int8_t id = get_uart_index(uart_name); if (id >= 0) { - UART_HandleTypeDef * huart = &uart_handlers[id]; + UART_HandleTypeDef *huart = &uart_handlers[id]; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) { @@ -124,7 +124,7 @@ static void lpuart1_irq(void) void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { struct serial_s *obj_s = SERIAL_S(obj); - + irq_handler = handler; serial_irq_ids[obj_s->index] = id; } @@ -259,7 +259,7 @@ void serial_break_set(serial_t *obj) * LOCAL HELPER FUNCTIONS ******************************************************************************/ -/** +/** * Configure the TX buffer for an asynchronous write serial transaction * * @param obj The serial object. @@ -279,7 +279,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t obj->tx_buff.length = tx_length; obj->tx_buff.pos = 0; } - + /** * Configure the RX buffer for an asynchronous write serial transaction * @@ -301,7 +301,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t obj->rx_buff.pos = 0; } -/** +/** * Configure events * * @param obj The serial object @@ -309,9 +309,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t * @param enable Set to non-zero to enable events, or zero to disable them */ static void serial_enable_event(serial_t *obj, int event, uint8_t enable) -{ +{ struct serial_s *obj_s = SERIAL_S(obj); - + // Shouldn't have to enable interrupt here, just need to keep track of the requested events. if (enable) { obj_s->events |= event; @@ -373,7 +373,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * MBED API FUNCTIONS ******************************************************************************/ -/** +/** * Begin asynchronous TX transfer. The used buffer is specified in the serial * object, tx_buff * @@ -387,28 +387,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) * @return Returns number of data transfered, or 0 otherwise */ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) -{ +{ // TODO: DMA usage is currently ignored (void) hint; - + // Check buffer is ok - MBED_ASSERT(tx != (void*)0); + MBED_ASSERT(tx != (void *)0); MBED_ASSERT(tx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef * huart = &uart_handlers[obj_s->index]; + UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; if (tx_length == 0) { return 0; } - + // Set up buffer serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); - + // Set up events serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events serial_enable_event(obj, event, 1); // Set only the wanted events - + // Enable interrupt IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); NVIC_ClearPendingIRQ(irq_n); @@ -418,14 +418,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(irq_n); // the following function will enable UART_IT_TXE and error interrupts - if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) { + if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) { return 0; } - + return tx_length; } -/** +/** * Begin asynchronous RX transfer (enable interrupt for data collecting) * The used buffer is specified in the serial object, rx_buff * @@ -446,18 +446,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt /* Sanity check arguments */ MBED_ASSERT(obj); - MBED_ASSERT(rx != (void*)0); + MBED_ASSERT(rx != (void *)0); MBED_ASSERT(rx_width == 8); // support only 8b width - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); serial_enable_event(obj, event, 1); - + // set CharMatch obj->char_match = char_match; - + serial_rx_buffer_set(obj, rx, rx_length, rx_width); IRQn_Type irq_n = serial_get_irq_n(obj_s->uart); @@ -467,8 +467,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_SetVector(irq_n, (uint32_t)handler); NVIC_EnableIRQ(irq_n); - // following HAL function will enable the RXNE interrupt + error interrupts - HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length); + // following HAL function will enable the RXNE interrupt + error interrupts + HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length); } /** @@ -480,10 +480,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt uint8_t serial_tx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0); } @@ -496,20 +496,22 @@ uint8_t serial_tx_active(serial_t *obj) uint8_t serial_rx_active(serial_t *obj) { MBED_ASSERT(obj); - + struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0); } -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); -} + } } -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { @@ -531,49 +533,49 @@ int serial_irq_handler_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + volatile int return_event = 0; - uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer); + uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); uint8_t i = 0; - + // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) { // Return event SERIAL_EVENT_TX_COMPLETE if requested - if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) { + if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) { return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events); } } } - + // Handle error events if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) { return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events); } -} + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) { return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events); } } - + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events); } } - + HAL_UART_IRQHandler(huart); - + // Abort if an error occurs if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || - (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || - (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } - + //RX PART if (huart->RxXferSize != 0) { obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount; @@ -581,7 +583,7 @@ int serial_irq_handler_asynch(serial_t *obj) if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events); } - + // Check if char_match is present if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (buf != NULL) { @@ -595,11 +597,11 @@ int serial_irq_handler_asynch(serial_t *obj) } } } - - return return_event; + + return return_event; } -/** +/** * Abort the ongoing TX transaction. It disables the enabled interupt for TX and * flush TX hardware buffer if TX FIFO is used * @@ -609,17 +611,17 @@ void serial_tx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - + // reset states huart->TxXferCount = 0; // update handle state - if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) { huart->gState = HAL_UART_STATE_BUSY_RX; } else { huart->gState = HAL_UART_STATE_READY; @@ -636,20 +638,20 @@ void serial_rx_abort_asynch(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - + // disable interrupts __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - + // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear errors flag - + // reset states huart->RxXferCount = 0; // update handle state - if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { huart->RxState = HAL_UART_STATE_BUSY_TX; } else { huart->RxState = HAL_UART_STATE_READY; @@ -679,9 +681,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts); MBED_ASSERT(obj_s->uart != (UARTName)NC); - if(type == FlowControlNone) { + if (type == FlowControlNone) { // Disable hardware flow control - obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; + obj_s->hw_flow_ctl = UART_HWCONTROL_NONE; } if (type == FlowControlRTS) { // Enable RTS @@ -711,7 +713,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi // Enable the pin for RTS function pinmap_pinout(rxflow, PinMap_UART_RTS); } - + init_uart(obj); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/spi_api.c b/targets/TARGET_STM/TARGET_STM32L4/spi_api.c index d383c9d31f..8e5259e9ac 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32L4/spi_api.c @@ -38,20 +38,21 @@ #include "PeripheralPins.h" #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif /* * Only the frequency is managed in the family specific part * the rest of SPI management is common to all STM32 families */ -int spi_get_clock_freq(spi_t *obj) { +int spi_get_clock_freq(spi_t *obj) +{ struct spi_s *spiobj = SPI_S(obj); - int spi_hz = 0; + int spi_hz = 0; - /* Get source clock depending on SPI instance */ + /* Get source clock depending on SPI instance */ switch ((int)spiobj->spi) { case SPI_1: /* SPI_1. Source CLK is PCKL2 */ @@ -65,7 +66,7 @@ int spi_get_clock_freq(spi_t *obj) { spi_hz = HAL_RCC_GetPCLK1Freq(); break; default: - error("CLK: SPI instance not set"); + error("CLK: SPI instance not set"); break; } return spi_hz; diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 246f5d1971..ecada7bb4b 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -45,7 +45,7 @@ void can_init(can_t *obj, PinName rd, PinName td) can_init_freq(obj, rd, td, 100000); } -void can_init_freq (can_t *obj, PinName rd, PinName td, int hz) +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) { CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); @@ -278,14 +278,14 @@ int can_write(can_t *obj, CAN_Message msg, int cc) } else if ((can->TSR & CAN_TSR_TME2) == CAN_TSR_TME2) { transmitmailbox = 2; } else { - return 0; + return 0; } can->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (!(msg.format)) { - can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | (msg.type << 1)); + can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 21) | (msg.type << 1)); } else { - can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | (msg.type << 1)); + can->sTxMailBox[transmitmailbox].TIR |= ((msg.id << 3) | CAN_ID_EXT | (msg.type << 1)); } /* Set up the DLC */ @@ -294,13 +294,13 @@ int can_write(can_t *obj, CAN_Message msg, int cc) /* Set up the data field */ can->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)msg.data[3] << 24) | - ((uint32_t)msg.data[2] << 16) | - ((uint32_t)msg.data[1] << 8) | - ((uint32_t)msg.data[0])); + ((uint32_t)msg.data[2] << 16) | + ((uint32_t)msg.data[1] << 8) | + ((uint32_t)msg.data[0])); can->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)msg.data[7] << 24) | - ((uint32_t)msg.data[6] << 16) | - ((uint32_t)msg.data[5] << 8) | - ((uint32_t)msg.data[4])); + ((uint32_t)msg.data[6] << 16) | + ((uint32_t)msg.data[5] << 8) | + ((uint32_t)msg.data[4])); /* Request transmission */ can->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; @@ -382,7 +382,7 @@ void can_monitor(can_t *obj, int silent) { CanMode mode = MODE_NORMAL; /* Update current state w/ or w/o silent */ - if(silent) { + if (silent) { switch (obj->CanHandle.Init.Mode) { case CAN_MODE_LOOPBACK: case CAN_MODE_SILENT_LOOPBACK: diff --git a/targets/TARGET_STM/gpio_api.c b/targets/TARGET_STM/gpio_api.c index 60d300d32c..02e6a5ca16 100644 --- a/targets/TARGET_STM/gpio_api.c +++ b/targets/TARGET_STM/gpio_api.c @@ -36,7 +36,8 @@ extern const uint32_t ll_pin_defines[16]; // Enable GPIO clock and return GPIO base address -GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) { +GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) +{ uint32_t gpio_add = 0; switch (port_idx) { case PortA: @@ -112,7 +113,8 @@ GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) { return (GPIO_TypeDef *) gpio_add; } -uint32_t gpio_set(PinName pin) { +uint32_t gpio_set(PinName pin) +{ MBED_ASSERT(pin != (PinName)NC); pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -121,7 +123,8 @@ uint32_t gpio_set(PinName pin) { } -void gpio_init(gpio_t *obj, PinName pin) { +void gpio_init(gpio_t *obj, PinName pin) +{ obj->pin = pin; if (pin == (PinName)NC) { return; @@ -145,11 +148,13 @@ void gpio_init(gpio_t *obj, PinName pin) { #endif } -void gpio_mode(gpio_t *obj, PinMode mode) { +void gpio_mode(gpio_t *obj, PinMode mode) +{ pin_mode(obj->pin, mode); } -inline void gpio_dir(gpio_t *obj, PinDirection direction) { +inline void gpio_dir(gpio_t *obj, PinDirection direction) +{ if (direction == PIN_INPUT) { LL_GPIO_SetPinMode(obj->gpio, obj->ll_pin, LL_GPIO_MODE_INPUT); } else { diff --git a/targets/TARGET_STM/gpio_irq_api.c b/targets/TARGET_STM/gpio_irq_api.c index f9c1f57990..522ee94034 100644 --- a/targets/TARGET_STM/gpio_irq_api.c +++ b/targets/TARGET_STM/gpio_irq_api.c @@ -43,7 +43,7 @@ typedef struct gpio_channel { uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance - GPIO_TypeDef* channel_gpio[MAX_PIN_LINE]; // base address of gpio port group + GPIO_TypeDef *channel_gpio[MAX_PIN_LINE]; // base address of gpio port group uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group } gpio_channel_t; @@ -168,7 +168,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 gpio_channel_t *gpio_channel; uint32_t gpio_idx; - if (pin == NC) return -1; + if (pin == NC) { + return -1; + } /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); diff --git a/targets/TARGET_STM/hal_tick_16b.c b/targets/TARGET_STM/hal_tick_16b.c index b8c4dc6fb0..32d67c96b8 100644 --- a/targets/TARGET_STM/hal_tick_16b.c +++ b/targets/TARGET_STM/hal_tick_16b.c @@ -25,7 +25,8 @@ volatile uint32_t PreviousVal = 0; void us_ticker_irq_handler(void); #if defined(TARGET_STM32F0) -void timer_update_irq_handler(void) { +void timer_update_irq_handler(void) +{ #else void timer_irq_handler(void) { @@ -45,7 +46,7 @@ void timer_oc_irq_handler(void) if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC1) == SET) { __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); - us_ticker_irq_handler(); + us_ticker_irq_handler(); } } } diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index b757e3b005..7ce17c692d 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -52,14 +52,14 @@ #endif #if DEVICE_I2C_ASYNCH - #define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) +#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) #else - #define I2C_S(obj) (struct i2c_s *) (obj) +#define I2C_S(obj) (struct i2c_s *) (obj) #endif /* Family specific description for I2C */ #define I2C_NUM (5) -static I2C_HandleTypeDef* i2c_handles[I2C_NUM]; +static I2C_HandleTypeDef *i2c_handles[I2C_NUM]; /* Timeout values are based on core clock and I2C clock. The BYTE_TIMEOUT is computed as twice the number of cycles it would @@ -75,7 +75,7 @@ static I2C_HandleTypeDef* i2c_handles[I2C_NUM]; #define BYTE_TIMEOUT_US ((SystemCoreClock / obj_s->hz) * 3 * 10) /* Timeout values for flags and events waiting loops. These timeouts are not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. + not remain stuck if the I2C communication is corrupted. */ #define FLAG_TIMEOUT ((int)0x1000) @@ -84,7 +84,7 @@ static I2C_HandleTypeDef* i2c_handles[I2C_NUM]; #if defined(I2C1_BASE) static void i2c1_irq(void) { - I2C_HandleTypeDef * handle = i2c_handles[0]; + I2C_HandleTypeDef *handle = i2c_handles[0]; HAL_I2C_EV_IRQHandler(handle); HAL_I2C_ER_IRQHandler(handle); } @@ -92,7 +92,7 @@ static void i2c1_irq(void) #if defined(I2C2_BASE) static void i2c2_irq(void) { - I2C_HandleTypeDef * handle = i2c_handles[1]; + I2C_HandleTypeDef *handle = i2c_handles[1]; HAL_I2C_EV_IRQHandler(handle); HAL_I2C_ER_IRQHandler(handle); } @@ -100,7 +100,7 @@ static void i2c2_irq(void) #if defined(I2C3_BASE) static void i2c3_irq(void) { - I2C_HandleTypeDef * handle = i2c_handles[2]; + I2C_HandleTypeDef *handle = i2c_handles[2]; HAL_I2C_EV_IRQHandler(handle); HAL_I2C_ER_IRQHandler(handle); } @@ -108,7 +108,7 @@ static void i2c3_irq(void) #if defined(I2C4_BASE) static void i2c4_irq(void) { - I2C_HandleTypeDef * handle = i2c_handles[3]; + I2C_HandleTypeDef *handle = i2c_handles[3]; HAL_I2C_EV_IRQHandler(handle); HAL_I2C_ER_IRQHandler(handle); } @@ -116,13 +116,14 @@ static void i2c4_irq(void) #if defined(FMPI2C1_BASE) static void i2c5_irq(void) { - I2C_HandleTypeDef * handle = i2c_handles[4]; + I2C_HandleTypeDef *handle = i2c_handles[4]; HAL_I2C_EV_IRQHandler(handle); HAL_I2C_ER_IRQHandler(handle); } #endif -void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) { +void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) +{ struct i2c_s *obj_s = I2C_S(obj); IRQn_Type irq_event_n = obj_s->event_i2cIRQ; IRQn_Type irq_error_n = obj_s->error_i2cIRQ; @@ -149,7 +150,8 @@ void i2c_ev_err_enable(i2c_t *obj, uint32_t handler) { NVIC_EnableIRQ(irq_error_n); } -void i2c_ev_err_disable(i2c_t *obj) { +void i2c_ev_err_disable(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); IRQn_Type irq_event_n = obj_s->event_i2cIRQ; IRQn_Type irq_error_n = obj_s->error_i2cIRQ; @@ -196,7 +198,8 @@ uint32_t i2c_get_irq_handler(i2c_t *obj) return handler; } -void i2c_hw_reset(i2c_t *obj) { +void i2c_hw_reset(i2c_t *obj) +{ int timeout; struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); @@ -251,11 +254,12 @@ void i2c_sw_reset(i2c_t *obj) * - Write PE=1. */ handle->Instance->CR1 &= ~I2C_CR1_PE; - while(handle->Instance->CR1 & I2C_CR1_PE); + while (handle->Instance->CR1 & I2C_CR1_PE); handle->Instance->CR1 |= I2C_CR1_PE; } -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ struct i2c_s *obj_s = I2C_S(obj); @@ -323,12 +327,13 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { // I2C configuration // Default hz value used for timeout computation - if(!obj_s->hz) - obj_s->hz = 100000; // 100 kHz per default + if (!obj_s->hz) { + obj_s->hz = 100000; // 100 kHz per default + } // Reset to clear pending flags if any i2c_hw_reset(obj); - i2c_frequency(obj, obj_s->hz ); + i2c_frequency(obj, obj_s->hz); #if DEVICE_I2CSLAVE // I2C master by default @@ -413,7 +418,7 @@ void i2c_frequency(i2c_t *obj, int hz) #ifdef I2C_ANALOGFILTER_ENABLE /* Enable the Analog I2C Filter */ - HAL_I2CEx_ConfigAnalogFilter(handle,I2C_ANALOGFILTER_ENABLE); + HAL_I2CEx_ConfigAnalogFilter(handle, I2C_ANALOGFILTER_ENABLE); #endif // I2C configuration @@ -429,20 +434,22 @@ void i2c_frequency(i2c_t *obj, int hz) obj_s->hz = hz; } -i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c){ +i2c_t *get_i2c_obj(I2C_HandleTypeDef *hi2c) +{ /* Aim of the function is to get i2c_s pointer using hi2c pointer */ /* Highly inspired from magical linux kernel's "container_of" */ /* (which was not directly used since not compatible with IAR toolchain) */ struct i2c_s *obj_s; i2c_t *obj; - obj_s = (struct i2c_s *)( (char *)hi2c - offsetof(struct i2c_s,handle)); - obj = (i2c_t *)( (char *)obj_s - offsetof(i2c_t,i2c)); + obj_s = (struct i2c_s *)((char *)hi2c - offsetof(struct i2c_s, handle)); + obj = (i2c_t *)((char *)obj_s - offsetof(i2c_t, i2c)); return (obj); } -void i2c_reset(i2c_t *obj) { +void i2c_reset(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); /* As recommended in i2c_api.h, mainly send stop */ i2c_stop(obj); @@ -456,7 +463,8 @@ void i2c_reset(i2c_t *obj) { * There are 2 different IPs version that need to be supported */ #ifdef I2C_IP_VERSION_V1 -int i2c_start(i2c_t *obj) { +int i2c_start(i2c_t *obj) +{ int timeout; struct i2c_s *obj_s = I2C_S(obj); @@ -488,7 +496,8 @@ int i2c_start(i2c_t *obj) { return 0; } -int i2c_stop(i2c_t *obj) { +int i2c_stop(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_TypeDef *i2c = (I2C_TypeDef *)obj_s->i2c; @@ -498,13 +507,15 @@ int i2c_stop(i2c_t *obj) { /* In case of mixed usage of the APIs (unitary + SYNC) * re-init HAL state */ - if(obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) - i2c_init(obj, obj_s->sda, obj_s->scl); + if (obj_s->XferOperation != I2C_FIRST_AND_LAST_FRAME) { + i2c_init(obj, obj_s->sda, obj_s->scl); + } return 0; } -int i2c_byte_read(i2c_t *obj, int last) { +int i2c_byte_read(i2c_t *obj, int last) +{ int timeout; struct i2c_s *obj_s = I2C_S(obj); @@ -529,7 +540,8 @@ int i2c_byte_read(i2c_t *obj, int last) { return (int)handle->Instance->DR; } -int i2c_byte_write(i2c_t *obj, int data) { +int i2c_byte_write(i2c_t *obj, int data) +{ int timeout; struct i2c_s *obj_s = I2C_S(obj); @@ -541,30 +553,31 @@ int i2c_byte_write(i2c_t *obj, int data) { timeout = FLAG_TIMEOUT; while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_TXE) == RESET) && (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BTF) == RESET) && - (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) { + (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) == RESET)) { if ((timeout--) == 0) { return 2; } } - if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET) - { - __HAL_I2C_CLEAR_ADDRFLAG(handle); - } + if (__HAL_I2C_GET_FLAG(handle, I2C_FLAG_ADDR) != RESET) { + __HAL_I2C_CLEAR_ADDRFLAG(handle); + } return 1; } #endif //I2C_IP_VERSION_V1 #ifdef I2C_IP_VERSION_V2 -int i2c_start(i2c_t *obj) { +int i2c_start(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); /* This I2C IP doesn't */ obj_s->pending_start = 1; return 0; } -int i2c_stop(i2c_t *obj) { +int i2c_stop(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int timeout = FLAG_TIMEOUT; @@ -609,7 +622,8 @@ int i2c_stop(i2c_t *obj) { return 0; } -int i2c_byte_read(i2c_t *obj, int last) { +int i2c_byte_read(i2c_t *obj, int last) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int timeout = FLAG_TIMEOUT; @@ -654,7 +668,8 @@ int i2c_byte_read(i2c_t *obj, int last) { return data; } -int i2c_byte_write(i2c_t *obj, int data) { +int i2c_byte_write(i2c_t *obj, int data) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int timeout = FLAG_TIMEOUT; @@ -669,10 +684,10 @@ int i2c_byte_write(i2c_t *obj, int data) { //* First byte after the start is the address */ tmpreg |= (uint32_t)((uint32_t)data & I2C_CR2_SADD); if (data & 0x01) { - tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN; + tmpreg |= I2C_CR2_START | I2C_CR2_RD_WRN; } else { - tmpreg |= I2C_CR2_START; - tmpreg &= ~I2C_CR2_RD_WRN; + tmpreg |= I2C_CR2_START; + tmpreg &= ~I2C_CR2_RD_WRN; } /* Disable reload first to use it later */ tmpreg &= ~I2C_CR2_RELOAD; @@ -697,9 +712,9 @@ int i2c_byte_write(i2c_t *obj, int data) { } /* Enable reload mode as we don't know how many bytes will eb sent */ tmpreg |= I2C_CR2_RELOAD; - /* Set transfer size to 1 */ + /* Set transfer size to 1 */ tmpreg |= (I2C_CR2_NBYTES & (1 << 16)); - /* Set the prepared configuration */ + /* Set the prepared configuration */ handle->Instance->CR2 = tmpreg; /* Prepare next write */ timeout = FLAG_TIMEOUT; @@ -719,7 +734,8 @@ int i2c_byte_write(i2c_t *obj, int data) { /* * SYNC APIS */ -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int count = I2C_ERROR_BUS_BUSY, ret = 0; @@ -729,37 +745,39 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; uint32_t op2 = I2C_LAST_FRAME; if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { - if (stop) + if (stop) { obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME; - else + } else { obj_s->XferOperation = I2C_FIRST_FRAME; + } } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) || - (obj_s->XferOperation == I2C_NEXT_FRAME)) { - if (stop) + (obj_s->XferOperation == I2C_NEXT_FRAME)) { + if (stop) { obj_s->XferOperation = I2C_LAST_FRAME; - else + } else { obj_s->XferOperation = I2C_NEXT_FRAME; + } } obj_s->event = 0; - /* Activate default IRQ handlers for sync mode - * which would be overwritten in async mode - */ + /* Activate default IRQ handlers for sync mode + * which would be overwritten in async mode + */ i2c_ev_err_enable(obj, i2c_get_irq_handler(obj)); ret = HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation); - if(ret == HAL_OK) { + if (ret == HAL_OK) { timeout = BYTE_TIMEOUT_US * (length + 1); /* transfer started : wait completion or timeout */ - while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) { + while (!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) { wait_us(1); } i2c_ev_err_disable(obj); - if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) { + if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) { DEBUG_PRINTF(" TIMEOUT or error in i2c_read\r\n"); /* re-init IP to try and get back in a working state */ i2c_init(obj, obj_s->sda, obj_s->scl); @@ -773,7 +791,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { return count; } -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int count = I2C_ERROR_BUS_BUSY, ret = 0; @@ -783,40 +802,42 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; uint32_t op2 = I2C_LAST_FRAME; if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { - if (stop) + if (stop) { obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME; - else + } else { obj_s->XferOperation = I2C_FIRST_FRAME; + } } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) || - (obj_s->XferOperation == I2C_NEXT_FRAME)) { - if (stop) + (obj_s->XferOperation == I2C_NEXT_FRAME)) { + if (stop) { obj_s->XferOperation = I2C_LAST_FRAME; - else + } else { obj_s->XferOperation = I2C_NEXT_FRAME; + } } obj_s->event = 0; i2c_ev_err_enable(obj, i2c_get_irq_handler(obj)); - ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation); + ret = HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *) data, length, obj_s->XferOperation); - if(ret == HAL_OK) { + if (ret == HAL_OK) { timeout = BYTE_TIMEOUT_US * (length + 1); /* transfer started : wait completion or timeout */ - while(!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) { + while (!(obj_s->event & I2C_EVENT_ALL) && (--timeout != 0)) { wait_us(1); } i2c_ev_err_disable(obj); - if((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) { + if ((timeout == 0) || (obj_s->event != I2C_EVENT_TRANSFER_COMPLETE)) { DEBUG_PRINTF(" TIMEOUT or error in i2c_write\r\n"); /* re-init IP to try and get back in a working state */ i2c_init(obj, obj_s->sda, obj_s->scl); - } else { + } else { count = length; - } + } } else { DEBUG_PRINTF("ERROR in i2c_read\r\n"); } @@ -824,7 +845,8 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { return count; } -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){ +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); @@ -838,9 +860,8 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){ obj_s->XferOperation = I2C_NEXT_FRAME; } - HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t*)obj->rx_buff.buffer , obj->rx_buff.length, obj_s->XferOperation); - } - else + HAL_I2C_Master_Sequential_Receive_IT(hi2c, obj_s->address, (uint8_t *)obj->rx_buff.buffer, obj->rx_buff.length, obj_s->XferOperation); + } else #endif { /* Set event flag */ @@ -848,7 +869,8 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c){ } } -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){ +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); @@ -857,7 +879,8 @@ void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c){ obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; } -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){ +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); @@ -865,8 +888,9 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){ I2C_HandleTypeDef *handle = &(obj_s->handle); uint32_t address = 0; /* Store address to handle it after reset */ - if(obj_s->slave) + if (obj_s->slave) { address = handle->Init.OwnAddress1; + } #endif DEBUG_PRINTF("HAL_I2C_ErrorCallback:%d, index=%d\r\n", (int) hi2c->ErrorCode, obj_s->index); @@ -888,7 +912,8 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c){ #if DEVICE_I2CSLAVE /* SLAVE API FUNCTIONS */ -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); @@ -901,7 +926,8 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { HAL_I2C_EnableListen_IT(handle); } -void i2c_slave_mode(i2c_t *obj, int enable_slave) { +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); @@ -922,29 +948,32 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) { #define WriteAddressed 3 // the master is writing to this slave (slave = receiver) -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); /* Transfer direction in HAL is from Master point of view */ - if(TransferDirection == I2C_DIRECTION_RECEIVE) { + if (TransferDirection == I2C_DIRECTION_RECEIVE) { obj_s->pending_slave_tx_master_rx = 1; } - if(TransferDirection == I2C_DIRECTION_TRANSMIT) { + if (TransferDirection == I2C_DIRECTION_TRANSMIT) { obj_s->pending_slave_rx_maxter_tx = 1; } } -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle){ +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *I2cHandle) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(I2cHandle); struct i2c_s *obj_s = I2C_S(obj); obj_s->pending_slave_tx_master_rx = 0; } -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle){ +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(I2cHandle); struct i2c_s *obj_s = I2C_S(obj); @@ -957,23 +986,25 @@ void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) HAL_I2C_EnableListen_IT(hi2c); } -int i2c_slave_receive(i2c_t *obj) { +int i2c_slave_receive(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); int retValue = NoData; - if(obj_s->pending_slave_rx_maxter_tx) { - retValue = WriteAddressed; - } + if (obj_s->pending_slave_rx_maxter_tx) { + retValue = WriteAddressed; + } - if(obj_s->pending_slave_tx_master_rx) { - retValue = ReadAddressed; - } + if (obj_s->pending_slave_tx_master_rx) { + retValue = ReadAddressed; + } return (retValue); } -int i2c_slave_read(i2c_t *obj, char *data, int length) { +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int count = 0; @@ -983,22 +1014,23 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) { /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */ ret = HAL_I2C_Slave_Sequential_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME); - if(ret == HAL_OK) { + if (ret == HAL_OK) { timeout = BYTE_TIMEOUT_US * (length + 1); - while(obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) { + while (obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) { wait_us(1); } - if(timeout != 0) { - count = length; - } else { - DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n"); - } + if (timeout != 0) { + count = length; + } else { + DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n"); + } } return count; } -int i2c_slave_write(i2c_t *obj, const char *data, int length) { +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); int count = 0; @@ -1008,17 +1040,17 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) { /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */ ret = HAL_I2C_Slave_Sequential_Transmit_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME); - if(ret == HAL_OK) { + if (ret == HAL_OK) { timeout = BYTE_TIMEOUT_US * (length + 1); - while(obj_s->pending_slave_tx_master_rx && (--timeout != 0)) { + while (obj_s->pending_slave_tx_master_rx && (--timeout != 0)) { wait_us(1); } - if(timeout != 0) { - count = length; - } else { - DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n"); - } + if (timeout != 0) { + count = length; + } else { + DEBUG_PRINTF("TIMEOUT or error in i2c_slave_write\r\n"); + } } return count; @@ -1027,7 +1059,8 @@ int i2c_slave_write(i2c_t *obj, const char *data, int length) { #if DEVICE_I2C_ASYNCH /* ASYNCH MASTER API FUNCTIONS */ -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){ +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); @@ -1041,7 +1074,8 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c){ obj_s->event = I2C_EVENT_ERROR; } -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) { +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ // TODO: DMA usage is currently ignored by this way (void) hint; @@ -1073,41 +1107,43 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; uint32_t op2 = I2C_LAST_FRAME; if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { - if (stop) + if (stop) { obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME; - else + } else { obj_s->XferOperation = I2C_FIRST_FRAME; + } } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) || - (obj_s->XferOperation == I2C_NEXT_FRAME)) { - if (stop) + (obj_s->XferOperation == I2C_NEXT_FRAME)) { + if (stop) { obj_s->XferOperation = I2C_LAST_FRAME; - else + } else { obj_s->XferOperation = I2C_NEXT_FRAME; + } } if (tx_length > 0) { - HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, obj_s->XferOperation); + HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, obj_s->XferOperation); } if (rx_length > 0) { - HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t*)rx, rx_length, obj_s->XferOperation); + HAL_I2C_Master_Sequential_Receive_IT(handle, address, (uint8_t *)rx, rx_length, obj_s->XferOperation); } - } - else if (tx_length && rx_length) { + } else if (tx_length && rx_length) { /* Two steps operation, don't modify XferOperation, keep it for next step */ // Trick to remove compiler warning "left and right operands are identical" in some cases uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; uint32_t op2 = I2C_LAST_FRAME; if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { - HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME); + HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, I2C_FIRST_FRAME); } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) || - (obj_s->XferOperation == I2C_NEXT_FRAME)) { - HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_NEXT_FRAME); + (obj_s->XferOperation == I2C_NEXT_FRAME)) { + HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t *)tx, tx_length, I2C_NEXT_FRAME); } } } -uint32_t i2c_irq_handler_asynch(i2c_t *obj) { +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); @@ -1115,24 +1151,25 @@ uint32_t i2c_irq_handler_asynch(i2c_t *obj) { HAL_I2C_EV_IRQHandler(handle); HAL_I2C_ER_IRQHandler(handle); - /* Return I2C event status */ + /* Return I2C event status */ return (obj_s->event & obj_s->available_events); } -uint8_t i2c_active(i2c_t *obj) { +uint8_t i2c_active(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); if (handle->State == HAL_I2C_STATE_READY) { return 0; - } - else { + } else { return 1; } } -void i2c_abort_asynch(i2c_t *obj) { +void i2c_abort_asynch(i2c_t *obj) +{ struct i2c_s *obj_s = I2C_S(obj); I2C_HandleTypeDef *handle = &(obj_s->handle); diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index e089cd05d4..b5601fd030 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -40,7 +40,7 @@ LPTIM_HandleTypeDef LptimHandle; -const ticker_info_t* lp_ticker_get_info() +const ticker_info_t *lp_ticker_get_info() { static const ticker_info_t info = { #if MBED_CONF_TARGET_LSE_AVAILABLE @@ -241,10 +241,10 @@ void lp_ticker_clear_interrupt(void) #include "rtc_api_hal.h" -const ticker_info_t* lp_ticker_get_info() +const ticker_info_t *lp_ticker_get_info() { static const ticker_info_t info = { - RTC_CLOCK/4, // RTC_WAKEUPCLOCK_RTCCLK_DIV4 + RTC_CLOCK / 4, // RTC_WAKEUPCLOCK_RTCCLK_DIV4 32 }; return &info; diff --git a/targets/TARGET_STM/mbed_crc_api.c b/targets/TARGET_STM/mbed_crc_api.c index 8ffb0f1d93..fd113e3fec 100644 --- a/targets/TARGET_STM/mbed_crc_api.c +++ b/targets/TARGET_STM/mbed_crc_api.c @@ -8,63 +8,63 @@ static CRC_HandleTypeDef current_state; static uint32_t final_xor; -bool hal_crc_is_supported(const crc_mbed_config_t* config) +bool hal_crc_is_supported(const crc_mbed_config_t *config) { - if (config == NULL) { - return false; - } + if (config == NULL) { + return false; + } - if (config->polynomial != POLY_32BIT_ANSI) { - return false; - } + if (config->polynomial != POLY_32BIT_ANSI) { + return false; + } - if (config->width != 32) { - return false; - } + if (config->width != 32) { + return false; + } - if ((config->final_xor != 0xFFFFFFFFU) && (config->final_xor != 0)) { - return false; - } + if ((config->final_xor != 0xFFFFFFFFU) && (config->final_xor != 0)) { + return false; + } - return true; + return true; } -void hal_crc_compute_partial_start(const crc_mbed_config_t* config) +void hal_crc_compute_partial_start(const crc_mbed_config_t *config) { - MBED_ASSERT(hal_crc_is_supported(config)); + MBED_ASSERT(hal_crc_is_supported(config)); - __HAL_RCC_CRC_CLK_ENABLE(); + __HAL_RCC_CRC_CLK_ENABLE(); - final_xor = config->final_xor; + final_xor = config->final_xor; - current_state.Instance = CRC; - current_state.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; - current_state.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; - current_state.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE; - current_state.Init.InitValue = config->initial_xor; - current_state.Init.CRCLength = CRC_POLYLENGTH_32B; - current_state.Init.InputDataInversionMode = - config->reflect_in ? CRC_INPUTDATA_INVERSION_BYTE - : CRC_INPUTDATA_INVERSION_NONE; - current_state.Init.OutputDataInversionMode = - config->reflect_out ? CRC_OUTPUTDATA_INVERSION_ENABLE - : CRC_OUTPUTDATA_INVERSION_DISABLE; + current_state.Instance = CRC; + current_state.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; + current_state.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; + current_state.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE; + current_state.Init.InitValue = config->initial_xor; + current_state.Init.CRCLength = CRC_POLYLENGTH_32B; + current_state.Init.InputDataInversionMode = + config->reflect_in ? CRC_INPUTDATA_INVERSION_BYTE + : CRC_INPUTDATA_INVERSION_NONE; + current_state.Init.OutputDataInversionMode = + config->reflect_out ? CRC_OUTPUTDATA_INVERSION_ENABLE + : CRC_OUTPUTDATA_INVERSION_DISABLE; - HAL_CRC_Init(¤t_state); + HAL_CRC_Init(¤t_state); } void hal_crc_compute_partial(const uint8_t *data, const size_t size) { - if (data && size) { - HAL_CRC_Accumulate(¤t_state, (uint32_t *)data, size); - } + if (data && size) { + HAL_CRC_Accumulate(¤t_state, (uint32_t *)data, size); + } } uint32_t hal_crc_get_result(void) { - const uint32_t result = current_state.Instance->DR; + const uint32_t result = current_state.Instance->DR; - return (final_xor == 0xFFFFFFFFU) ? ~result : result; + return (final_xor == 0xFFFFFFFFU) ? ~result : result; } #endif // DEVICE_CRC diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index 7692445cb1..bd37f4adfe 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -126,14 +126,14 @@ #endif // INITIAL_SP #if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS)) - extern uint32_t __StackLimit[]; - extern uint32_t __StackTop[]; - extern uint32_t __end__[]; - extern uint32_t __HeapLimit[]; - #define HEAP_START ((unsigned char*)__end__) - #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) - #define ISR_STACK_START ((unsigned char*)__StackLimit) - #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) +extern uint32_t __StackLimit[]; +extern uint32_t __StackTop[]; +extern uint32_t __end__[]; +extern uint32_t __HeapLimit[]; +#define HEAP_START ((unsigned char*)__end__) +#define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) +#define ISR_STACK_START ((unsigned char*)__StackLimit) +#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) #endif #endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_STM/nvic_addr.h b/targets/TARGET_STM/nvic_addr.h index 023b5fcf33..adb75f0028 100644 --- a/targets/TARGET_STM/nvic_addr.h +++ b/targets/TARGET_STM/nvic_addr.h @@ -21,16 +21,16 @@ extern "C" { #endif #if defined(__ICCARM__) - #pragma section=".intvec" - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) +#pragma section=".intvec" +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) #elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - extern uint32_t Load$$LR$$LR_IROM1$$Base[]; - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) +extern uint32_t Load$$LR$$LR_IROM1$$Base[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) #elif defined(__GNUC__) - extern uint32_t g_pfnVectors[]; - #define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors) +extern uint32_t g_pfnVectors[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors) #else - #error "Flash vector address not set for this toolchain" +#error "Flash vector address not set for this toolchain" #endif #ifdef __cplusplus diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 5b9a3fa6b0..5c92ad19bd 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -77,11 +77,11 @@ void pin_function(PinName pin, int data) * But for families like F1, speed only applies to output. */ #if defined (TARGET_STM32F1) -if (mode == STM_PIN_OUTPUT) { + if (mode == STM_PIN_OUTPUT) { #endif - LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); + LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); #if defined (TARGET_STM32F1) -} + } #endif switch (mode) { @@ -94,7 +94,7 @@ if (mode == STM_PIN_OUTPUT) { case STM_PIN_ALTERNATE: ll_mode = LL_GPIO_MODE_ALTERNATE; // In case of ALT function, also set he afnum - stm_pin_SetAFPin(gpio, pin, afnum); + stm_pin_SetAFPin(gpio, pin, afnum); break; case STM_PIN_ANALOG: ll_mode = LL_GPIO_MODE_ANALOG; @@ -115,12 +115,12 @@ if (mode == STM_PIN_OUTPUT) { #endif /* For now by default use Speed HIGH for output or alt modes */ - if ((mode == STM_PIN_OUTPUT) ||(mode == STM_PIN_ALTERNATE)) { - if (STM_PIN_OD(data)) { + if ((mode == STM_PIN_OUTPUT) || (mode == STM_PIN_ALTERNATE)) { + if (STM_PIN_OD(data)) { LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN); - } else { + } else { LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_PUSHPULL); - } + } } stm_pin_PullConfig(gpio, ll_pin, STM_PIN_PUPD(data)); @@ -141,8 +141,7 @@ void pin_mode(PinName pin, PinMode mode) GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index); uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin); - if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE)) - { + if ((function == LL_GPIO_MODE_OUTPUT) || (function == LL_GPIO_MODE_ALTERNATE)) { if ((mode == OpenDrainNoPull) || (mode == OpenDrainPullUp) || (mode == OpenDrainPullDown)) { LL_GPIO_SetPinOutputType(gpio, ll_pin, LL_GPIO_OUTPUT_OPENDRAIN); } else { diff --git a/targets/TARGET_STM/pwmout_api.c b/targets/TARGET_STM/pwmout_api.c index 552fde0a79..e94b0628b4 100644 --- a/targets/TARGET_STM/pwmout_api.c +++ b/targets/TARGET_STM/pwmout_api.c @@ -39,7 +39,7 @@ static TIM_HandleTypeDef TimHandle; -void pwmout_init(pwmout_t* obj, PinName pin) +void pwmout_init(pwmout_t *obj, PinName pin) { // Get the peripheral name from the pin and assign it to the object obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); @@ -53,7 +53,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) // Enable TIM clock #if defined(TIM1_BASE) - if (obj->pwm == PWM_1){ + if (obj->pwm == PWM_1) { __HAL_RCC_TIM1_CLK_ENABLE(); } #endif @@ -163,13 +163,13 @@ void pwmout_init(pwmout_t* obj, PinName pin) pwmout_period_us(obj, 20000); // 20 ms per default } -void pwmout_free(pwmout_t* obj) +void pwmout_free(pwmout_t *obj) { // Configure GPIO pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -void pwmout_write(pwmout_t* obj, float value) +void pwmout_write(pwmout_t *obj, float value) { TIM_OC_InitTypeDef sConfig; int channel = 0; @@ -228,7 +228,7 @@ void pwmout_write(pwmout_t* obj, float value) } } -float pwmout_read(pwmout_t* obj) +float pwmout_read(pwmout_t *obj) { float value = 0; if (obj->period > 0) { @@ -237,17 +237,17 @@ float pwmout_read(pwmout_t* obj) return ((value > (float)1.0) ? (float)(1.0) : (value)); } -void pwmout_period(pwmout_t* obj, float seconds) +void pwmout_period(pwmout_t *obj, float seconds) { pwmout_period_us(obj, seconds * 1000000.0f); } -void pwmout_period_ms(pwmout_t* obj, int ms) +void pwmout_period_ms(pwmout_t *obj, int ms) { pwmout_period_us(obj, ms * 1000); } -void pwmout_period_us(pwmout_t* obj, int us) +void pwmout_period_us(pwmout_t *obj, int us) { TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); RCC_ClkInitTypeDef RCC_ClkInitStruct; @@ -263,14 +263,15 @@ void pwmout_period_us(pwmout_t* obj, int us) HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &PclkFreq); /* Parse the pwm / apb mapping table to find the right entry */ - while(pwm_apb_map_table[i].pwm != obj->pwm) { + while (pwm_apb_map_table[i].pwm != obj->pwm) { i++; } - if(pwm_apb_map_table[i].pwm == 0) + if (pwm_apb_map_table[i].pwm == 0) { error("Unknown PWM instance"); + } - if(pwm_apb_map_table[i].pwmoutApb == PWMOUT_ON_APB1) { + if (pwm_apb_map_table[i].pwmoutApb == PWMOUT_ON_APB1) { PclkFreq = HAL_RCC_GetPCLK1Freq(); APBxCLKDivider = RCC_ClkInitStruct.APB1CLKDivider; } else { @@ -295,9 +296,9 @@ void pwmout_period_us(pwmout_t* obj, int us) while ((TimHandle.Init.Period > 0xFFFF) || (TimHandle.Init.Prescaler > 0xFFFF)) { obj->prescaler = obj->prescaler * 2; if (APBxCLKDivider == RCC_HCLK_DIV1) { - TimHandle.Init.Prescaler = (((PclkFreq) / 1000000) * obj->prescaler) - 1; + TimHandle.Init.Prescaler = (((PclkFreq) / 1000000) * obj->prescaler) - 1; } else { - TimHandle.Init.Prescaler = (((PclkFreq * 2) / 1000000) * obj->prescaler) - 1; + TimHandle.Init.Prescaler = (((PclkFreq * 2) / 1000000) * obj->prescaler) - 1; } TimHandle.Init.Period = (us - 1) / obj->prescaler; /* Period decreases and prescaler increases over loops, so check for @@ -324,17 +325,17 @@ void pwmout_period_us(pwmout_t* obj, int us) __HAL_TIM_ENABLE(&TimHandle); } -void pwmout_pulsewidth(pwmout_t* obj, float seconds) +void pwmout_pulsewidth(pwmout_t *obj, float seconds) { pwmout_pulsewidth_us(obj, seconds * 1000000.0f); } -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) { pwmout_pulsewidth_us(obj, ms * 1000); } -void pwmout_pulsewidth_us(pwmout_t* obj, int us) +void pwmout_pulsewidth_us(pwmout_t *obj, int us) { float value = (float)us / (float)obj->period; pwmout_write(obj, value); diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 0b4439fbbb..d048add696 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -46,7 +46,7 @@ void rtc_init(void) HAL_PWR_EnableBkUpAccess(); #if DEVICE_LPTICKER - if ( (rtc_isenabled()) && ((RTC->PRER & RTC_PRER_PREDIV_S) == PREDIV_S_VALUE) ) { + if ((rtc_isenabled()) && ((RTC->PRER & RTC_PRER_PREDIV_S) == PREDIV_S_VALUE)) { #else /* DEVICE_LPTICKER */ if (rtc_isenabled()) { #endif /* DEVICE_LPTICKER */ @@ -259,7 +259,7 @@ void rtc_write(time_t t) int rtc_isenabled(void) { #if !(TARGET_STM32F1) - return ( ((RTC->ISR & RTC_ISR_INITS) == RTC_ISR_INITS) && ((RTC->ISR & RTC_ISR_RSF) == RTC_ISR_RSF) ); + return (((RTC->ISR & RTC_ISR_INITS) == RTC_ISR_INITS) && ((RTC->ISR & RTC_ISR_RSF) == RTC_ISR_RSF)); #else /* TARGET_STM32F1 */ return ((RTC->CRL & RTC_CRL_RSF) == RTC_CRL_RSF); #endif /* TARGET_STM32F1 */ @@ -286,9 +286,9 @@ static void RTC_IRQHandler(void) { /* Update HAL state */ RtcHandle.Instance = RTC; - if(__HAL_RTC_WAKEUPTIMER_GET_IT(&RtcHandle, RTC_IT_WUT)) { + if (__HAL_RTC_WAKEUPTIMER_GET_IT(&RtcHandle, RTC_IT_WUT)) { /* Get the status of the Interrupt */ - if((uint32_t)(RTC->CR & RTC_IT_WUT) != (uint32_t)RESET) { + if ((uint32_t)(RTC->CR & RTC_IT_WUT) != (uint32_t)RESET) { /* Clear the WAKEUPTIMER interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RtcHandle, RTC_FLAG_WUTF); diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index a3209f1f6d..065418c74b 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -57,8 +57,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) if ((tx == STDIO_UART_TX) || (rx == STDIO_UART_RX)) { stdio_config = 1; - } - else { + } else { if (uart_tx == pinmap_peripheral(STDIO_UART_TX, PinMap_UART_TX)) { error("Error: new serial object is using same UART as STDIO"); } @@ -206,8 +205,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) #if MBED_CONF_PLATFORM_STDIO_BAUD_RATE obj_s->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json #endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */ - } - else { + } else { #if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE obj_s->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json #endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */ @@ -370,7 +368,7 @@ void serial_baud(serial_t *obj, int baudrate) obj_s->baudrate = baudrate; #if defined(LPUART1_BASE) - /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */ + /* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */ if (obj_s->uart == LPUART_1) { /* If baudrate is lower than 9600 try to change to LSE */ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; @@ -384,7 +382,7 @@ void serial_baud(serial_t *obj, int baudrate) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); } if (init_uart(obj) == HAL_OK) { - return; + return; } /* Change LPUART clock source and try again */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; @@ -466,7 +464,7 @@ int serial_readable(serial_t *obj) /* To avoid a target blocking case, let's check for * possible OVERRUN error and discard it */ - if(__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE)) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE)) { __HAL_UART_CLEAR_OREFLAG(huart); } // Check if data is received diff --git a/targets/TARGET_STM/serial_api_hal.h b/targets/TARGET_STM/serial_api_hal.h index c5cea54e0b..1849128106 100644 --- a/targets/TARGET_STM/serial_api_hal.h +++ b/targets/TARGET_STM/serial_api_hal.h @@ -47,9 +47,9 @@ extern "C" { */ #if DEVICE_SERIAL_ASYNCH - #define SERIAL_S(obj) (&((obj)->serial)) +#define SERIAL_S(obj) (&((obj)->serial)) #else - #define SERIAL_S(obj) (obj) +#define SERIAL_S(obj) (obj) #endif diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index 3dd90a3477..5769f3f13d 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -64,12 +64,12 @@ static void ForcePeriphOutofDeepSleep(void) // Select HSI ss system clock source as a first step #ifdef RCC_CLOCKTYPE_PCLK2 - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; #else - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK - | RCC_CLOCKTYPE_PCLK1); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK + | RCC_CLOCKTYPE_PCLK1); #endif RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; @@ -84,12 +84,12 @@ static void ForcePeriphOutofDeepSleep(void) /**Initializes the CPU, AHB and APB busses clocks */ #ifdef RCC_CLOCKTYPE_PCLK2 - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; #else - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1); #endif RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; @@ -213,7 +213,7 @@ void hal_deepsleep(void) } #endif // Enable IRQs - core_util_critical_section_exit(); + core_util_critical_section_exit(); } #endif diff --git a/targets/TARGET_STM/stm32_assert.h b/targets/TARGET_STM/stm32_assert.h index 45aa52f72b..ad44f9ce36 100644 --- a/targets/TARGET_STM/stm32_assert.h +++ b/targets/TARGET_STM/stm32_assert.h @@ -37,7 +37,7 @@ * If expr is true, it returns no value. * @retval None */ - #include "mbed_assert.h" - #define assert_param(expr) MBED_ASSERT(expr) +#include "mbed_assert.h" +#define assert_param(expr) MBED_ASSERT(expr) #endif diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index b4a71e7bd1..64cd9bdfbb 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -42,15 +42,15 @@ #include "spi_device.h" #if DEVICE_SPI_ASYNCH - #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi)) +#define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi)) #else - #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi)) +#define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi)) #endif #if DEVICE_SPI_ASYNCH - #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) +#define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) #else - #define SPI_S(obj) (( struct spi_s *)(obj)) +#define SPI_S(obj) (( struct spi_s *)(obj)) #endif #ifndef DEBUG_STDIO @@ -176,7 +176,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (miso != NC) { handle->Init.Direction = SPI_DIRECTION_2LINES; } else { - handle->Init.Direction = SPI_DIRECTION_1LINE; + handle->Init.Direction = SPI_DIRECTION_1LINE; } handle->Init.CLKPhase = SPI_PHASE_1EDGE; @@ -311,20 +311,22 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) */ extern int spi_get_clock_freq(spi_t *obj); -static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2, - SPI_BAUDRATEPRESCALER_4, - SPI_BAUDRATEPRESCALER_8, - SPI_BAUDRATEPRESCALER_16, - SPI_BAUDRATEPRESCALER_32, - SPI_BAUDRATEPRESCALER_64, - SPI_BAUDRATEPRESCALER_128, - SPI_BAUDRATEPRESCALER_256}; +static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2, + SPI_BAUDRATEPRESCALER_4, + SPI_BAUDRATEPRESCALER_8, + SPI_BAUDRATEPRESCALER_16, + SPI_BAUDRATEPRESCALER_32, + SPI_BAUDRATEPRESCALER_64, + SPI_BAUDRATEPRESCALER_128, + SPI_BAUDRATEPRESCALER_256 + }; -void spi_frequency(spi_t *obj, int hz) { +void spi_frequency(spi_t *obj, int hz) +{ struct spi_s *spiobj = SPI_S(obj); int spi_hz = 0; uint8_t prescaler_rank = 0; - uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1; + uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1; SPI_HandleTypeDef *handle = &(spiobj->handle); /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */ @@ -386,7 +388,7 @@ int spi_master_write(spi_t *obj, int value) SPI_HandleTypeDef *handle = &(spiobj->handle); if (handle->Init.Direction == SPI_DIRECTION_1LINE) { - return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE); + return HAL_SPI_Transmit(handle, (uint8_t *)&value, 1, TIMEOUT_1_BYTE); } #if defined(LL_SPI_RX_FIFO_TH_HALF) @@ -441,13 +443,13 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, } else { /* In case of 1 WIRE only, first handle TX, then Rx */ if (tx_length != 0) { - if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) { + if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t *)tx_buffer, tx_length, tx_length * TIMEOUT_1_BYTE)) { /* report an error */ total = 0; } } if (rx_length != 0) { - if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) { + if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t *)rx_buffer, rx_length, rx_length * TIMEOUT_1_BYTE)) { /* report an error */ total = 0; } @@ -538,18 +540,18 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer // enable the right hal transfer int rc = 0; - switch(transfer_type) { + switch (transfer_type) { case SPI_TRANSFER_TYPE_TXRX: - rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words); + rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t *)tx, (uint8_t *)rx, words); break; case SPI_TRANSFER_TYPE_TX: - rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words); + rc = HAL_SPI_Transmit_IT(handle, (uint8_t *)tx, words); break; case SPI_TRANSFER_TYPE_RX: // the receive function also "transmits" the receive buffer so in order // to guarantee that 0xff is on the line, we explicitly memset it here memset(rx, SPI_FILL_WORD, length); - rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words); + rc = HAL_SPI_Receive_IT(handle, (uint8_t *)rx, words); break; default: length = 0; @@ -578,8 +580,9 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); // don't do anything, if the buffers aren't valid - if (!use_tx && !use_rx) + if (!use_tx && !use_rx) { return; + } // copy the buffers to the SPI object obj->tx_buff.buffer = (void *) tx; @@ -603,8 +606,8 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, // enable the right hal transfer if (use_tx && use_rx) { // we cannot manage different rx / tx sizes, let's use smaller one - size_t size = (tx_length < rx_length)? tx_length : rx_length; - if(tx_length != rx_length) { + size_t size = (tx_length < rx_length) ? tx_length : rx_length; + if (tx_length != rx_length) { DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size); obj->tx_buff.length = size; obj->rx_buff.length = size; @@ -627,7 +630,7 @@ inline uint32_t spi_irq_handler_asynch(spi_t *obj) if (obj->spi.handle.State == HAL_SPI_STATE_READY) { // When HAL SPI is back to READY state, check if there was an error int error = obj->spi.handle.ErrorCode; - if(error != HAL_SPI_ERROR_NONE) { + if (error != HAL_SPI_ERROR_NONE) { // something went wrong and the transfer has definitely completed event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; @@ -638,10 +641,10 @@ inline uint32_t spi_irq_handler_asynch(spi_t *obj) } else { // else we're done event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; - } - // enable the interrupt - NVIC_DisableIRQ(obj->spi.spiIRQ); - NVIC_ClearPendingIRQ(obj->spi.spiIRQ); + } + // enable the interrupt + NVIC_DisableIRQ(obj->spi.spiIRQ); + NVIC_ClearPendingIRQ(obj->spi.spiIRQ); } @@ -654,7 +657,7 @@ uint8_t spi_active(spi_t *obj) SPI_HandleTypeDef *handle = &(spiobj->handle); HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle); - switch(state) { + switch (state) { case HAL_SPI_STATE_RESET: case HAL_SPI_STATE_READY: case HAL_SPI_STATE_ERROR: diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c index f77f2b3151..f85dae2bd7 100644 --- a/targets/TARGET_STM/trng_api.c +++ b/targets/TARGET_STM/trng_api.c @@ -33,7 +33,7 @@ void trng_init(trng_t *obj) uint32_t dummy; /* We're only supporting a single user of RNG */ - if (core_util_atomic_incr_u8(&users, 1) > 1 ) { + if (core_util_atomic_incr_u8(&users, 1) > 1) { error("Only 1 RNG instance supported\r\n"); } @@ -77,11 +77,11 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l *output_length = 0; /* Get Random byte */ - while ((*output_length < length) && (ret ==0)) { - if ( HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random ) != HAL_OK) { - ret = -1; + while ((*output_length < length) && (ret == 0)) { + if (HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random) != HAL_OK) { + ret = -1; } else { - for (uint8_t i =0; (i < 4) && (*output_length < length) ; i++) { + for (uint8_t i = 0; (i < 4) && (*output_length < length) ; i++) { *output++ = random[i]; *output_length += 1; random[i] = 0; @@ -90,11 +90,11 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l } /* Just be extra sure that we didn't do it wrong */ - if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) { + if ((__HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS))) != 0) { ret = -1; } - return( ret ); + return (ret); } #endif diff --git a/targets/TARGET_STM/us_ticker.c b/targets/TARGET_STM/us_ticker.c index b6bb210baa..db4a9e96ab 100644 --- a/targets/TARGET_STM/us_ticker.c +++ b/targets/TARGET_STM/us_ticker.c @@ -26,7 +26,7 @@ TIM_HandleTypeDef TimMasterHandle; -const ticker_info_t* us_ticker_get_info() +const ticker_info_t *us_ticker_get_info() { static const ticker_info_t info = { 1000000,