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Merge pull request #7351 from jeromecoutant/PR_ASTYLE 

STM32 files with MBED astyle rules
pull/7361/head
Cruz Monrreal 2018-06-28 10:06:03 -05:00 committed by GitHub
parent 5bf483ee17 408209989e
commit bf21bac52d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
279 changed files with 4542 additions and 4306 deletions
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2
features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1510/mbedtls_device.h
View File

@ -1,5 +1,5 @@
/*
* mbedtls_device.h
* mbedtls_device.h
*******************************************************************************
* Copyright (c) 2017, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0

2
features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_MTB_ADV_WISE_1570/mbedtls_device.h
View File

@ -1,5 +1,5 @@
/*
* mbedtls_device.h
* mbedtls_device.h
*******************************************************************************
* Copyright (c) 2017, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0

2
features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L486RG/mbedtls_device.h
View File

@ -1,5 +1,5 @@
/*
* mbedtls_device.h
* mbedtls_device.h
*******************************************************************************
* Copyright (c) 2017, STMicroelectronics
* SPDX-License-Identifier: Apache-2.0

268
features/mbedtls/targets/TARGET_STM/aes_alt.c
View File

@ -31,16 +31,16 @@
#define CRYP AES
#endif
static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits )
static int aes_set_key(mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits)
{
switch( keybits ) {
switch (keybits) {
case 128:
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_128B;
memcpy(ctx->aes_key, key, 16);
break;
case 192:
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
#else
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_192B;
memcpy(ctx->aes_key, key, 24);
@ -51,12 +51,14 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi
ctx->hcryp_aes.Init.KeySize = CRYP_KEYSIZE_256B;
memcpy(ctx->aes_key, key, 32);
break;
default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
default :
return (MBEDTLS_ERR_AES_INVALID_KEY_LENGTH);
}
/* Deinitializes the CRYP peripheral */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR)
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) == HAL_ERROR) {
return (HAL_ERROR);
}
ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
ctx->hcryp_aes.Instance = CRYP;
@ -67,64 +69,69 @@ static int aes_set_key( mbedtls_aes_context *ctx, const unsigned char *key, unsi
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
#endif
if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR)
if (HAL_CRYP_Init(&ctx->hcryp_aes) == HAL_ERROR) {
return (HAL_ERROR);
}
/* allow multi-instance of CRYP use: save context for CRYP HW module CR */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
return(0);
return (0);
}
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n )
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
volatile unsigned char *p = (unsigned char *)v;
while (n--) {
*p++ = 0;
}
}
void mbedtls_aes_init( mbedtls_aes_context *ctx )
void mbedtls_aes_init(mbedtls_aes_context *ctx)
{
memset( ctx, 0, sizeof( mbedtls_aes_context ) );
memset(ctx, 0, sizeof(mbedtls_aes_context));
}
void mbedtls_aes_free( mbedtls_aes_context *ctx )
void mbedtls_aes_free(mbedtls_aes_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
}
/* Force the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_FORCE_RESET();
/* Release the CRYP Periheral Clock Reset */
__HAL_RCC_CRYP_RELEASE_RESET();
mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) );
mbedtls_zeroize(ctx, sizeof(mbedtls_aes_context));
}
int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits )
int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits)
{
int ret_val = 0;
ret_val = aes_set_key(ctx, key, keybits);
return(ret_val);
return (ret_val);
}
int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits )
int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits)
{
int ret_val = 0;
ret_val = aes_set_key(ctx, key, keybits);
return( ret_val );
return (ret_val);
}
int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
int mode,
const unsigned char input[16],
unsigned char output[16] )
int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx,
int mode,
const unsigned char input[16],
unsigned char output[16])
{
/* allow multi-instance of CRYP use: restore context for CRYP hw module */
@ -133,27 +140,28 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
ctx->hcryp_aes.Init.pKey = ctx->aes_key;
if(mode == MBEDTLS_AES_DECRYPT) { /* AES decryption */
if (mbedtls_internal_aes_decrypt( ctx, input, output )){
if (mode == MBEDTLS_AES_DECRYPT) { /* AES decryption */
if (mbedtls_internal_aes_decrypt(ctx, input, output)) {
return ST_ERR_AES_BUSY;
}
} else { /* AES encryption */
if (mbedtls_internal_aes_encrypt( ctx, input, output )) {
if (mbedtls_internal_aes_encrypt(ctx, input, output)) {
return ST_ERR_AES_BUSY;
}
}
/* allow multi-instance of CRYP use: save context for CRYP HW module CR */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
return( 0 );
return (0);
}
#if defined(MBEDTLS_CIPHER_MODE_CBC)
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
static int st_cbc_restore_context(mbedtls_aes_context *ctx){
static int st_cbc_restore_context(mbedtls_aes_context *ctx)
{
uint32_t tickstart;
tickstart = HAL_GetTick();
while((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0){
while ((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0) {
if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) {
return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy
}
@ -163,62 +171,71 @@ static int st_cbc_restore_context(mbedtls_aes_context *ctx){
return 0;
}
static int st_hal_cryp_cbc( mbedtls_aes_context *ctx, uint32_t opmode, size_t length,
unsigned char iv[16], uint8_t *input, uint8_t *output)
static int st_hal_cryp_cbc(mbedtls_aes_context *ctx, uint32_t opmode, size_t length,
unsigned char iv[16], uint8_t *input, uint8_t *output)
{
ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init
/* At this moment only, we know we have CBC mode: Re-initialize AES
IP with proper parameters and apply key and IV for multi context usecase */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
ctx->hcryp_aes.Init.OperatingMode = opmode;
ctx->hcryp_aes.Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
if(HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0)
if (HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0) {
return ST_ERR_AES_BUSY;
}
return 0;
}
#else /* STM32F4 and STM32F7 */
static int st_cbc_restore_context(mbedtls_aes_context *ctx){
static int st_cbc_restore_context(mbedtls_aes_context *ctx)
{
/* allow multi-instance of CRYP use: restore context for CRYP hw module */
ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
/* Re-initialize AES processor with proper parameters
and (re-)apply key and IV for multi context usecases */
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
}
if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
return 0;
}
#endif /* TARGET_STM32L486xG || TARGET_STM32L443xC */
int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output )
int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output)
{
uint32_t tickstart;
uint32_t *iv_ptr = (uint32_t *)&iv[0];
if( length % 16 )
return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
if (length % 16) {
return (MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH);
}
ctx->hcryp_aes.Init.pInitVect = &iv[0];
if (st_cbc_restore_context(ctx) != 0)
if (st_cbc_restore_context(ctx) != 0) {
return (ST_ERR_AES_BUSY);
}
#if defined (TARGET_STM32L486xG) || defined (TARGET_STM32L443xC)
if( mode == MBEDTLS_AES_DECRYPT ) {
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0)
if (mode == MBEDTLS_AES_DECRYPT) {
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) {
return ST_ERR_AES_BUSY;
}
/* Save the internal IV vector for multi context purpose */
tickstart = HAL_GetTick();
while((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0){
while ((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0) {
if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) {
return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy
}
@ -230,20 +247,22 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
*iv_ptr++ = ctx->hcryp_aes.Instance->IVR1;
*iv_ptr++ = ctx->hcryp_aes.Instance->IVR0;
} else {
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0)
if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0) {
return ST_ERR_AES_BUSY;
memcpy( iv, output, 16 ); /* current output is the IV vector for the next call */
}
memcpy(iv, output, 16); /* current output is the IV vector for the next call */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
}
#else
if( mode == MBEDTLS_AES_DECRYPT ) {
if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK)
if (mode == MBEDTLS_AES_DECRYPT) {
if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) {
return ST_ERR_AES_BUSY;
}
/* Save the internal IV vector for multi context purpose */
tickstart = HAL_GetTick();
while((ctx->hcryp_aes.Instance->SR & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM){
while ((ctx->hcryp_aes.Instance->SR & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM) {
if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) {
return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy
}
@ -255,9 +274,10 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
*iv_ptr++ = ctx->hcryp_aes.Instance->IV1LR;
*iv_ptr++ = ctx->hcryp_aes.Instance->IV1RR;
} else {
if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK)
if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK) {
return ST_ERR_AES_BUSY;
memcpy( iv, output, 16 ); /* current output is the IV vector for the next call */
}
memcpy(iv, output, 16); /* current output is the IV vector for the next call */
ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
}
@ -267,115 +287,121 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
#endif /* MBEDTLS_CIPHER_MODE_CBC */
#if defined(MBEDTLS_CIPHER_MODE_CFB)
int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output )
int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output)
{
int c;
size_t n = *iv_off;
if( mode == MBEDTLS_AES_DECRYPT ) {
while( length-- ) {
if( n == 0 )
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
if (mode == MBEDTLS_AES_DECRYPT) {
while (length--) {
if (n == 0)
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) {
return ST_ERR_AES_BUSY;
}
c = *input++;
*output++ = (unsigned char)( c ^ iv[n] );
*output++ = (unsigned char)(c ^ iv[n]);
iv[n] = (unsigned char) c;
n = ( n + 1 ) & 0x0F;
n = (n + 1) & 0x0F;
}
} else {
while( length-- ) {
if( n == 0 )
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
while (length--) {
if (n == 0)
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) {
return ST_ERR_AES_BUSY;
}
iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
iv[n] = *output++ = (unsigned char)(iv[n] ^ *input++);
n = ( n + 1 ) & 0x0F;
n = (n + 1) & 0x0F;
}
}
*iv_off = n;
return( 0 );
return (0);
}
int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output )
int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output)
{
unsigned char c;
unsigned char ov[17];
while( length-- ) {
memcpy( ov, iv, 16 );
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
while (length--) {
memcpy(ov, iv, 16);
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) != 0) {
return ST_ERR_AES_BUSY;
}
if( mode == MBEDTLS_AES_DECRYPT )
if (mode == MBEDTLS_AES_DECRYPT) {
ov[16] = *input;
}
c = *output++ = (unsigned char)( iv[0] ^ *input++ );
c = *output++ = (unsigned char)(iv[0] ^ *input++);
if( mode == MBEDTLS_AES_ENCRYPT )
if (mode == MBEDTLS_AES_ENCRYPT) {
ov[16] = c;
}
memcpy( iv, ov + 1, 16 );
memcpy(iv, ov + 1, 16);
}
return( 0 );
return (0);
}
#endif /*MBEDTLS_CIPHER_MODE_CFB */
#if defined(MBEDTLS_CIPHER_MODE_CTR)
int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output )
int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output)
{
int c, i;
size_t n = *nc_off;
while( length-- )
{
if( n == 0 ) {
if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ) != 0)
while (length--) {
if (n == 0) {
if (mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block) != 0) {
return ST_ERR_AES_BUSY;
}
for( i = 16; i > 0; i-- )
if( ++nonce_counter[i - 1] != 0 )
for (i = 16; i > 0; i--)
if (++nonce_counter[i - 1] != 0) {
break;
}
}
c = *input++;
*output++ = (unsigned char)( c ^ stream_block[n] );
*output++ = (unsigned char)(c ^ stream_block[n]);
n = ( n + 1 ) & 0x0F;
n = (n + 1) & 0x0F;
}
*nc_off = n;
return( 0 );
return (0);
}
#endif /* MBEDTLS_CIPHER_MODE_CTR */
int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] )
int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16])
{
if (HAL_CRYP_AESECB_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) {
// error found
@ -385,11 +411,11 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
}
int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] )
int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16])
{
if(HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) {
if (HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) {
// error found
return ST_ERR_AES_BUSY;
}
@ -397,18 +423,18 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
}
#if !defined(MBEDTLS_DEPRECATED_REMOVED)
void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] )
void mbedtls_aes_encrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16])
{
mbedtls_internal_aes_encrypt( ctx, input, output );
mbedtls_internal_aes_encrypt(ctx, input, output);
}
void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] )
void mbedtls_aes_decrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16])
{
mbedtls_internal_aes_decrypt( ctx, input, output );
mbedtls_internal_aes_decrypt(ctx, input, output);
}
#endif /* MBEDTLS_DEPRECATED_REMOVED */
#endif /*MBEDTLS_AES_ALT*/

99
features/mbedtls/targets/TARGET_STM/aes_alt.h
View File

@ -41,8 +41,7 @@ extern "C" {
* - to simplify key expansion in the 256-bit case by
* generating an extra round key
*/
typedef struct
{
typedef struct {
unsigned char aes_key[32]; /* Decryption key */
CRYP_HandleTypeDef hcryp_aes;
uint32_t ctx_save_cr; /* save context for multi-instance */
@ -54,14 +53,14 @@ mbedtls_aes_context;
*
* \param ctx AES context to be initialized
*/
void mbedtls_aes_init( mbedtls_aes_context *ctx );
void mbedtls_aes_init(mbedtls_aes_context *ctx);
/**
* \brief Clear AES context
*
* \param ctx AES context to be cleared
*/
void mbedtls_aes_free( mbedtls_aes_context *ctx );
void mbedtls_aes_free(mbedtls_aes_context *ctx);
/**
* \brief AES key schedule (encryption)
@ -72,8 +71,8 @@ void mbedtls_aes_free( mbedtls_aes_context *ctx );
*
* \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
*/
int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits );
int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits);
/**
* \brief AES key schedule (decryption)
@ -84,8 +83,8 @@ int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
*
* \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
*/
int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits );
int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key,
unsigned int keybits);
/**
* \brief AES-ECB block encryption/decryption
@ -97,10 +96,10 @@ int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
int mode,
const unsigned char input[16],
unsigned char output[16] );
int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx,
int mode,
const unsigned char input[16],
unsigned char output[16]);
#if defined(MBEDTLS_CIPHER_MODE_CBC)
/**
@ -125,12 +124,12 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
*
* \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
*/
int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output);
#endif /* MBEDTLS_CIPHER_MODE_CBC */
#if defined(MBEDTLS_CIPHER_MODE_CFB)
@ -159,13 +158,13 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx,
int mode,
size_t length,
size_t *iv_off,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output);
/**
* \brief AES-CFB8 buffer encryption/decryption.
@ -191,12 +190,12 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output );
int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx,
int mode,
size_t length,
unsigned char iv[16],
const unsigned char *input,
unsigned char *output);
#endif /*MBEDTLS_CIPHER_MODE_CFB */
#if defined(MBEDTLS_CIPHER_MODE_CTR)
@ -222,13 +221,13 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
*
* \return 0 if successful
*/
int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output );
int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx,
size_t length,
size_t *nc_off,
unsigned char nonce_counter[16],
unsigned char stream_block[16],
const unsigned char *input,
unsigned char *output);
#endif /* MBEDTLS_CIPHER_MODE_CTR */
/**
@ -242,9 +241,9 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
*
* \return 0 if successful
*/
int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] );
int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16]);
/**
* \brief Internal AES block decryption function
@ -257,9 +256,9 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
*
* \return 0 if successful
*/
int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] );
int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16]);
#if !defined(MBEDTLS_DEPRECATED_REMOVED)
#if defined(MBEDTLS_DEPRECATED_WARNING)
@ -277,9 +276,9 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
* \param input Plaintext block
* \param output Output (ciphertext) block
*/
MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] );
MBEDTLS_DEPRECATED void mbedtls_aes_encrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16]);
/**
* \brief Deprecated internal AES block decryption function
@ -291,9 +290,9 @@ MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
* \param input Ciphertext block
* \param output Output (plaintext) block
*/
MBEDTLS_DEPRECATED void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16] );
MBEDTLS_DEPRECATED void mbedtls_aes_decrypt(mbedtls_aes_context *ctx,
const unsigned char input[16],
unsigned char output[16]);
#undef MBEDTLS_DEPRECATED
#endif /* !MBEDTLS_DEPRECATED_REMOVED */

43
features/mbedtls/targets/TARGET_STM/md5_alt.c
View File

@ -24,8 +24,12 @@
#include "mbedtls/platform.h"
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = v; while( n-- ) *p++ = 0;
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = v;
while (n--) {
*p++ = 0;
}
}
static int st_md5_restore_hw_context(mbedtls_md5_context *ctx)
@ -42,7 +46,7 @@ static int st_md5_restore_hw_context(mbedtls_md5_context *ctx)
}
HASH->STR = ctx->ctx_save_str;
HASH->CR = (ctx->ctx_save_cr | HASH_CR_INIT);
for (i=0;i<38;i++) {
for (i = 0; i < 38; i++) {
HASH->CSR[i] = ctx->ctx_save_csr[i];
}
return 1;
@ -62,35 +66,36 @@ static int st_md5_save_hw_context(mbedtls_md5_context *ctx)
/* allow multi-instance of HASH use: restore context for HASH HW module CR */
ctx->ctx_save_cr = HASH->CR;
ctx->ctx_save_str = HASH->STR;
for (i=0;i<38;i++) {
for (i = 0; i < 38; i++) {
ctx->ctx_save_csr[i] = HASH->CSR[i];
}
return 1;
}
void mbedtls_md5_init( mbedtls_md5_context *ctx )
void mbedtls_md5_init(mbedtls_md5_context *ctx)
{
mbedtls_zeroize( ctx, sizeof( mbedtls_md5_context ) );
mbedtls_zeroize(ctx, sizeof(mbedtls_md5_context));
/* Enable HASH clock */
__HAL_RCC_HASH_CLK_ENABLE();
}
void mbedtls_md5_free( mbedtls_md5_context *ctx )
void mbedtls_md5_free(mbedtls_md5_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
mbedtls_zeroize( ctx, sizeof( mbedtls_md5_context ) );
}
mbedtls_zeroize(ctx, sizeof(mbedtls_md5_context));
}
void mbedtls_md5_clone( mbedtls_md5_context *dst,
const mbedtls_md5_context *src )
void mbedtls_md5_clone(mbedtls_md5_context *dst,
const mbedtls_md5_context *src)
{
*dst = *src;
}
int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx )
int mbedtls_md5_starts_ret(mbedtls_md5_context *ctx)
{
/* HASH IP initialization */
if (HAL_HASH_DeInit(&ctx->hhash_md5) != 0) {
@ -112,7 +117,7 @@ int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx )
return 0;
}
int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE] )
int mbedtls_internal_md5_process(mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE])
{
if (st_md5_restore_hw_context(ctx) != 1) {
// Return HASH_BUSY timeout error here
@ -128,7 +133,7 @@ int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char
return 0;
}
int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen )
int mbedtls_md5_update_ret(mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen)
{
int err;
size_t currentlen = ilen;
@ -142,7 +147,7 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input
// store mechanism to accumulate ST_MD5_BLOCK_SIZE bytes (512 bits) in the HW
if (currentlen < (ST_MD5_BLOCK_SIZE - ctx->sbuf_len)) {
// only buffurize
memcpy(ctx->sbuf+ctx->sbuf_len, input, currentlen);
memcpy(ctx->sbuf + ctx->sbuf_len, input, currentlen);
ctx->sbuf_len += currentlen;
} else {
// fill buffer and process it
@ -154,14 +159,14 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input
}
// Process every input as long as it is %64 bytes, ie 512 bits
size_t iter = currentlen / ST_MD5_BLOCK_SIZE;
if (iter !=0) {
if (iter != 0) {
if (HAL_HASH_MD5_Accumulate(&ctx->hhash_md5, (uint8_t *)(input + ST_MD5_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_MD5_BLOCK_SIZE)) != 0) {
return MBEDTLS_ERR_MD5_HW_ACCEL_FAILED;
}
}
// sbuf is completely accumulated, now copy up to 63 remaining bytes
ctx->sbuf_len = currentlen % ST_MD5_BLOCK_SIZE;
if (ctx->sbuf_len !=0) {
if (ctx->sbuf_len != 0) {
memcpy(ctx->sbuf, input + ilen - ctx->sbuf_len, ctx->sbuf_len);
}
}
@ -174,7 +179,7 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input
return 0;
}
int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] )
int mbedtls_md5_finish_ret(mbedtls_md5_context *ctx, unsigned char output[16])
{
if (st_md5_restore_hw_context(ctx) != 1) {
// Return HASH_BUSY timeout error here
@ -186,7 +191,7 @@ int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] )
return MBEDTLS_ERR_MD5_HW_ACCEL_FAILED;
}
mbedtls_zeroize( ctx->sbuf, ST_MD5_BLOCK_SIZE);
mbedtls_zeroize(ctx->sbuf, ST_MD5_BLOCK_SIZE);
ctx->sbuf_len = 0;
__HAL_HASH_START_DIGEST();

35
features/mbedtls/targets/TARGET_STM/md5_alt.h
View File

@ -41,8 +41,7 @@ extern "C" {
* ST_MD5_BLOCK_SIZE bytes per ST_MD5_BLOCK_SIZE bytes
* If MD5_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_MD5_Finish
*/
typedef struct
{
typedef struct {
HASH_HandleTypeDef hhash_md5;/*!< ST HAL HASH struct */
unsigned char sbuf[ST_MD5_BLOCK_SIZE]; /*!< MBEDTLS_MD5_BLOCK_SIZE buffer to store values so that algorithm is caled once the buffer is filled */
unsigned char sbuf_len; /*!< number of bytes to be processed in sbuf */
@ -57,14 +56,14 @@ mbedtls_md5_context;
*
* \param ctx MD5 context to be initialized
*/
void mbedtls_md5_init( mbedtls_md5_context *ctx );
void mbedtls_md5_init(mbedtls_md5_context *ctx);
/**
* \brief Clear MD5 context
*
* \param ctx MD5 context to be cleared
*/
void mbedtls_md5_free( mbedtls_md5_context *ctx );
void mbedtls_md5_free(mbedtls_md5_context *ctx);
/**
* \brief Clone (the state of) an MD5 context
@ -72,8 +71,8 @@ void mbedtls_md5_free( mbedtls_md5_context *ctx );
* \param dst The destination context
* \param src The context to be cloned
*/
void mbedtls_md5_clone( mbedtls_md5_context *dst,
const mbedtls_md5_context *src );
void mbedtls_md5_clone(mbedtls_md5_context *dst,
const mbedtls_md5_context *src);
/**
* \brief MD5 context setup
@ -82,7 +81,7 @@ void mbedtls_md5_clone( mbedtls_md5_context *dst,
*
* \returns error code
*/
int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx );
int mbedtls_md5_starts_ret(mbedtls_md5_context *ctx);
/**
* \brief MD5 process buffer
@ -93,7 +92,7 @@ int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx );
*
* \returns error code
*/
int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen );
int mbedtls_md5_update_ret(mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen);
/**
* \brief MD5 final digest
@ -103,10 +102,10 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input
*
* \returns error code
*/
int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] );
int mbedtls_md5_finish_ret(mbedtls_md5_context *ctx, unsigned char output[16]);
/* Internal use */
int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE] );
int mbedtls_internal_md5_process(mbedtls_md5_context *ctx, const unsigned char data[ST_MD5_BLOCK_SIZE]);
#if !defined(MBEDTLS_DEPRECATED_REMOVED)
#if defined(MBEDTLS_DEPRECATED_WARNING)
@ -126,7 +125,7 @@ int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_md5_starts( mbedtls_md5_context *ctx );
MBEDTLS_DEPRECATED void mbedtls_md5_starts(mbedtls_md5_context *ctx);
/**
* \brief MD5 process buffer
@ -142,9 +141,9 @@ MBEDTLS_DEPRECATED void mbedtls_md5_starts( mbedtls_md5_context *ctx );
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_md5_update( mbedtls_md5_context *ctx,
const unsigned char *input,
size_t ilen );
MBEDTLS_DEPRECATED void mbedtls_md5_update(mbedtls_md5_context *ctx,
const unsigned char *input,
size_t ilen);
/**
* \brief MD5 final digest
@ -159,8 +158,8 @@ MBEDTLS_DEPRECATED void mbedtls_md5_update( mbedtls_md5_context *ctx,
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_md5_finish( mbedtls_md5_context *ctx,
unsigned char output[16] );
MBEDTLS_DEPRECATED void mbedtls_md5_finish(mbedtls_md5_context *ctx,
unsigned char output[16]);
/**
* \brief MD5 process data block (internal use only)
@ -175,8 +174,8 @@ MBEDTLS_DEPRECATED void mbedtls_md5_finish( mbedtls_md5_context *ctx,
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_md5_process( mbedtls_md5_context *ctx,
const unsigned char data[64] );
MBEDTLS_DEPRECATED void mbedtls_md5_process(mbedtls_md5_context *ctx,
const unsigned char data[64]);
#undef MBEDTLS_DEPRECATED
#endif /* !MBEDTLS_DEPRECATED_REMOVED */

49
features/mbedtls/targets/TARGET_STM/sha1_alt.c
View File

@ -22,8 +22,12 @@
#include "mbedtls/platform.h"
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = (unsigned char *)v;
while (n--) {
*p++ = 0;
}
}
static int st_sha1_restore_hw_context(mbedtls_sha1_context *ctx)
@ -40,7 +44,7 @@ static int st_sha1_restore_hw_context(mbedtls_sha1_context *ctx)
}
HASH->STR = ctx->ctx_save_str;
HASH->CR = (ctx->ctx_save_cr | HASH_CR_INIT);
for (i=0;i<38;i++) {
for (i = 0; i < 38; i++) {
HASH->CSR[i] = ctx->ctx_save_csr[i];
}
return 1;
@ -60,35 +64,36 @@ static int st_sha1_save_hw_context(mbedtls_sha1_context *ctx)
/* allow multi-instance of HASH use: restore context for HASH HW module CR */
ctx->ctx_save_cr = HASH->CR;
ctx->ctx_save_str = HASH->STR;
for (i=0;i<38;i++) {
for (i = 0; i < 38; i++) {
ctx->ctx_save_csr[i] = HASH->CSR[i];
}
return 1;
}
void mbedtls_sha1_init( mbedtls_sha1_context *ctx )
void mbedtls_sha1_init(mbedtls_sha1_context *ctx)
{
mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_context ) );
mbedtls_zeroize(ctx, sizeof(mbedtls_sha1_context));
/* Enable HASH clock */
__HAL_RCC_HASH_CLK_ENABLE();
}
void mbedtls_sha1_free( mbedtls_sha1_context *ctx )
void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_context ) );
}
mbedtls_zeroize(ctx, sizeof(mbedtls_sha1_context));
}
void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
const mbedtls_sha1_context *src )
void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
const mbedtls_sha1_context *src)
{
*dst = *src;
}
int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx )
int mbedtls_sha1_starts_ret(mbedtls_sha1_context *ctx)
{
/* Deinitializes the HASH peripheral */
if (HAL_HASH_DeInit(&ctx->hhash_sha1) == HAL_ERROR) {
@ -109,7 +114,7 @@ int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx )
return 0;
}
int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE] )
int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE])
{
if (st_sha1_restore_hw_context(ctx) != 1) {
// return HASH_BUSY timeout Error here
@ -126,7 +131,7 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned cha
return 0;
}
int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen )
int mbedtls_sha1_update_ret(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
{
int err;
size_t currentlen = ilen;
@ -136,11 +141,11 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp
}
// store mechanism to accumulate ST_SHA1_BLOCK_SIZE bytes (512 bits) in the HW
if (currentlen == 0){ // only change HW status is size if 0
if(ctx->hhash_sha1.Phase == HAL_HASH_PHASE_READY) {
/* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
if (currentlen == 0) { // only change HW status is size if 0
if (ctx->hhash_sha1.Phase == HAL_HASH_PHASE_READY) {
/* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
}
ctx->hhash_sha1.Phase = HAL_HASH_PHASE_PROCESS;
} else if (currentlen < (ST_SHA1_BLOCK_SIZE - ctx->sbuf_len)) {
@ -162,7 +167,7 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp
}
// sbuf is completely accumulated, now copy up to 63 remaining bytes
ctx->sbuf_len = currentlen % ST_SHA1_BLOCK_SIZE;
if (ctx->sbuf_len !=0) {
if (ctx->sbuf_len != 0) {
memcpy(ctx->sbuf, input + ilen - ctx->sbuf_len, ctx->sbuf_len);
}
}
@ -173,7 +178,7 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp
return 0;
}
int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] )
int mbedtls_sha1_finish_ret(mbedtls_sha1_context *ctx, unsigned char output[20])
{
if (st_sha1_restore_hw_context(ctx) != 1) {
// return HASH_BUSY timeout Error here
@ -189,7 +194,7 @@ int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20]
ctx->sbuf_len = 0;
__HAL_HASH_START_DIGEST();
if (HAL_HASH_SHA1_Finish(&ctx->hhash_sha1, output, 10) != 0){
if (HAL_HASH_SHA1_Finish(&ctx->hhash_sha1, output, 10) != 0) {
return MBEDTLS_ERR_SHA1_HW_ACCEL_FAILED;
}
if (st_sha1_save_hw_context(ctx) != 1) {

35
features/mbedtls/targets/TARGET_STM/sha1_alt.h
View File

@ -41,8 +41,7 @@ extern "C" {
* multiples of ST_SHA1_BLOCK_SIZE bytes
* If SHA1_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_SHA1_Finish
*/
typedef struct
{
typedef struct {
unsigned char sbuf[ST_SHA1_BLOCK_SIZE]; /*!< MBEDTLS_SHA1_BLOCK_SIZE buffer to store values so that algorithm is caled once the buffer is filled */
unsigned char sbuf_len; /*!< number of bytes remaining in sbuf to be processed */
HASH_HandleTypeDef hhash_sha1; /*!< ST HAL HASH struct */
@ -57,14 +56,14 @@ mbedtls_sha1_context;
*
* \param ctx SHA-1 context to be initialized
*/
void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
void mbedtls_sha1_init(mbedtls_sha1_context *ctx);
/**
* \brief Clear SHA-1 context
*
* \param ctx SHA-1 context to be cleared
*/
void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
void mbedtls_sha1_free(mbedtls_sha1_context *ctx);
/**
* \brief Clone (the state of) a SHA-1 context
@ -72,8 +71,8 @@ void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
* \param dst The destination context
* \param src The context to be cloned
*/
void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
const mbedtls_sha1_context *src );
void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
const mbedtls_sha1_context *src);
/**
* \brief SHA-1 context setup
@ -82,7 +81,7 @@ void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
*
* \returns error code
*/
int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx );
int mbedtls_sha1_starts_ret(mbedtls_sha1_context *ctx);
/**
* \brief SHA-1 process buffer
@ -93,7 +92,7 @@ int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx );
*
* \returns error code
*/
int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
int mbedtls_sha1_update_ret(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen);
/**
* \brief SHA-1 final digest
@ -103,10 +102,10 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *inp
*
* \returns error code
*/
int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] );
int mbedtls_sha1_finish_ret(mbedtls_sha1_context *ctx, unsigned char output[20]);
/* Internal use */
int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE] );
int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[ST_SHA1_BLOCK_SIZE]);
#if !defined(MBEDTLS_DEPRECATED_REMOVED)
#if defined(MBEDTLS_DEPRECATED_WARNING)
@ -126,7 +125,7 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned cha
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
MBEDTLS_DEPRECATED void mbedtls_sha1_starts(mbedtls_sha1_context *ctx);
/**
* \brief SHA-1 process buffer
@ -142,9 +141,9 @@ MBEDTLS_DEPRECATED void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_sha1_update( mbedtls_sha1_context *ctx,
const unsigned char *input,
size_t ilen );
MBEDTLS_DEPRECATED void mbedtls_sha1_update(mbedtls_sha1_context *ctx,
const unsigned char *input,
size_t ilen);
/**
* \brief SHA-1 final digest
@ -159,8 +158,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha1_update( mbedtls_sha1_context *ctx,
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_sha1_finish( mbedtls_sha1_context *ctx,
unsigned char output[20] );
MBEDTLS_DEPRECATED void mbedtls_sha1_finish(mbedtls_sha1_context *ctx,
unsigned char output[20]);
/**
* \brief SHA-1 process data block (internal use only)
@ -175,8 +174,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha1_finish( mbedtls_sha1_context *ctx,
* stronger message digests instead.
*
*/
MBEDTLS_DEPRECATED void mbedtls_sha1_process( mbedtls_sha1_context *ctx,
const unsigned char data[64] );
MBEDTLS_DEPRECATED void mbedtls_sha1_process(mbedtls_sha1_context *ctx,
const unsigned char data[64]);
#undef MBEDTLS_DEPRECATED
#endif /* !MBEDTLS_DEPRECATED_REMOVED */

45
features/mbedtls/targets/TARGET_STM/sha256_alt.c
View File

@ -23,8 +23,12 @@
#include "mbedtls/platform.h"
/* Implementation that should never be optimized out by the compiler */
static void mbedtls_zeroize( void *v, size_t n ) {
volatile unsigned char *p = v; while( n-- ) *p++ = 0;
static void mbedtls_zeroize(void *v, size_t n)
{
volatile unsigned char *p = v;
while (n--) {
*p++ = 0;
}
}
static int st_sha256_restore_hw_context(mbedtls_sha256_context *ctx)
@ -41,7 +45,7 @@ static int st_sha256_restore_hw_context(mbedtls_sha256_context *ctx)
}
HASH->STR = ctx->ctx_save_str;
HASH->CR = (ctx->ctx_save_cr | HASH_CR_INIT);
for (i=0;i<38;i++) {
for (i = 0; i < 38; i++) {
HASH->CSR[i] = ctx->ctx_save_csr[i];
}
return 1;
@ -61,34 +65,35 @@ static int st_sha256_save_hw_context(mbedtls_sha256_context *ctx)
/* allow multi-instance of HASH use: restore context for HASH HW module CR */
ctx->ctx_save_cr = HASH->CR;
ctx->ctx_save_str = HASH->STR;
for (i=0;i<38;i++) {
for (i = 0; i < 38; i++) {
ctx->ctx_save_csr[i] = HASH->CSR[i];
}
return 1;
}
void mbedtls_sha256_init( mbedtls_sha256_context *ctx )
void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
{
mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_context ) );
mbedtls_zeroize(ctx, sizeof(mbedtls_sha256_context));
/* Enable HASH clock */
__HAL_RCC_HASH_CLK_ENABLE();
}
void mbedtls_sha256_free( mbedtls_sha256_context *ctx )
void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
{
if( ctx == NULL )
if (ctx == NULL) {
return;
mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_context ) );
}
mbedtls_zeroize(ctx, sizeof(mbedtls_sha256_context));
}
void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
const mbedtls_sha256_context *src )
void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
const mbedtls_sha256_context *src)
{
*dst = *src;
}
int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 )
int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224)
{
/* HASH IP initialization */
if (HAL_HASH_DeInit(&ctx->hhash_sha256) == HAL_ERROR) {
@ -111,7 +116,7 @@ int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 )
return 0;
}
int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE] )
int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE])
{
if (st_sha256_restore_hw_context(ctx) != 1) {
// Return HASH_BUSY timeout error here
@ -134,7 +139,7 @@ int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned
return 0;
}
int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen )
int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
{
int err;
size_t currentlen = ilen;
@ -145,7 +150,7 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char
// store mechanism to accumulate ST_SHA256_BLOCK_SIZE bytes (512 bits) in the HW
if (currentlen == 0) { // only change HW status is size if 0
if(ctx->hhash_sha256.Phase == HAL_HASH_PHASE_READY) {
if (ctx->hhash_sha256.Phase == HAL_HASH_PHASE_READY) {
/* Select the SHA256 or SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
if (ctx->is224 == 0) {
@ -169,20 +174,20 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char
}
// Process every input as long as it is %64 bytes, ie 512 bits
size_t iter = currentlen / ST_SHA256_BLOCK_SIZE;
if (iter !=0) {
if (iter != 0) {
if (ctx->is224 == 0) {
if (HAL_HASHEx_SHA256_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) {
if (HAL_HASHEx_SHA256_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) {
return MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED;
}
} else {
if (HAL_HASHEx_SHA224_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) {
if (HAL_HASHEx_SHA224_Accumulate(&ctx->hhash_sha256, (uint8_t *)(input + ST_SHA256_BLOCK_SIZE - ctx->sbuf_len), (iter * ST_SHA256_BLOCK_SIZE)) != 0) {
return MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED;
}
}
}
// sbuf is completely accumulated, now copy up to 63 remaining bytes
ctx->sbuf_len = currentlen % ST_SHA256_BLOCK_SIZE;
if (ctx->sbuf_len !=0) {
if (ctx->sbuf_len != 0) {
memcpy(ctx->sbuf, input + ilen - ctx->sbuf_len, ctx->sbuf_len);
}
}
@ -193,7 +198,7 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char
return 0;
}
int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] )
int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx, unsigned char output[32])
{
if (st_sha256_restore_hw_context(ctx) != 1) {
// Return HASH_BUSY timeout error here

45
features/mbedtls/targets/TARGET_STM/sha256_alt.h
View File

@ -40,10 +40,9 @@ extern "C" {
* ST_SHA256_BLOCK_SIZE bytes per ST_SHA256_BLOCK_SIZE bytes
* If sha256_finish is called and sbuf_len>0, the remaining bytes are accumulated prior to the call to HAL_HASH_SHA256_Finish
*/
typedef struct
{
int is224; /*!< 0 => SHA-256, else SHA-224 */
HASH_HandleTypeDef hhash_sha256;
typedef struct {
int is224; /*!< 0 => SHA-256, else SHA-224 */
HASH_HandleTypeDef hhash_sha256;
unsigned char sbuf[ST_SHA256_BLOCK_SIZE]; /*!< ST_SHA256_BLOCK_SIZE buffer to store values so that algorithm is called once the buffer is filled */
unsigned char sbuf_len; /*!< number of bytes to be processed in sbuf */
uint32_t ctx_save_cr;
@ -57,14 +56,14 @@ mbedtls_sha256_context;
*
* \param ctx SHA-256 context to be initialized
*/
void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
void mbedtls_sha256_init(mbedtls_sha256_context *ctx);
/**
* \brief Clear SHA-256 context
*
* \param ctx SHA-256 context to be cleared
*/
void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
void mbedtls_sha256_free(mbedtls_sha256_context *ctx);
/**
* \brief Clone (the state of) a SHA-256 context
@ -72,8 +71,8 @@ void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
* \param dst The destination context
* \param src The context to be cloned
*/
void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
const mbedtls_sha256_context *src );
void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
const mbedtls_sha256_context *src);
/**
* \brief SHA-256 context setup
@ -83,7 +82,7 @@ void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
*
* \returns error code
*/
int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 );
int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224);
/**
* \brief SHA-256 process buffer
@ -94,9 +93,9 @@ int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 );
*
* \returns error code
*/
int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx,
const unsigned char *input,
size_t ilen );
int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx,
const unsigned char *input,
size_t ilen);
/**
* \brief SHA-256 final digest
@ -106,10 +105,10 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx,
*
* \returns error code
*/
int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] );
int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx, unsigned char output[32]);
/* Internal use */
int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE] );
int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[ST_SHA256_BLOCK_SIZE]);
#if !defined(MBEDTLS_DEPRECATED_REMOVED)
#if defined(MBEDTLS_DEPRECATED_WARNING)
@ -127,8 +126,8 @@ int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned
* <ul><li>0: Use SHA-256.</li>
* <li>1: Use SHA-224.</li></ul>
*/
MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx,
int is224 );
MBEDTLS_DEPRECATED void mbedtls_sha256_starts(mbedtls_sha256_context *ctx,
int is224);
/**
* \brief This function feeds an input buffer into an ongoing
@ -140,9 +139,9 @@ MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx,
* \param input The buffer holding the data.
* \param ilen The length of the input data.
*/
MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx,
const unsigned char *input,
size_t ilen );
MBEDTLS_DEPRECATED void mbedtls_sha256_update(mbedtls_sha256_context *ctx,
const unsigned char *input,
size_t ilen);
/**
* \brief This function finishes the SHA-256 operation, and writes
@ -153,8 +152,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx,
* \param ctx The SHA-256 context.
* \param output The SHA-224or SHA-256 checksum result.
*/
MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx,
unsigned char output[32] );
MBEDTLS_DEPRECATED void mbedtls_sha256_finish(mbedtls_sha256_context *ctx,
unsigned char output[32]);
/**
* \brief This function processes a single data block within
@ -166,8 +165,8 @@ MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx,
* \param ctx The SHA-256 context.
* \param data The buffer holding one block of data.
*/
MBEDTLS_DEPRECATED void mbedtls_sha256_process( mbedtls_sha256_context *ctx,
const unsigned char data[64] );
MBEDTLS_DEPRECATED void mbedtls_sha256_process(mbedtls_sha256_context *ctx,
const unsigned char data[64]);
#undef MBEDTLS_DEPRECATED
#endif /* !MBEDTLS_DEPRECATED_REMOVED */

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f2_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -59,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -79,7 +79,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -88,7 +88,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

5
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F2/stm32f2_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth)
.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
.VLANTagIdentifier = 0x0U
};
};
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;

5
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth)
.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
.VLANTagIdentifier = 0x0U,
};
};
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;

12
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_ARCH_MAX/stm32f4_eth_init.c
View File

@ -3,7 +3,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -20,7 +20,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER --------------------->
RMII_MII_RXER --------------------->
RMII_MII_TX_EN --------------------> PB11
RMII_MII_TXD0 ---------------------> PB12
RMII_MII_TXD1 ---------------------> PB13
@ -28,7 +28,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -44,7 +44,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -53,7 +53,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */
@ -66,7 +66,7 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER --------------------->
RMII_MII_RXER --------------------->
RMII_MII_TX_EN --------------------> PB11
RMII_MII_TXD0 ---------------------> PB12
RMII_MII_TXD1 ---------------------> PB13

5
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth)
.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
.VLANTagIdentifier = 0x0U,
};
};
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F429ZI/stm32f4_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -59,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -79,7 +79,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -88,7 +88,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

5
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth)
.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
.VLANTagIdentifier = 0x0U,
};
};
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F4/TARGET_NUCLEO_F439ZI/stm32f4_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -59,7 +59,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -79,7 +79,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -88,7 +88,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -60,7 +60,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -76,7 +76,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -85,7 +85,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_DISCO_F769NI/stm32f7_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f7_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F756ZG/stm32f7_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

8
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/stm32f7_eth_init.c
View File

@ -33,7 +33,7 @@
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
@ -61,7 +61,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
@ -81,7 +81,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
@ -90,7 +90,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */

5
features/netsocket/emac-drivers/TARGET_STM_EMAC/TARGET_STM32F7/stm32f7_eth_conf.c
View File

@ -18,8 +18,7 @@
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf =
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
@ -49,7 +48,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth)
.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
.VLANTagIdentifier = 0x0
};
};
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;

67
features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.cpp
View File

@ -24,22 +24,22 @@
#define STM_ETH_IF_NAME "st"
#if defined (__ICCARM__) /*!< IAR Compiler */
#pragma data_alignment=4
#pragma data_alignment=4
#endif
__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END; /* Ethernet Rx DMA Descriptor */
#if defined (__ICCARM__) /*!< IAR Compiler */
#pragma data_alignment=4
#pragma data_alignment=4
#endif
__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END; /* Ethernet Tx DMA Descriptor */
#if defined (__ICCARM__) /*!< IAR Compiler */
#pragma data_alignment=4
#pragma data_alignment=4
#endif
__ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */
#if defined (__ICCARM__) /*!< IAR Compiler */
#pragma data_alignment=4
#pragma data_alignment=4
#endif
__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
@ -326,16 +326,16 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
*/
void STM32_EMAC::packet_rx()
{
/* move received packet into a new buf */
while (1) {
emac_mem_buf_t *p = NULL;
if (low_level_input(&p) < 0) {
break;
}
if (p) {
emac_link_input_cb(p);
}
}
/* move received packet into a new buf */
while (1) {
emac_mem_buf_t *p = NULL;
if (low_level_input(&p) < 0) {
break;
}
if (p) {
emac_link_input_cb(p);
}
}
}
/** \brief Worker thread.
@ -344,7 +344,7 @@ void STM32_EMAC::packet_rx()
*
* \param[in] pvParameters pointer to the interface data
*/
void STM32_EMAC::thread_function(void* pvParameters)
void STM32_EMAC::thread_function(void *pvParameters)
{
static struct STM32_EMAC *stm32_enet = static_cast<STM32_EMAC *>(pvParameters);
@ -391,16 +391,16 @@ void STM32_EMAC::phy_task()
*
* \param[in] pvParameters pointer to the interface data
*/
void STM32_EMAC::rmii_watchdog_thread_function(void* pvParameters)
void STM32_EMAC::rmii_watchdog_thread_function(void *pvParameters)
{
struct STM32_EMAC *stm32_enet = static_cast<STM32_EMAC *>(pvParameters);
while(1) {
while (1) {
/* some good packets are received */
if (stm32_enet->EthHandle.Instance->MMCRGUFCR > 0) {
/* RMII Init is OK - would need service to terminate or suspend
* the thread */
while(1) {
while (1) {
/* don't do anything anymore */
osDelay(0xFFFFFFFF);
}
@ -432,7 +432,8 @@ void STM32_EMAC::disable_interrupts(void)
* @param mac A 6-byte array to write the MAC address
*/
void mbed_mac_address(char *mac) {
void mbed_mac_address(char *mac)
{
if (mbed_otp_mac_address(mac)) {
return;
} else {
@ -441,11 +442,13 @@ void mbed_mac_address(char *mac) {
return;
}
__weak uint8_t mbed_otp_mac_address(char *mac) {
__weak uint8_t mbed_otp_mac_address(char *mac)
{
return 0;
}
void mbed_default_mac_address(char *mac) {
void mbed_default_mac_address(char *mac)
{
unsigned char ST_mac_addr[3] = {0x00, 0x80, 0xe1}; // default STMicro mac address
// Read unic id
@ -456,7 +459,7 @@ void mbed_default_mac_address(char *mac) {
#elif defined (TARGET_STM32F7)
uint32_t word0 = *(uint32_t *)0x1FF0F420;
#else
#error MAC address can not be derived from target unique Id
#error MAC address can not be derived from target unique Id
#endif
mac[0] = ST_mac_addr[0];
@ -522,37 +525,37 @@ bool STM32_EMAC::get_hwaddr(uint8_t *addr) const
void STM32_EMAC::set_hwaddr(const uint8_t *addr)
{
/* No-op at this stage */
/* No-op at this stage */
}
void STM32_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
{
emac_link_input_cb = input_cb;
emac_link_input_cb = input_cb;
}
void STM32_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
{
emac_link_state_cb = state_cb;
emac_link_state_cb = state_cb;
}
void STM32_EMAC::add_multicast_group(const uint8_t *addr)
{
/* No-op at this stage */
/* No-op at this stage */
}
void STM32_EMAC::remove_multicast_group(const uint8_t *addr)
{
/* No-op at this stage */
/* No-op at this stage */
}
void STM32_EMAC::set_all_multicast(bool all)
{
/* No-op at this stage */
/* No-op at this stage */
}
void STM32_EMAC::power_down()
{
/* No-op at this stage */
/* No-op at this stage */
}
void STM32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
@ -560,12 +563,14 @@ void STM32_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
memory_manager = &mem_mngr;
}
STM32_EMAC &STM32_EMAC::get_instance() {
STM32_EMAC &STM32_EMAC::get_instance()
{
static STM32_EMAC emac;
return emac;
}
// Weak so a module can override
MBED_WEAK EMAC &EMAC::get_default_instance() {
MBED_WEAK EMAC &EMAC::get_default_instance()
{
return STM32_EMAC::get_instance();
}

4
features/netsocket/emac-drivers/TARGET_STM_EMAC/stm32xx_emac.h
View File

@ -155,8 +155,8 @@ private:
bool low_level_init_successful();
void packet_rx();
int low_level_input(emac_mem_buf_t **buf);
static void thread_function(void* pvParameters);
static void rmii_watchdog_thread_function(void* pvParameters);
static void thread_function(void *pvParameters);
static void rmii_watchdog_thread_function(void *pvParameters);
void phy_task();
void enable_interrupts();
void disable_interrupts();

16
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h
View File

@ -42,8 +42,7 @@
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
typedef struct {
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
@ -71,10 +70,10 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
return 1024;
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN;
void (USBHAL::*func)(int frame) = priv->sof;
(obj->*func)(sofnum);
@ -92,8 +91,9 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
USBHAL *USBHAL::instance;
USBHAL::USBHAL(void) {
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
USBHAL::USBHAL(void)
{
USBHAL_Private_t *HALPriv = new (USBHAL_Private_t);
hpcd.Instance = USB;
@ -151,7 +151,7 @@ USBHAL::USBHAL(void) {
__HAL_RCC_SYSCFG_CLK_ENABLE();
// Configure PCD and FIFOs
hpcd.pData = (void*)HALPriv;
hpcd.pData = (void *)HALPriv;
hpcd.State = HAL_PCD_STATE_RESET;
HAL_PCD_Init(&hpcd);

19
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
View File

@ -44,8 +44,7 @@
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
typedef struct {
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
@ -71,17 +70,16 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
uint32_t len;
if (fifo == 0) {
len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ >> 16;
}
else {
} else {
len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
}
return len * 4;
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
void (USBHAL::*func)(int frame) = priv->sof;
@ -90,8 +88,9 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
USBHAL *USBHAL::instance;
USBHAL::USBHAL(void) {
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
USBHAL::USBHAL(void)
{
USBHAL_Private_t *HALPriv = new (USBHAL_Private_t);
memset(&hpcd.Init, 0, sizeof(hpcd.Init));
@ -215,7 +214,7 @@ USBHAL::USBHAL(void) {
__HAL_RCC_SYSCFG_CLK_ENABLE();
// Configure PCD and FIFOs
hpcd.pData = (void*)HALPriv;
hpcd.pData = (void *)HALPriv;
hpcd.State = HAL_PCD_STATE_RESET;
HAL_PCD_Init(&hpcd);

255
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp
View File

@ -42,13 +42,13 @@
/* this call at device reception completion on a Out Enpoint */
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
uint8_t endpoint = ADDR_EPOUT(epnum);
priv->epComplete[endpoint] = 1;
/* -2 endpoint 0 In out are not in call back list */
if (epnum) {
bool (USBHAL::*func)(void) = priv->epCallback[endpoint-2];
bool (USBHAL::*func)(void) = priv->epCallback[endpoint - 2];
(obj->*func)();
} else {
void (USBHAL::*func)(void) = priv->ep0_out;
@ -59,13 +59,13 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
/* this is call at device transmission completion on In endpoint */
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
uint8_t endpoint = ADDR_EPIN(epnum);
priv->epComplete[endpoint] = 1;
/* -2 endpoint 0 In out are not in call back list */
if (epnum) {
bool (USBHAL::*func)(void) = priv->epCallback[endpoint-2];
bool (USBHAL::*func)(void) = priv->epCallback[endpoint - 2];
(obj->*func)();
} else {
void (USBHAL::*func)(void) = priv->ep0_in;
@ -75,158 +75,172 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
/* This is call at device set up reception */
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
void (USBHAL::*func)(void)=priv->ep0_setup;
void (USBHAL::*func1)(void)=priv->ep0_read;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
void (USBHAL::*func)(void) = priv->ep0_setup;
void (USBHAL::*func1)(void) = priv->ep0_read;
(obj->*func)();
(obj->*func1)();
}
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->suspend_change;
(obj->*func)(1);
}
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->suspend_change;
(obj->*func)(0);
}
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->connect_change;
(obj->*func)(1);
}
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->connect_change;
(obj->*func)(0);
}
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj = priv->inst;
unsigned int i;
for(i=0;i<hpcd->Init.dev_endpoints;i++) {
priv->epComplete[2*i]=0;
HAL_PCD_EP_Close(hpcd,EP_ADDR(2*i));
HAL_PCD_EP_Flush(hpcd,EP_ADDR(2*i));
priv->epComplete[2*i+1]=0;
HAL_PCD_EP_Close(hpcd,EP_ADDR(2*i+1));
HAL_PCD_EP_Flush(hpcd,EP_ADDR(2*i+1));
for (i = 0; i < hpcd->Init.dev_endpoints; i++) {
priv->epComplete[2 * i] = 0;
HAL_PCD_EP_Close(hpcd, EP_ADDR(2 * i));
HAL_PCD_EP_Flush(hpcd, EP_ADDR(2 * i));
priv->epComplete[2 * i + 1] = 0;
HAL_PCD_EP_Close(hpcd, EP_ADDR(2 * i + 1));
HAL_PCD_EP_Flush(hpcd, EP_ADDR(2 * i + 1));
}
void (USBHAL::*func)(void)=priv->bus_reset;
void (USBHAL::*func)(void) = priv->bus_reset;
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) = priv->ep_realise;
(obj->*func)();
(obj->*ep_realise)(EP0IN, MAX_PACKET_SIZE_EP0,0);
(obj->*ep_realise)(EP0OUT, MAX_PACKET_SIZE_EP0,0);
(obj->*ep_realise)(EP0IN, MAX_PACKET_SIZE_EP0, 0);
(obj->*ep_realise)(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
}
/* hal pcd handler , used for STM32 HAL PCD Layer */
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
{
return 0;
}
USBHAL::~USBHAL(void) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_PCD_DeInit(&hpcd);
delete HALPriv;
USBHAL::~USBHAL(void)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_PCD_DeInit(&hpcd);
delete HALPriv;
}
void USBHAL::connect(void) {
void USBHAL::connect(void)
{
NVIC_EnableIRQ(USBHAL_IRQn);
}
void USBHAL::disconnect(void) {
void USBHAL::disconnect(void)
{
NVIC_DisableIRQ(USBHAL_IRQn);
}
void USBHAL::configureDevice(void) {
void USBHAL::configureDevice(void)
{
// Not needed
}
void USBHAL::unconfigureDevice(void) {
void USBHAL::unconfigureDevice(void)
{
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
HAL_PCD_SetAddress(&hpcd, address);
void USBHAL::setAddress(uint8_t address)
{
HAL_PCD_SetAddress(&hpcd, address);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags)
{
uint32_t epIndex = EP_ADDR(endpoint);
uint32_t type;
uint32_t len;
HAL_StatusTypeDef ret;
switch (endpoint) {
case EP0IN:
case EP0OUT:
type = 0;
break;
case EPISO_IN:
case EPISO_OUT:
type = 1;
break;
case EPBULK_IN:
case EPBULK_OUT:
type = 2;
break;
case EPINT_IN:
case EPINT_OUT:
type = 3;
break;
case EP0IN:
case EP0OUT:
type = 0;
break;
case EPISO_IN:
case EPISO_OUT:
type = 1;
break;
case EPBULK_IN:
case EPBULK_OUT:
type = 2;
break;
case EPINT_IN:
case EPINT_OUT:
type = 3;
break;
}
if (maxPacket > MAXTRANSFER_SIZE) {
return false;
}
if (maxPacket > MAXTRANSFER_SIZE) return false;
if (epIndex & 0x80) {
len = HAL_PCDEx_GetTxFiFo(&hpcd,epIndex & 0x7f);
len = HAL_PCDEx_GetTxFiFo(&hpcd, epIndex & 0x7f);
MBED_ASSERT(len >= maxPacket);
}
ret = HAL_PCD_EP_Open(&hpcd, epIndex, maxPacket, type);
MBED_ASSERT(ret!=HAL_BUSY);
return (ret == HAL_OK) ? true:false;
MBED_ASSERT(ret != HAL_BUSY);
return (ret == HAL_OK) ? true : false;
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
void USBHAL::EP0setup(uint8_t *buffer)
{
memcpy(buffer, hpcd.Setup, MAX_PACKET_SIZE_SETUP);
memset(hpcd.Setup,0,MAX_PACKET_SIZE_SETUP);
memset(hpcd.Setup, 0, MAX_PACKET_SIZE_SETUP);
}
void USBHAL::EP0readStage(void) {
void USBHAL::EP0readStage(void)
{
}
void USBHAL::EP0read(void) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t epIndex = EP_ADDR(EP0OUT);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0;
HAL_StatusTypeDef ret;
HALPriv->epComplete[EP0OUT] = 2;
ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, MAX_PACKET_SIZE_EP0 );
MBED_ASSERT(ret!=HAL_BUSY);
void USBHAL::EP0read(void)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t epIndex = EP_ADDR(EP0OUT);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0;
HAL_StatusTypeDef ret;
HALPriv->epComplete[EP0OUT] = 2;
ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, MAX_PACKET_SIZE_EP0);
MBED_ASSERT(ret != HAL_BUSY);
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, 0);
HALPriv->epComplete[EP0OUT] = 0;
HALPriv->epComplete[EP0OUT] = 0;
if (length) {
uint8_t *buff = (uint8_t *)HALPriv->pBufRx0;
memcpy(buffer, buff, length);
@ -234,97 +248,114 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
/* check that endpoint maximum size is not exceeding TX fifo */
MBED_ASSERT(hpcd.IN_ep[0].maxpacket >= size);
endpointWrite(EP0IN, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
void USBHAL::EP0getWriteResult(void)
{
}
void USBHAL::EP0stall(void) {
void USBHAL::EP0stall(void)
{
stallEndpoint(EP0IN);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t* pBuf = (uint8_t *)HALPriv->pBufRx;
HAL_StatusTypeDef ret;
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx;
HAL_StatusTypeDef ret;
// clean reception end flag before requesting reception
HALPriv->epComplete[endpoint] = 2;
ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, maximumSize);
MBED_ASSERT(ret!=HAL_BUSY);
MBED_ASSERT(ret != HAL_BUSY);
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint]==0) {
/* no reception possible !!! */
bytesRead = 0;
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 0) {
/* no reception possible !!! */
bytesRead = 0;
return EP_COMPLETED;
}else if ((HALPriv->epComplete[endpoint]!=1))
return EP_PENDING;
} else if ((HALPriv->epComplete[endpoint] != 1)) {
return EP_PENDING;
}
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t *buff = (uint8_t *)HALPriv->pBufRx;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, epIndex);
memcpy(buffer, buff, length);
*bytesRead = length;
HALPriv->epComplete[endpoint]= 0;
HALPriv->epComplete[endpoint] = 0;
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
HAL_StatusTypeDef ret;
// clean transmission end flag before requesting transmission
HALPriv->epComplete[endpoint] = 2;
ret = HAL_PCD_EP_Transmit(&hpcd, epIndex, data, size);
MBED_ASSERT(ret!=HAL_BUSY);
MBED_ASSERT(ret != HAL_BUSY);
// update the status
if (ret != HAL_OK) return EP_INVALID;
if (ret != HAL_OK) {
return EP_INVALID;
}
// fix me return is too simple
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 1)
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 1) {
return EP_COMPLETED;
}
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_StatusTypeDef ret;
HALPriv->epComplete[endpoint] = 0;
ret = HAL_PCD_EP_SetStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret!=HAL_BUSY);
void USBHAL::stallEndpoint(uint8_t endpoint)
{
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_StatusTypeDef ret;
HALPriv->epComplete[endpoint] = 0;
ret = HAL_PCD_EP_SetStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret != HAL_BUSY);
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
HAL_StatusTypeDef ret;
void USBHAL::unstallEndpoint(uint8_t endpoint)
{
HAL_StatusTypeDef ret;
ret = HAL_PCD_EP_ClrStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret!=HAL_BUSY);
MBED_ASSERT(ret != HAL_BUSY);
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
bool USBHAL::getEndpointStallState(uint8_t endpoint)
{
return false;
}
void USBHAL::remoteWakeup(void) {
void USBHAL::remoteWakeup(void)
{
}
void USBHAL::_usbisr(void) {
void USBHAL::_usbisr(void)
{
instance->usbisr();
}
void USBHAL::usbisr(void) {
void USBHAL::usbisr(void)
{
HAL_PCD_IRQHandler(&instance->hpcd);
}

106
features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F4.cpp
View File

@ -22,7 +22,7 @@
#include "USBRegs_STM32.h"
#include "pinmap.h"
USBHAL * USBHAL::instance;
USBHAL *USBHAL::instance;
static volatile int epComplete = 0;
@ -32,11 +32,13 @@ static uint32_t rxFifoCount = 0;
static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer)
{
return 0;
}
USBHAL::USBHAL(void) {
USBHAL::USBHAL(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP1_IN_callback;
@ -94,32 +96,39 @@ USBHAL::USBHAL(void) {
NVIC_SetPriority(OTG_FS_IRQn, 1);
}
USBHAL::~USBHAL(void) {
USBHAL::~USBHAL(void)
{
}
void USBHAL::connect(void) {
void USBHAL::connect(void)
{
NVIC_EnableIRQ(OTG_FS_IRQn);
}
void USBHAL::disconnect(void) {
void USBHAL::disconnect(void)
{
NVIC_DisableIRQ(OTG_FS_IRQn);
}
void USBHAL::configureDevice(void) {
void USBHAL::configureDevice(void)
{
// Not needed
}
void USBHAL::unconfigureDevice(void) {
void USBHAL::unconfigureDevice(void)
{
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
void USBHAL::setAddress(uint8_t address)
{
OTG_FS->DREGS.DCFG |= (address << 4);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
uint32_t flags) {
uint32_t flags)
{
uint32_t epIndex = endpoint >> 1;
uint32_t type;
@ -151,8 +160,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
if (endpoint == EP0IN) {
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
else {
} else {
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
@ -169,8 +177,7 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
}
else { // Out endpoint
} else { // Out endpoint
// Set the out EP specific control settings
control |= (1 << 26); // CNAK
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
@ -182,18 +189,22 @@ bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
void USBHAL::EP0setup(uint8_t *buffer)
{
memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
}
void USBHAL::EP0readStage(void) {
void USBHAL::EP0readStage(void)
{
}
void USBHAL::EP0read(void) {
void USBHAL::EP0read(void)
{
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t* buffer32 = (uint32_t *) buffer;
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
{
uint32_t *buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
buffer32[i >> 2] = OTG_FS->FIFO[0][0];
@ -203,14 +214,17 @@ uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
{
endpointWrite(0, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
void USBHAL::EP0getWriteResult(void)
{
}
void USBHAL::EP0stall(void) {
void USBHAL::EP0stall(void)
{
// If we stall the out endpoint here then we have problems transferring
// and setup requests after the (stalled) get device qualifier requests.
// TODO: Find out if this is correct behavior, or whether we are doing
@ -219,12 +233,13 @@ void USBHAL::EP0stall(void) {
// stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
{
uint32_t epIndex = endpoint >> 1;
uint32_t size = (1 << 19) | // 1 packet
(maximumSize << 0); // Packet size
// if (endpoint == EP0OUT) {
size |= (1 << 29); // 1 setup packet
size |= (1 << 29); // 1 setup packet
// }
OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
@ -234,12 +249,13 @@ EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead)
{
if (!(epComplete & (1 << endpoint))) {
return EP_PENDING;
}
uint32_t* buffer32 = (uint32_t *) buffer;
uint32_t *buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
@ -249,7 +265,8 @@ EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
{
uint32_t epIndex = endpoint >> 1;
OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
(size << 0); // Size of packet
@ -259,7 +276,7 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
for (uint32_t i = 0; i < (size + 3) >> 2; i++, data += 4) {
OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
}
@ -268,7 +285,8 @@ EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
{
if (epComplete & (1 << endpoint)) {
epComplete &= ~(1 << endpoint);
return EP_COMPLETED;
@ -277,36 +295,41 @@ EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
void USBHAL::stallEndpoint(uint8_t endpoint)
{
if (endpoint & 0x1) { // In EP
OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
else { // Out EP
} else { // Out EP
OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
void USBHAL::unstallEndpoint(uint8_t endpoint)
{
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
bool USBHAL::getEndpointStallState(uint8_t endpoint)
{
return false;
}
void USBHAL::remoteWakeup(void) {
void USBHAL::remoteWakeup(void)
{
}
void USBHAL::_usbisr(void) {
void USBHAL::_usbisr(void)
{
instance->usbisr();
}
void USBHAL::usbisr(void) {
void USBHAL::usbisr(void)
{
if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
suspendStateChanged(1);
};
@ -347,7 +370,7 @@ void USBHAL::usbisr(void) {
if (type == 0x6) {
// Setup packet
for (uint32_t i=0; i<length; i+=4) {
for (uint32_t i = 0; i < length; i += 4) {
setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
}
rxFifoCount = 0;
@ -363,8 +386,7 @@ void USBHAL::usbisr(void) {
// Out packet
if (endpoint == EP0OUT) {
EP0out();
}
else {
} else {
epComplete |= (1 << endpoint);
if ((instance->*(epCallback[endpoint - 2]))()) {
epComplete &= ~(1 << endpoint);
@ -372,7 +394,7 @@ void USBHAL::usbisr(void) {
}
}
for (uint32_t i=0; i<rxFifoCount; i+=4) {
for (uint32_t i = 0; i < rxFifoCount; i += 4) {
(void) OTG_FS->FIFO[0][0];
}
OTG_FS->GREGS.GINTSTS = (1 << 4);
@ -380,7 +402,7 @@ void USBHAL::usbisr(void) {
if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
// Loop through the in endpoints
for (uint32_t i=0; i<4; i++) {
for (uint32_t i = 0; i < 4; i++) {
if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty

139
features/unsupported/USBDevice/targets/TARGET_STM/USBRegs_STM32.h
View File

@ -28,97 +28,90 @@
#ifndef __USB_OTG_REGS_H__
#define __USB_OTG_REGS_H__
typedef struct //000h
{
__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
__IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
__IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
__IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
__IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
uint32_t Reserved30[2]; /* Reserved 030h*/
__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
__IO uint32_t CID; /* User ID Register 03Ch*/
uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
__IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
typedef struct { //000h
__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
__IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
__IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
__IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
__IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
uint32_t Reserved30[2]; /* Reserved 030h*/
__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
__IO uint32_t CID; /* User ID Register 03Ch*/
uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
__IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
}
USB_OTG_GREGS;
typedef struct // 800h
{
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
uint32_t Reserved0C; /* Reserved 80Ch*/
__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
uint32_t Reserved20; /* Reserved 820h*/
uint32_t Reserved9; /* Reserved 824h*/
__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
__IO uint32_t DTHRCTL; /* dev thr 830h*/
__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
typedef struct { // 800h
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
uint32_t Reserved0C; /* Reserved 80Ch*/
__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
uint32_t Reserved20; /* Reserved 820h*/
uint32_t Reserved9; /* Reserved 824h*/
__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
__IO uint32_t DTHRCTL; /* dev thr 830h*/
__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
}
USB_OTG_DREGS;
typedef struct
{
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
uint32_t Reserved14;
__IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
typedef struct {
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
uint32_t Reserved14;
__IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
}
USB_OTG_INEPREGS;
typedef struct
{
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
uint32_t Reserved14[3];
typedef struct {
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
uint32_t Reserved14[3];
}
USB_OTG_OUTEPREGS;
typedef struct
{
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /* Reserved 40Ch*/
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
typedef struct {
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /* Reserved 40Ch*/
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
}
USB_OTG_HREGS;
typedef struct
{
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
__IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ;
uint32_t Reserved[3];
typedef struct {
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
__IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ;
uint32_t Reserved[3];
}
USB_OTG_HC_REGS;
typedef struct
{
typedef struct {
USB_OTG_GREGS GREGS;
uint32_t RESERVED0[188];
USB_OTG_HREGS HREGS;

54
features/unsupported/USBHost/targets/TARGET_STM/USBEndpoint_STM.cpp
View File

@ -19,13 +19,13 @@
#include "USBEndpoint.h"
extern uint32_t HAL_HCD_HC_GetMaxPacket(HCD_HandleTypeDef *hhcd, uint8_t chn_num);
extern uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd, uint8_t chn_num);
extern void HAL_HCD_DisableInt(HCD_HandleTypeDef* hhcd, uint8_t chn_num);
extern void HAL_HCD_EnableInt(HCD_HandleTypeDef* hhcd, uint8_t chn_num);
extern void HAL_HCD_DisableInt(HCD_HandleTypeDef *hhcd, uint8_t chn_num);
extern void HAL_HCD_EnableInt(HCD_HandleTypeDef *hhcd, uint8_t chn_num);
void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD* td_list_[2])
void USBEndpoint::init(HCED *hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD *td_list_[2])
{
HCD_HandleTypeDef *hhcd;
uint32_t *addr;
@ -36,7 +36,7 @@ void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir
setup = (type == CONTROL_ENDPOINT) ? true : false;
//TDs have been allocated by the host
memcpy((HCTD**)td_list, td_list_, sizeof(HCTD*)*2); //TODO: Maybe should add a param for td_list size... at least a define
memcpy((HCTD **)td_list, td_list_, sizeof(HCTD *) * 2); //TODO: Maybe should add a param for td_list size... at least a define
memset(td_list_[0], 0, sizeof(HCTD));
memset(td_list_[1], 0, sizeof(HCTD));
@ -56,11 +56,11 @@ void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir
/* remove potential post pending from previous endpoint */
ep_queue.get(0);
intf_nb = 0;
hhcd = (HCD_HandleTypeDef*)hced->hhcd;
hhcd = (HCD_HandleTypeDef *)hced->hhcd;
addr = &((uint32_t *)hhcd->pData)[hced->ch_num];
*addr = 0;
state = USB_TYPE_IDLE;
speed =false;
speed = false;
}
void USBEndpoint::setSize(uint32_t size)
{
@ -77,7 +77,7 @@ void USBEndpoint::setDeviceAddress(uint8_t addr)
if (this->speed) {
USB_WARN("small speed device on hub not supported");
}
MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef*)hced->hhcd,hced->ch_num, address, addr, hcd_speed, type, size)!=HAL_BUSY);
MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num, address, addr, hcd_speed, type, size) != HAL_BUSY);
this->device_address = addr;
}
@ -98,26 +98,26 @@ void USBEndpoint::setState(USB_TYPE st)
state = st;
if (st == USB_TYPE_FREE) {
HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef*)hced->hhcd;
HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)hced->hhcd;
uint32_t *addr = &((uint32_t *)hhcd->pData)[hced->ch_num];
if ((*addr) && (type != INTERRUPT_ENDPOINT)) {
this->ep_queue.put((uint8_t*)1);
this->ep_queue.put((uint8_t *)1);
}
MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num)!=HAL_BUSY);
HAL_HCD_DisableInt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num);
MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num) != HAL_BUSY);
HAL_HCD_DisableInt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num);
*addr = 0;
}
if (st == USB_TYPE_ERROR) {
MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num)!=HAL_BUSY);
HAL_HCD_DisableInt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num);
MBED_ASSERT(HAL_HCD_HC_Halt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num) != HAL_BUSY);
HAL_HCD_DisableInt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num);
}
if (st == USB_TYPE_ERROR) {
uint8_t hcd_speed = HCD_SPEED_FULL;
/* small speed device with hub not supported
if (this->speed) hcd_speed = HCD_SPEED_LOW;*/
MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef*)hced->hhcd,hced->ch_num, address, 0, hcd_speed, type, size)!=HAL_BUSY);
MBED_ASSERT(HAL_HCD_HC_Init((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num, address, 0, hcd_speed, type, size) != HAL_BUSY);
}
}
@ -128,7 +128,7 @@ extern uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd, uint8_t chn_num);
USB_TYPE USBEndpoint::queueTransfer()
{
HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef*)hced->hhcd;
HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)hced->hhcd;
uint32_t *addr = &((uint32_t *)hhcd->pData)[hced->ch_num];
uint32_t type = HAL_HCD_HC_GetType(hhcd, hced->ch_num);
uint32_t max_size = HAL_HCD_HC_GetMaxPacket(hhcd, hced->ch_num);
@ -138,14 +138,14 @@ USB_TYPE USBEndpoint::queueTransfer()
return USB_TYPE_FREE;
}
ep_queue.get(0);
MBED_ASSERT(*addr ==0);
MBED_ASSERT(*addr == 0);
transfer_len = td_current->size <= max_size ? td_current->size : max_size;
buf_start = (uint8_t *)td_current->currBufPtr;
//Now add this free TD at this end of the queue
state = USB_TYPE_PROCESSING;
/* one request */
td_current->nextTD = (hcTd*)0;
td_current->nextTD = (hcTd *)0;
#if defined(MAX_NYET_RETRY)
td_current->retry = 0;
#endif
@ -154,28 +154,28 @@ USB_TYPE USBEndpoint::queueTransfer()
/* dir /setup is inverted for ST */
/* token is useful only ctrl endpoint */
/* last parameter is ping ? */
MBED_ASSERT(HAL_HCD_HC_SubmitRequest((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num, dir-1, type,!setup,(uint8_t*) td_current->currBufPtr, transfer_len, 0)==HAL_OK);
HAL_HCD_EnableInt((HCD_HandleTypeDef*)hced->hhcd, hced->ch_num);
MBED_ASSERT(HAL_HCD_HC_SubmitRequest((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num, dir - 1, type, !setup, (uint8_t *) td_current->currBufPtr, transfer_len, 0) == HAL_OK);
HAL_HCD_EnableInt((HCD_HandleTypeDef *)hced->hhcd, hced->ch_num);
return USB_TYPE_PROCESSING;
}
void USBEndpoint::unqueueTransfer(volatile HCTD * td)
void USBEndpoint::unqueueTransfer(volatile HCTD *td)
{
if (state==USB_TYPE_FREE) {
if (state == USB_TYPE_FREE) {
return;
}
uint32_t *addr = &((uint32_t *)((HCD_HandleTypeDef*)hced->hhcd)->pData)[hced->ch_num];
td->state=0;
td->currBufPtr=0;
td->size=0;
td->nextTD=0;
uint32_t *addr = &((uint32_t *)((HCD_HandleTypeDef *)hced->hhcd)->pData)[hced->ch_num];
td->state = 0;
td->currBufPtr = 0;
td->size = 0;
td->nextTD = 0;
*addr = 0;
td_current = td_next;
td_next = td;
}
void USBEndpoint::queueEndpoint(USBEndpoint * ed)
void USBEndpoint::queueEndpoint(USBEndpoint *ed)
{
nextEp = ed;
}

82
features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.cpp
View File

@ -24,63 +24,63 @@
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
USBHALHost_Private_t *priv=(USBHALHost_Private_t *)(hhcd->pData);
USBHALHost *obj= priv->inst;
void (USBHALHost::*func)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent ) = priv->deviceConnected;
(obj->*func)(0,1,0,NULL);
USBHALHost_Private_t *priv = (USBHALHost_Private_t *)(hhcd->pData);
USBHALHost *obj = priv->inst;
void (USBHALHost::*func)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent) = priv->deviceConnected;
(obj->*func)(0, 1, 0, NULL);
}
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
USBHALHost_Private_t *priv=(USBHALHost_Private_t *)(hhcd->pData);
USBHALHost *obj= priv->inst;
void (USBHALHost::*func1)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr)= priv->deviceDisconnected;
(obj->*func1)(0,1,(USBHostHub *)NULL,0);
USBHALHost_Private_t *priv = (USBHALHost_Private_t *)(hhcd->pData);
USBHALHost *obj = priv->inst;
void (USBHALHost::*func1)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr) = priv->deviceDisconnected;
(obj->*func1)(0, 1, (USBHostHub *)NULL, 0);
}
int HAL_HCD_HC_GetDirection(HCD_HandleTypeDef *hhcd,uint8_t chnum)
int HAL_HCD_HC_GetDirection(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
/* useful for transmission */
return hhcd->hc[chnum].ep_is_in;
}
uint32_t HAL_HCD_HC_GetMaxPacket(HCD_HandleTypeDef *hhcd,uint8_t chnum)
uint32_t HAL_HCD_HC_GetMaxPacket(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
/* useful for transmission */
return hhcd->hc[chnum].max_packet;
}
void HAL_HCD_EnableInt(HCD_HandleTypeDef *hhcd,uint8_t chnum)
void HAL_HCD_EnableInt(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
USBx_HOST->HAINTMSK |= (1 << chnum);
}
void HAL_HCD_DisableInt(HCD_HandleTypeDef *hhcd,uint8_t chnum)
void HAL_HCD_DisableInt(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
USBx_HOST->HAINTMSK &= ~(1 << chnum);
}
uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd,uint8_t chnum)
uint32_t HAL_HCD_HC_GetType(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
/* useful for transmission */
return hhcd->hc[chnum].ep_type;
}
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum, HCD_URBStateTypeDef urb_state)
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
USBHALHost_Private_t *priv=(USBHALHost_Private_t *)(hhcd->pData);
USBHALHost *obj= priv->inst;
void (USBHALHost::*func)(volatile uint32_t addr)= priv->transferCompleted;
USBHALHost_Private_t *priv = (USBHALHost_Private_t *)(hhcd->pData);
USBHALHost *obj = priv->inst;
void (USBHALHost::*func)(volatile uint32_t addr) = priv->transferCompleted;
uint32_t addr = priv->addr[chnum];
uint32_t max_size = HAL_HCD_HC_GetMaxPacket(hhcd, chnum);
uint32_t type = HAL_HCD_HC_GetType(hhcd, chnum);
uint32_t dir = HAL_HCD_HC_GetDirection(hhcd,chnum);
uint32_t dir = HAL_HCD_HC_GetDirection(hhcd, chnum);
uint32_t length;
if ( (addr!=0)) {
if ((addr != 0)) {
HCTD *td = (HCTD *)addr;
if ((type == EP_TYPE_BULK) || (type == EP_TYPE_CTRL )) {
if ((type == EP_TYPE_BULK) || (type == EP_TYPE_CTRL)) {
switch (urb_state) {
case URB_DONE:
#if defined(MAX_NYET_RETRY)
@ -91,7 +91,7 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum,
td->currBufPtr += max_size;
td->size -= max_size;
length = td->size <= max_size ? td->size : max_size;
MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir ,type , !td->setup,(uint8_t*) td->currBufPtr, length, 0)==HAL_OK);
MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir, type, !td->setup, (uint8_t *) td->currBufPtr, length, 0) == HAL_OK);
HAL_HCD_EnableInt(hhcd, chnum);
return;
}
@ -106,7 +106,7 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum,
td->retry++;
#endif
length = td->size <= max_size ? td->size : max_size;
MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir ,type , !td->setup,(uint8_t*) td->currBufPtr, length, 0)==HAL_OK);
MBED_ASSERT(HAL_HCD_HC_SubmitRequest(hhcd, chnum, dir, type, !td->setup, (uint8_t *) td->currBufPtr, length, 0) == HAL_OK);
HAL_HCD_EnableInt(hhcd, chnum);
return;
#if defined(MAX_NYET_RETRY)
@ -117,25 +117,25 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,uint8_t chnum,
break;
}
}
if ((type == EP_TYPE_INTR) ) {
if ((type == EP_TYPE_INTR)) {
/* reply a packet of length NULL, this will be analyse in call back
* for mouse or hub */
td->state =USB_TYPE_IDLE ;
td->state = USB_TYPE_IDLE ;
HAL_HCD_DisableInt(hhcd, chnum);
} else {
td->state = (urb_state == URB_DONE) ? USB_TYPE_IDLE : USB_TYPE_ERROR;
}
td->currBufPtr +=HAL_HCD_HC_GetXferCount(hhcd, chnum);
td->currBufPtr += HAL_HCD_HC_GetXferCount(hhcd, chnum);
(obj->*func)(addr);
} else {
if (urb_state !=0) {
USB_DBG_EVENT("spurious %d %d",chnum, urb_state);
if (urb_state != 0) {
USB_DBG_EVENT("spurious %d %d", chnum, urb_state);
}
}
}
USBHALHost * USBHALHost::instHost;
USBHALHost *USBHALHost::instHost;
void USBHALHost::init()
@ -209,37 +209,37 @@ bool USBHALHost::disableList(ENDPOINT_TYPE type)
void USBHALHost::memInit()
{
usb_hcca = (volatile HCD_HandleTypeDef *)usb_buf;
usb_hcca = (volatile HCD_HandleTypeDef *)usb_buf;
usb_edBuf = usb_buf + HCCA_SIZE;
usb_tdBuf = usb_buf + HCCA_SIZE +(MAX_ENDPOINT*ED_SIZE);
usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT * ED_SIZE);
/* init channel */
memset((void*)usb_buf,0, TOTAL_SIZE);
for (int i=0; i < MAX_ENDPOINT; i++) {
HCED *hced = (HCED*)(usb_edBuf + i*ED_SIZE);
memset((void *)usb_buf, 0, TOTAL_SIZE);
for (int i = 0; i < MAX_ENDPOINT; i++) {
HCED *hced = (HCED *)(usb_edBuf + i * ED_SIZE);
hced->ch_num = i;
hced->hhcd = (HCCA *) usb_hcca;
}
}
volatile uint8_t * USBHALHost::getED()
volatile uint8_t *USBHALHost::getED()
{
for (int i = 0; i < MAX_ENDPOINT; i++) {
if ( !edBufAlloc[i] ) {
if (!edBufAlloc[i]) {
edBufAlloc[i] = true;
return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
return (volatile uint8_t *)(usb_edBuf + i * ED_SIZE);
}
}
perror("Could not allocate ED\r\n");
return NULL; //Could not alloc ED
}
volatile uint8_t * USBHALHost::getTD()
volatile uint8_t *USBHALHost::getTD()
{
int i;
for (i = 0; i < MAX_TD; i++) {
if ( !tdBufAlloc[i] ) {
if (!tdBufAlloc[i]) {
tdBufAlloc[i] = true;
return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
return (volatile uint8_t *)(usb_tdBuf + i * TD_SIZE);
}
}
perror("Could not allocate TD\r\n");
@ -247,14 +247,14 @@ volatile uint8_t * USBHALHost::getTD()
}
void USBHALHost::freeED(volatile uint8_t * ed)
void USBHALHost::freeED(volatile uint8_t *ed)
{
int i;
i = (ed - usb_edBuf) / ED_SIZE;
edBufAlloc[i] = false;
}
void USBHALHost::freeTD(volatile uint8_t * td)
void USBHALHost::freeTD(volatile uint8_t *td)
{
int i;
i = (td - usb_tdBuf) / TD_SIZE;

14
features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h
View File

@ -47,8 +47,8 @@ typedef struct {
* endpoint */
volatile uint32_t addr[MAX_ENDPOINT];
USBHALHost *inst;
void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub * hub_parent);
void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr);
void (USBHALHost::*deviceConnected)(int hub, int port, bool lowSpeed, USBHostHub *hub_parent);
void (USBHALHost::*deviceDisconnected)(int hub, int port, USBHostHub *hub_parent, volatile uint32_t addr);
void (USBHALHost::*transferCompleted)(volatile uint32_t addr);
} USBHALHost_Private_t;
@ -120,7 +120,7 @@ static gpio_t gpio_powerpin;
#endif
void usb_vbus( uint8_t state)
void usb_vbus(uint8_t state)
{
if (state == 0) {
gpio_write(&gpio_powerpin, USB_POWER_OFF);
@ -135,14 +135,14 @@ USBHALHost::USBHALHost()
{
instHost = this;
HCD_HandleTypeDef *hhcd = {0};
USBHALHost_Private_t *HALPriv = new(USBHALHost_Private_t);
USBHALHost_Private_t *HALPriv = new (USBHALHost_Private_t);
memset(HALPriv, 0, sizeof(USBHALHost_Private_t));
memInit();
memset((void*)usb_hcca, 0, HCCA_SIZE);
memset((void *)usb_hcca, 0, HCCA_SIZE);
hhcd = (HCD_HandleTypeDef *)usb_hcca;
hhcd->pData = (void*)HALPriv;
hhcd->pData = (void *)HALPriv;
#if defined(TARGET_DISCO_F746NG_HS) || defined(TARGET_DISCO_F769NI)
hhcd->Instance = USB_OTG_HS;
@ -169,7 +169,7 @@ USBHALHost::USBHALHost()
for (int i = 0; i < MAX_ENDPOINT; i++) {
edBufAlloc[i] = false;
HALPriv->addr[i] = (uint32_t)-1;
HALPriv->addr[i] = (uint32_t) - 1;
}
for (int i = 0; i < MAX_TD; i++) {

2
targets/TARGET_STM/PinNamesTypes.h
View File

@ -37,7 +37,7 @@ extern "C" {
#endif
/* STM PIN data as used in pin_function is coded on 32 bits as below
* [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog
* [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog
* [3] Output Push-Pull / Open Drain (as in OTYPER reg)
* [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc
* [7:6] Reserved for speed config (as in OSPEEDR), but not used yet

4
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h
View File

@ -46,7 +46,7 @@ typedef enum {
} DACName;
typedef enum {
UART_1 = (int)USART1_BASE,
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE
} UARTName;
@ -63,7 +63,7 @@ typedef enum {
typedef enum {
PWM_1 = (int)TIM1_BASE,
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_14 = (int)TIM14_BASE,
PWM_15 = (int)TIM15_BASE,
PWM_16 = (int)TIM16_BASE,

24
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h
View File

@ -49,17 +49,17 @@ typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT0 = PA_2 | ALT0,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT0 = PA_3 | ALT0,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -71,8 +71,8 @@ typedef enum {
PB_0 = 0x10,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
@ -87,8 +87,8 @@ typedef enum {
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_1 = 0x21,
@ -230,13 +230,13 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

2
targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h
View File

@ -49,7 +49,7 @@ struct gpio_irq_s {
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
PinDirection direction;
__IO uint32_t *reg_in;
__IO uint32_t *reg_out;
};

20
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h
View File

@ -53,11 +53,11 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -69,8 +69,8 @@ typedef enum {
PB_0 = 0x10,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
@ -85,8 +85,8 @@ typedef enum {
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_1 = 0x21,
@ -175,13 +175,13 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PC_7,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

18
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h
View File

@ -53,11 +53,11 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -68,10 +68,10 @@ typedef enum {
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
@ -142,11 +142,11 @@ typedef enum {
SPI_CS = PB_1,
PWM_OUT = PB_0,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

20
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h
View File

@ -53,11 +53,11 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -68,10 +68,10 @@ typedef enum {
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
@ -140,18 +140,18 @@ typedef enum {
SPI_CS = PA_4,
PWM_OUT = PB_0,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
USB_NOE = PA_4,
USB_NOE_ALT0 = PA_13,
USB_NOE_ALT1 = PA_15,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

26
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h
View File

@ -53,11 +53,11 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -69,8 +69,8 @@ typedef enum {
PB_0 = 0x10,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
@ -85,8 +85,8 @@ typedef enum {
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_1 = 0x21,
@ -99,9 +99,9 @@ typedef enum {
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -173,18 +173,18 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
USB_NOE = PA_13,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

30
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h
View File

@ -53,11 +53,11 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -68,10 +68,10 @@ typedef enum {
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
@ -85,10 +85,10 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_1 = 0x21,
@ -101,9 +101,9 @@ typedef enum {
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -175,18 +175,18 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
USB_NOE = PA_13,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

32
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h
View File

@ -53,11 +53,11 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -68,10 +68,10 @@ typedef enum {
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
@ -85,15 +85,15 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_3 = 0x23,
PC_4 = 0x24,
@ -103,9 +103,9 @@ typedef enum {
PC_8 = 0x28,
PC_9 = 0x29,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -178,13 +178,13 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_SWCLK = PA_14,
SYS_SWDIO = PA_13,
SYS_WKUP1 = PA_0,

8
targets/TARGET_STM/TARGET_STM32F0/analogout_device.c
View File

@ -35,7 +35,8 @@
#include "mbed_error.h"
#include "PeripheralPins.h"
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -73,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin) {
obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
obj->handle.State = HAL_DAC_STATE_RESET;
if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
error("HAL_DAC_Init failed");
}
@ -87,7 +88,8 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
__HAL_RCC_DAC1_FORCE_RESET();
__HAL_RCC_DAC1_RELEASE_RESET();

2
targets/TARGET_STM/TARGET_STM32F0/flash_api.c
View File

@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
} else { /* case where data is aligned, so let's avoid any copy */
while ((address < (StartAddress + size)) && (status == 0)) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) {
address = address + MIN_PROG_SIZE;
data = data + MIN_PROG_SIZE;
} else {

7
targets/TARGET_STM/TARGET_STM32F0/pin_device.h
View File

@ -56,14 +56,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
}
}
static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F0/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

172
targets/TARGET_STM/TARGET_STM32F0/serial_device.c
View File

@ -33,13 +33,13 @@
#include "serial_api_hal.h"
#if defined (TARGET_STM32F031K6)
#define UART_NUM (1)
#define UART_NUM (1)
#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6)
#define UART_NUM (2)
#define UART_NUM (2)
#elif defined (TARGET_STM32F070RB) || defined (TARGET_STM32F072RB)
#define UART_NUM (4)
#define UART_NUM (4)
#else
#define UART_NUM (8) // max value (TARGET_STM32F091RC)
#define UART_NUM (8) // max value (TARGET_STM32F091RC)
#endif
uint32_t serial_irq_ids[UART_NUM] = {0};
@ -59,7 +59,7 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
@ -100,45 +100,45 @@ static void uart3_8_irq(void)
{
#if defined(TARGET_STM32F091RC)
#if defined(USART3_BASE)
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) {
uart_irq(UART_3);
}
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART3) != RESET) {
uart_irq(UART_3);
}
#endif
#if defined(USART4_BASE)
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) {
uart_irq(UART_4);
}
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART4) != RESET) {
uart_irq(UART_4);
}
#endif
#if defined(USART5_BASE)
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) {
uart_irq(UART_5);
}
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART5) != RESET) {
uart_irq(UART_5);
}
#endif
#if defined(USART6_BASE)
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) {
uart_irq(UART_6);
}
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART6) != RESET) {
uart_irq(UART_6);
}
#endif
#if defined(USART7_BASE)
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) {
uart_irq(UART_7);
}
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART7) != RESET) {
uart_irq(UART_7);
}
#endif
#if defined(USART8_BASE)
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) {
uart_irq(UART_8);
}
if (__HAL_GET_PENDING_IT(HAL_ITLINE_USART8) != RESET) {
uart_irq(UART_8);
}
#endif
#else // TARGET_STM32F070RB, TARGET_STM32F072RB
#if defined(USART3_BASE)
if (USART3->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) {
uart_irq(UART_3);
}
if (USART3->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) {
uart_irq(UART_3);
}
#endif
#if defined(USART4_BASE)
if (USART4->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) {
uart_irq(UART_4);
}
if (USART4->ISR & (UART_FLAG_TXE | UART_FLAG_RXNE | UART_FLAG_ORE)) {
uart_irq(UART_4);
}
#endif
#endif
}
@ -146,7 +146,7 @@ static void uart3_8_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -297,7 +297,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -317,7 +317,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -339,7 +339,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -347,9 +347,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -439,7 +439,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -453,28 +453,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -484,14 +484,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -512,18 +512,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -533,8 +533,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -546,10 +546,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -562,20 +562,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
}
@ -600,49 +602,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -650,7 +652,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -664,11 +666,11 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
return return_event;
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -678,17 +680,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -705,20 +707,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -748,9 +750,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -780,7 +782,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

9
targets/TARGET_STM/TARGET_STM32F0/spi_api.c
View File

@ -37,17 +37,18 @@
#include "PeripheralPins.h"
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
/* SPI_1, SPI_2. Source CLK is PCKL1 */
int spi_get_clock_freq(spi_t *obj)
{
/* SPI_1, SPI_2. Source CLK is PCKL1 */
return HAL_RCC_GetPCLK1Freq();
}

4
targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PeripheralPins.c
View File

@ -172,12 +172,12 @@ const PinMap PinMap_SPI_SSEL[] = {
const PinMap PinMap_CAN_RD[] = {
{PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)},
{PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)},
{PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 1)},
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
{PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},
{PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
{PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)},
{NC, NC, 0}
};

2
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h
View File

@ -45,7 +45,7 @@ typedef enum {
} DACName;
typedef enum {
UART_1 = (int)USART1_BASE,
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
UART_3 = (int)USART3_BASE
} UARTName;

4
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h
View File

@ -174,13 +174,13 @@ typedef enum {
SPI_CS = PB_12,
PWM_OUT = PB_8,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PD_0,
RCC_OSC_OUT = PD_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

2
targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h
View File

@ -49,7 +49,7 @@ struct gpio_irq_s {
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
PinDirection direction;
__IO uint32_t *reg_in;
__IO uint32_t *reg_out;
};

4
targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c
View File

@ -109,8 +109,8 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4
{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1
{PB_0 , PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3
{PB_1 , PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4
{PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3
{PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4
{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 // Connected to SWO
{PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2

6
targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h
View File

@ -154,17 +154,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PD_0,
RCC_OSC_OUT = PD_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

2
targets/TARGET_STM/TARGET_STM32F1/flash_api.c
View File

@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
} else { /* case where data is aligned, so let's avoid any copy */
while ((address < (StartAddress + size)) && (status == 0)) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) {
address = address + MIN_PROG_SIZE;
data = data + MIN_PROG_SIZE;
} else {

73
targets/TARGET_STM/TARGET_STM32F1/pin_device.h
View File

@ -58,40 +58,40 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af
if (afnum > 0) {
switch (afnum) {
case 1: // Remap SPI1
__HAL_AFIO_REMAP_SPI1_ENABLE();
break;
case 2: // Remap I2C1
__HAL_AFIO_REMAP_I2C1_ENABLE();
break;
case 3: // Remap USART1
__HAL_AFIO_REMAP_USART1_ENABLE();
break;
case 4: // Remap USART2
__HAL_AFIO_REMAP_USART2_ENABLE();
break;
case 5: // Partial Remap USART3
__HAL_AFIO_REMAP_USART3_PARTIAL();
break;
case 6: // Partial Remap TIM1
__HAL_AFIO_REMAP_TIM1_PARTIAL();
break;
case 7: // Partial Remap TIM3
__HAL_AFIO_REMAP_TIM3_PARTIAL();
break;
case 8: // Full Remap TIM2
__HAL_AFIO_REMAP_TIM2_ENABLE();
break;
case 9: // Full Remap TIM3
__HAL_AFIO_REMAP_TIM3_ENABLE();
break;
case 1: // Remap SPI1
__HAL_AFIO_REMAP_SPI1_ENABLE();
break;
case 2: // Remap I2C1
__HAL_AFIO_REMAP_I2C1_ENABLE();
break;
case 3: // Remap USART1
__HAL_AFIO_REMAP_USART1_ENABLE();
break;
case 4: // Remap USART2
__HAL_AFIO_REMAP_USART2_ENABLE();
break;
case 5: // Partial Remap USART3
__HAL_AFIO_REMAP_USART3_PARTIAL();
break;
case 6: // Partial Remap TIM1
__HAL_AFIO_REMAP_TIM1_PARTIAL();
break;
case 7: // Partial Remap TIM3
__HAL_AFIO_REMAP_TIM3_PARTIAL();
break;
case 8: // Full Remap TIM2
__HAL_AFIO_REMAP_TIM2_ENABLE();
break;
case 9: // Full Remap TIM3
__HAL_AFIO_REMAP_TIM3_ENABLE();
break;
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
__HAL_AFIO_REMAP_CAN1_2();
break;
case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
__HAL_AFIO_REMAP_CAN1_2();
break;
#endif
default:
break;
default:
break;
}
}
}
@ -102,19 +102,22 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
switch (pull_config) {
case GPIO_PULLUP:
if (function == LL_GPIO_MODE_FLOATING)
if (function == LL_GPIO_MODE_FLOATING) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
}
LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
break;
case GPIO_PULLDOWN:
if (function == LL_GPIO_MODE_FLOATING)
if (function == LL_GPIO_MODE_FLOATING) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
}
LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
break;
default:
/* Input+NoPull = Floating for F1 family */
if (function == LL_GPIO_MODE_INPUT)
if (function == LL_GPIO_MODE_INPUT) {
LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_FLOATING);
}
break;
}
}

3
targets/TARGET_STM/TARGET_STM32F1/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM1_BASE)
{PWM_1, PWMOUT_ON_APB2},
#endif

116
targets/TARGET_STM/TARGET_STM32F1/serial_device.c
View File

@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
@ -97,7 +97,7 @@ static void uart3_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -214,7 +214,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -234,7 +234,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -256,7 +256,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -264,9 +264,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -313,7 +313,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -327,28 +327,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -358,14 +358,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -386,18 +386,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -407,8 +407,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -420,10 +420,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -436,20 +436,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
@ -471,49 +473,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -521,7 +523,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -535,11 +537,11 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
return return_event;
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -549,17 +551,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -576,20 +578,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -619,9 +621,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -651,7 +653,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

29
targets/TARGET_STM/TARGET_STM32F1/spi_api.c
View File

@ -37,31 +37,32 @@
#include "PeripheralPins.h"
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
int spi_hz = 0;
/* Get source clock depending on SPI instance */
/* Get source clock depending on SPI instance */
switch ((int)spiobj->spi) {
case SPI_1:
/* SPI_1. Source CLK is PCKL2 */
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
case SPI_2:
/* SPI_2. Source CLK is PCKL1 */
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
default:
error("CLK: SPI instance not set");
/* SPI_1. Source CLK is PCKL2 */
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
case SPI_2:
/* SPI_2. Source CLK is PCKL1 */
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
default:
error("CLK: SPI instance not set");
break;
}
return spi_hz;

94
targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h
View File

@ -47,27 +47,27 @@ typedef enum {
typedef enum {
PA_0 = 0x00,
PA_0_ALT0 = 0x00|ALT0,
PA_0_ALT1 = 0x00|ALT1,
PA_0_ALT0 = 0x00 | ALT0,
PA_0_ALT1 = 0x00 | ALT1,
PA_1 = 0x01,
PA_1_ALT0 = PA_1|ALT0,
PA_1_ALT1 = PA_1|ALT1,
PA_1_ALT0 = PA_1 | ALT0,
PA_1_ALT1 = PA_1 | ALT1,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT1 = PA_2|ALT1,
PA_2_ALT0 = PA_2 | ALT0,
PA_2_ALT1 = PA_2 | ALT1,
PA_3 = 0x03,
PA_3_ALT0 = 0x03|ALT0,
PA_3_ALT1 = 0x03|ALT1,
PA_3_ALT0 = 0x03 | ALT0,
PA_3_ALT1 = 0x03 | ALT1,
PA_4 = 0x04,
PA_4_ALT0 = 0x04|ALT0,
PA_4_ALT0 = 0x04 | ALT0,
PA_5 = 0x05,
PA_5_ALT0 = 0x05|ALT0,
PA_5_ALT0 = 0x05 | ALT0,
PA_6 = 0x06,
PA_6_ALT0 = 0x06|ALT0,
PA_6_ALT0 = 0x06 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = 0x07|ALT0,
PA_7_ALT1 = 0x07|ALT1,
PA_7_ALT2 = 0x07|ALT2,
PA_7_ALT0 = 0x07 | ALT0,
PA_7_ALT1 = 0x07 | ALT1,
PA_7_ALT2 = 0x07 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -76,63 +76,63 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = 0x0F|ALT0,
PA_15_ALT0 = 0x0F | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = 0x10|ALT0,
PB_0_ALT1 = 0x10|ALT1,
PB_0_ALT2 = 0x10|ALT2,
PB_0_ALT0 = 0x10 | ALT0,
PB_0_ALT1 = 0x10 | ALT1,
PB_0_ALT2 = 0x10 | ALT2,
PB_1 = 0x11,
PB_1_ALT0 = 0x11|ALT0,
PB_1_ALT1 = 0x11|ALT1,
PB_1_ALT0 = 0x11 | ALT0,
PB_1_ALT1 = 0x11 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = 0x13|ALT0,
PB_3_ALT0 = 0x13 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = 0x14|ALT0,
PB_4_ALT0 = 0x14 | ALT0,
PB_5 = 0x15,
PB_5_ALT0 = 0x15|ALT0,
PB_5_ALT0 = 0x15 | ALT0,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = 0x18|ALT0,
PB_8_ALT0 = 0x18 | ALT0,
PB_9 = 0x19,
PB_9_ALT0 = 0x19|ALT0,
PB_9_ALT0 = 0x19 | ALT0,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT1 = PB_14|ALT1,
PB_14_ALT0 = PB_14 | ALT0,
PB_14_ALT1 = PB_14 | ALT1,
PB_15 = 0x1F,
PB_15_ALT0 = 0x1F|ALT0,
PB_15_ALT1 = 0x1F|ALT1,
PB_15_ALT0 = 0x1F | ALT0,
PB_15_ALT1 = 0x1F | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = 0x20|ALT0,
PC_0_ALT1 = 0x20|ALT1,
PC_0_ALT0 = 0x20 | ALT0,
PC_0_ALT1 = 0x20 | ALT1,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT1 = PC_1|ALT1,
PC_1_ALT0 = PC_1 | ALT0,
PC_1_ALT1 = PC_1 | ALT1,
PC_2 = 0x22,
PC_2_ALT0 = 0x22|ALT0,
PC_2_ALT1 = 0x22|ALT1,
PC_2_ALT0 = 0x22 | ALT0,
PC_2_ALT1 = 0x22 | ALT1,
PC_3 = 0x23,
PC_3_ALT0 = 0x23|ALT0,
PC_3_ALT1 = 0x23|ALT1,
PC_3_ALT0 = 0x23 | ALT0,
PC_3_ALT1 = 0x23 | ALT1,
PC_4 = 0x24,
PC_4_ALT0 = PC_4|ALT0,
PC_4_ALT0 = PC_4 | ALT0,
PC_5 = 0x25,
PC_5_ALT0 = PC_5|ALT0,
PC_5_ALT0 = PC_5 | ALT0,
PC_6 = 0x26,
PC_6_ALT0 = 0x26|ALT0,
PC_6_ALT0 = 0x26 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = 0x27|ALT0,
PC_7_ALT0 = 0x27 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = 0x28|ALT0,
PC_8_ALT0 = 0x28 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = 0x29|ALT0,
PC_9_ALT0 = 0x29 | ALT0,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
@ -272,7 +272,7 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
@ -296,7 +296,7 @@ typedef enum {
USB_OTG_HS_ULPI_STP = PC_0,
USB_OTG_HS_VBUS = PB_13,
/**** ETHERNET pins ****/
/**** ETHERNET pins ****/
ETH_COL = PA_3,
ETH_CRS = PA_0,
ETH_CRS_DV = PA_7,
@ -323,13 +323,13 @@ typedef enum {
ETH_TX_EN = PB_11,
ETH_TX_EN_ALT0 = PG_11,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

2
targets/TARGET_STM/TARGET_STM32F2/analogout_device.c
View File

@ -74,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin)
obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
obj->handle.State = HAL_DAC_STATE_RESET;
if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
error("HAL_DAC_Init failed");
}

32
targets/TARGET_STM/TARGET_STM32F2/flash_api.c
View File

@ -14,7 +14,7 @@
* limitations under the License.
*/
#if DEVICE_FLASH
#if DEVICE_FLASH
#include "flash_api.h"
#include "flash_data.h"
@ -99,10 +99,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
return -1;
}
/* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the FLASH_CR register. */
/* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
you have to make sure that these data are rewritten before they are accessed during code
execution. If this cannot be done safely, it is recommended to flush the caches by setting the
DCRST and ICRST bits in the FLASH_CR register. */
__HAL_FLASH_DATA_CACHE_DISABLE();
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
@ -171,13 +171,13 @@ static uint32_t GetSector(uint32_t address)
}
#endif
if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
sector += tmp >>14;
sector += tmp >> 14;
}
#if defined(ADDR_FLASH_SECTOR_5)
else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
sector += FLASH_SECTOR_4;
} else {
sector += 4 + (tmp >>17);
sector += 4 + (tmp >> 17);
}
#else
// In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one.
@ -197,16 +197,16 @@ static uint32_t GetSectorSize(uint32_t Sector)
{
uint32_t sectorsize = 0x00;
#if defined(FLASH_SECTOR_16)
if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
(Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
(Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
sectorsize = 16 * 1024;
} else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \
(Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \
(Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
sectorsize = 16 * 1024;
} else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
#else
if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
(Sector == FLASH_SECTOR_3)) {
sectorsize = 16 * 1024;
} else if(Sector == FLASH_SECTOR_4) {
if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \
(Sector == FLASH_SECTOR_3)) {
sectorsize = 16 * 1024;
} else if (Sector == FLASH_SECTOR_4) {
#endif
sectorsize = 64 * 1024;
} else {

12
targets/TARGET_STM/TARGET_STM32F2/gpio_irq_device.h
View File

@ -39,27 +39,27 @@ extern "C" {
// until then let's define locally the required functions
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR, ExtiLine);
SET_BIT(EXTI->RTSR, ExtiLine);
}
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR, ExtiLine);
CLEAR_BIT(EXTI->RTSR, ExtiLine);
}
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR, ExtiLine);
SET_BIT(EXTI->FTSR, ExtiLine);
}
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR, ExtiLine);
CLEAR_BIT(EXTI->FTSR, ExtiLine);
}
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR, ExtiLine);
SET_BIT(EXTI->IMR, ExtiLine);
}
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR, ExtiLine);
CLEAR_BIT(EXTI->IMR, ExtiLine);
}
// Above lines shall be later defined in LL

27
targets/TARGET_STM/TARGET_STM32F2/pin_device.h
View File

@ -71,35 +71,35 @@
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
(Alternate << (POSITION_VAL(Pin) * 4U)));
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
(Alternate << (POSITION_VAL(Pin) * 4U)));
}
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
}
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
}
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
}
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
}
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
{
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
(Speed << (POSITION_VAL(Pin) * 2U)));
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
(Speed << (POSITION_VAL(Pin) * 2U)));
}
// Above lines shall be defined in LL when available
@ -126,14 +126,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
}
}
static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F2/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

116
targets/TARGET_STM/TARGET_STM32F2/serial_device.c
View File

@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
@ -132,7 +132,7 @@ static void uart8_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -271,7 +271,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -291,7 +291,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -313,7 +313,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -321,9 +321,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -396,7 +396,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -410,28 +410,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -441,14 +441,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -469,18 +469,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -490,8 +490,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -503,10 +503,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -519,20 +519,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
@ -554,49 +556,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -604,7 +606,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -618,11 +620,11 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
return return_event;
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -632,17 +634,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -659,20 +661,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear error flags
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -702,9 +704,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -734,7 +736,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

11
targets/TARGET_STM/TARGET_STM32F2/spi_api.c
View File

@ -39,20 +39,21 @@
#include "mbed_error.h"
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
int spi_hz = 0;
/* Get source clock depending on SPI instance */
/* Get source clock depending on SPI instance */
switch ((int)spiobj->spi) {
case SPI_1:
#if defined SPI4_BASE

18
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/PinNames.h
View File

@ -54,14 +54,14 @@ typedef enum {
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT0 = PA_7 | ALT0,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT0 = PA_11 | ALT0,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT0 = PA_12 | ALT0,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
@ -81,10 +81,10 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_1 = 0x21,
@ -169,17 +169,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TARGET_NUCLEO_F302R8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

24
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h
View File

@ -53,33 +53,33 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT0 = PA_11 | ALT0,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT0 = PA_12 | ALT0,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT0 = PB_1 | ALT0,
PB_3 = 0x13,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT0 = PB_4 | ALT0,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT0 = PB_5 | ALT0,
PB_6 = 0x16,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT0 = PB_7 | ALT0,
PF_0 = 0x50,
PF_1 = 0x51,
@ -148,11 +148,11 @@ typedef enum {
SPI_CS = PA_11,
PWM_OUT = PA_8,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

102
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h
View File

@ -51,88 +51,88 @@ typedef enum {
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_13_ALT0 = PA_13|ALT0,
PA_13_ALT0 = PA_13 | ALT0,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT1 = PB_6|ALT1,
PB_6_ALT0 = PB_6 | ALT0,
PB_6_ALT1 = PB_6 | ALT1,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -149,15 +149,15 @@ typedef enum {
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_10_ALT0 = PD_10|ALT0,
PD_10_ALT0 = PD_10 | ALT0,
PD_11 = 0x3B,
PD_11_ALT0 = PD_11|ALT0,
PD_11_ALT0 = PD_11 | ALT0,
PD_12 = 0x3C,
PD_12_ALT0 = PD_12|ALT0,
PD_12_ALT0 = PD_12 | ALT0,
PD_13 = 0x3D,
PD_13_ALT0 = PD_13|ALT0,
PD_13_ALT0 = PD_13 | ALT0,
PD_14 = 0x3E,
PD_14_ALT0 = PD_14|ALT0,
PD_14_ALT0 = PD_14 | ALT0,
PD_15 = 0x3F,
PE_0 = 0x40,
@ -169,7 +169,7 @@ typedef enum {
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_8_ALT0 = PE_8|ALT0,
PE_8_ALT0 = PE_8 | ALT0,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
@ -181,7 +181,7 @@ typedef enum {
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,
PF_2_ALT0 = PF_2|ALT0,
PF_2_ALT0 = PF_2 | ALT0,
PF_3 = 0x53,
PF_4 = 0x54,
PF_5 = 0x55,
@ -271,17 +271,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c
View File

@ -66,7 +66,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -129,7 +129,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

90
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h
View File

@ -51,89 +51,89 @@ typedef enum {
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_13_ALT0 = PA_13|ALT0,
PA_13_ALT0 = PA_13 | ALT0,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT1 = PB_6|ALT1,
PB_6_ALT0 = PB_6 | ALT0,
PB_6_ALT1 = PB_6 | ALT1,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_11_ALT0 = PB_11|ALT0,
PB_11_ALT0 = PB_11 | ALT0,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_10_ALT0 = PC_10|ALT0,
PC_10_ALT0 = PC_10 | ALT0,
PC_11 = 0x2B,
PC_11_ALT0 = PC_11|ALT0,
PC_11_ALT0 = PC_11 | ALT0,
PC_12 = 0x2C,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -213,17 +213,17 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c
View File

@ -62,7 +62,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -125,7 +125,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h
View File

@ -59,7 +59,7 @@ typedef enum {
SPI_1 = (int)SPI1_BASE,
SPI_2 = (int)SPI2_BASE,
SPI_3 = (int)SPI3_BASE,
SPI_4 = (int)SPI4_BASE
SPI_4 = (int)SPI4_BASE
} SPIName;
@ -78,7 +78,7 @@ typedef enum {
PWM_15 = (int)TIM15_BASE,
PWM_16 = (int)TIM16_BASE,
PWM_17 = (int)TIM17_BASE,
PWM_20 = (int)TIM20_BASE
PWM_20 = (int)TIM20_BASE
} PWMName;
typedef enum {

112
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h
View File

@ -50,87 +50,87 @@ typedef enum {
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT0 = PA_3 | ALT0,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_13_ALT0 = PA_13|ALT0,
PA_13_ALT0 = PA_13 | ALT0,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_6_ALT0 = PB_6|ALT0,
PB_6_ALT1 = PB_6|ALT1,
PB_6_ALT0 = PB_6 | ALT0,
PB_6_ALT1 = PB_6 | ALT1,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT1 = PB_8|ALT1,
PB_8_ALT0 = PB_8 | ALT0,
PB_8_ALT1 = PB_8 | ALT1,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT1 = PB_9|ALT1,
PB_9_ALT0 = PB_9 | ALT0,
PB_9_ALT1 = PB_9 | ALT1,
PB_10 = 0x1A,
PB_11 = 0x1B,
PB_11_ALT0 = PB_11|ALT0,
PB_11_ALT0 = PB_11 | ALT0,
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
PC_6_ALT0 = PC_6|ALT0,
PC_6_ALT0 = PC_6 | ALT0,
PC_7 = 0x27,
PC_7_ALT0 = PC_7|ALT0,
PC_7_ALT0 = PC_7 | ALT0,
PC_8 = 0x28,
PC_8_ALT0 = PC_8|ALT0,
PC_8_ALT0 = PC_8 | ALT0,
PC_9 = 0x29,
PC_9_ALT0 = PC_9|ALT0,
PC_9_ALT0 = PC_9 | ALT0,
PC_10 = 0x2A,
PC_11 = 0x2B,
PC_12 = 0x2C,
@ -149,32 +149,32 @@ typedef enum {
PD_8 = 0x38,
PD_9 = 0x39,
PD_10 = 0x3A,
PD_10_ALT0 = PD_10|ALT0,
PD_10_ALT0 = PD_10 | ALT0,
PD_11 = 0x3B,
PD_11_ALT0 = PD_11|ALT0,
PD_11_ALT0 = PD_11 | ALT0,
PD_12 = 0x3C,
PD_12_ALT0 = PD_12|ALT0,
PD_12_ALT0 = PD_12 | ALT0,
PD_13 = 0x3D,
PD_13_ALT0 = PD_13|ALT0,
PD_13_ALT0 = PD_13 | ALT0,
PD_14 = 0x3E,
PD_14_ALT0 = PD_14|ALT0,
PD_14_ALT0 = PD_14 | ALT0,
PD_15 = 0x3F,
PE_0 = 0x40,
PE_1 = 0x41,
PE_1_ALT0 = PE_1|ALT0,
PE_1_ALT0 = PE_1 | ALT0,
PE_2 = 0x42,
PE_2_ALT0 = PE_2|ALT0,
PE_2_ALT0 = PE_2 | ALT0,
PE_3 = 0x43,
PE_3_ALT0 = PE_3|ALT0,
PE_3_ALT0 = PE_3 | ALT0,
PE_4 = 0x44,
PE_4_ALT0 = PE_4|ALT0,
PE_4_ALT0 = PE_4 | ALT0,
PE_5 = 0x45,
PE_5_ALT0 = PE_5|ALT0,
PE_5_ALT0 = PE_5 | ALT0,
PE_6 = 0x46,
PE_7 = 0x47,
PE_8 = 0x48,
PE_8_ALT0 = PE_8|ALT0,
PE_8_ALT0 = PE_8 | ALT0,
PE_9 = 0x49,
PE_10 = 0x4A,
PE_11 = 0x4B,
@ -186,7 +186,7 @@ typedef enum {
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,
PF_2_ALT0 = PF_2|ALT0,
PF_2_ALT0 = PF_2 | ALT0,
PF_3 = 0x53,
PF_4 = 0x54,
PF_5 = 0x55,
@ -291,17 +291,17 @@ typedef enum {
SPI_CS = D10,
PWM_OUT = D9,
/**** USB pins ****/
/**** USB pins ****/
USB_DM = PA_11,
USB_DP = PA_12,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c
View File

@ -62,7 +62,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -125,7 +125,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

46
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/PinNames.h
View File

@ -53,42 +53,42 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
@ -96,10 +96,10 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_13 = 0x2D,
PC_14 = 0x2E,
@ -174,13 +174,13 @@ typedef enum {
SPI_CS = PA_4,
PWM_OUT = PB_6,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_DISCO_F334C8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

54
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/PinNames.h
View File

@ -53,42 +53,42 @@ typedef enum {
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_6_ALT0 = PA_6|ALT0,
PA_6_ALT0 = PA_6 | ALT0,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT1 = PA_7|ALT1,
PA_7_ALT2 = PA_7|ALT2,
PA_7_ALT0 = PA_7 | ALT0,
PA_7_ALT1 = PA_7 | ALT1,
PA_7_ALT2 = PA_7 | ALT2,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_11_ALT0 = PA_11|ALT0,
PA_11_ALT1 = PA_11|ALT1,
PA_11_ALT0 = PA_11 | ALT0,
PA_11_ALT1 = PA_11 | ALT1,
PA_12 = 0x0C,
PA_12_ALT0 = PA_12|ALT0,
PA_12_ALT1 = PA_12|ALT1,
PA_12_ALT0 = PA_12 | ALT0,
PA_12_ALT1 = PA_12 | ALT1,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT1 = PB_0|ALT1,
PB_0_ALT0 = PB_0 | ALT0,
PB_0_ALT1 = PB_0 | ALT1,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT1 = PB_1|ALT1,
PB_1_ALT0 = PB_1 | ALT0,
PB_1_ALT1 = PB_1 | ALT1,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT1 = PB_4|ALT1,
PB_4_ALT0 = PB_4 | ALT0,
PB_4_ALT1 = PB_4 | ALT1,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT1 = PB_5|ALT1,
PB_5_ALT0 = PB_5 | ALT0,
PB_5_ALT1 = PB_5 | ALT1,
PB_6 = 0x16,
PB_7 = 0x17,
PB_7_ALT0 = PB_7|ALT0,
PB_7_ALT1 = PB_7|ALT1,
PB_7_ALT0 = PB_7 | ALT0,
PB_7_ALT1 = PB_7 | ALT1,
PB_8 = 0x18,
PB_9 = 0x19,
PB_10 = 0x1A,
@ -96,19 +96,19 @@ typedef enum {
PB_12 = 0x1C,
PB_13 = 0x1D,
PB_14 = 0x1E,
PB_14_ALT0 = PB_14|ALT0,
PB_14_ALT0 = PB_14 | ALT0,
PB_15 = 0x1F,
PB_15_ALT0 = PB_15|ALT0,
PB_15_ALT1 = PB_15|ALT1,
PB_15_ALT0 = PB_15 | ALT0,
PB_15_ALT1 = PB_15 | ALT1,
PC_0 = 0x20,
PC_0_ALT0 = PC_0|ALT0,
PC_0_ALT0 = PC_0 | ALT0,
PC_1 = 0x21,
PC_1_ALT0 = PC_1|ALT0,
PC_1_ALT0 = PC_1 | ALT0,
PC_2 = 0x22,
PC_2_ALT0 = PC_2|ALT0,
PC_2_ALT0 = PC_2 | ALT0,
PC_3 = 0x23,
PC_3_ALT0 = PC_3|ALT0,
PC_3_ALT0 = PC_3 | ALT0,
PC_4 = 0x24,
PC_5 = 0x25,
PC_6 = 0x26,
@ -191,13 +191,13 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_4,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PF_0,
RCC_OSC_OUT = PF_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_TRACESWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TARGET_NUCLEO_F334R8/system_clock.c
View File

@ -67,7 +67,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
@ -130,7 +130,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

6
targets/TARGET_STM/TARGET_STM32F3/analogin_device.c
View File

@ -170,8 +170,7 @@ uint16_t adc_read(analogin_t *obj)
if ((ADCName)obj->handle.Instance == ADC_1) {
sConfig.Channel = ADC_CHANNEL_VOPAMP1;
sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5;
}
else {
} else {
sConfig.Channel = ADC_CHANNEL_15;
}
break;
@ -179,8 +178,7 @@ uint16_t adc_read(analogin_t *obj)
if ((ADCName)obj->handle.Instance == ADC_1) {
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
sConfig.SamplingTime = ADC_SAMPLETIME_181CYCLES_5;
}
else {
} else {
sConfig.Channel = ADC_CHANNEL_16;
}
break;

16
targets/TARGET_STM/TARGET_STM32F3/analogout_device.c
View File

@ -39,7 +39,8 @@
static int pa4_used = 0;
static int pa5_used = 0;
void analogout_init(dac_t *obj, PinName pin) {
void analogout_init(dac_t *obj, PinName pin)
{
DAC_ChannelConfTypeDef sConfig = {0};
// Get the peripheral name from the pin and assign it to the object
@ -85,7 +86,7 @@ void analogout_init(dac_t *obj, PinName pin) {
obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
obj->handle.State = HAL_DAC_STATE_RESET;
if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
error("HAL_DAC_Init failed");
}
@ -115,10 +116,15 @@ void analogout_init(dac_t *obj, PinName pin) {
analogout_write_u16(obj, 0);
}
void analogout_free(dac_t *obj) {
void analogout_free(dac_t *obj)
{
// Reset DAC and disable clock
if (obj->pin == PA_4) pa4_used = 0;
if (obj->pin == PA_5) pa5_used = 0;
if (obj->pin == PA_4) {
pa4_used = 0;
}
if (obj->pin == PA_5) {
pa5_used = 0;
}
if ((pa4_used == 0) && (pa5_used == 0)) {
__HAL_RCC_DAC1_FORCE_RESET();

2
targets/TARGET_STM/TARGET_STM32F3/flash_api.c
View File

@ -134,7 +134,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
} else { /* case where data is aligned, so let's avoid any copy */
while ((address < (StartAddress + size)) && (status == 0)) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t *) data)) == HAL_OK) {
address = address + MIN_PROG_SIZE;
data = data + MIN_PROG_SIZE;
} else {

7
targets/TARGET_STM/TARGET_STM32F3/pin_device.h
View File

@ -57,14 +57,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
}
}
static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
{
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
if (STM_PIN(pin) > 7)
if (STM_PIN(pin) > 7) {
LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
else
} else {
LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
}
}
#endif

3
targets/TARGET_STM/TARGET_STM32F3/pwmout_device.c
View File

@ -33,8 +33,7 @@
#ifdef DEVICE_PWMOUT
const pwm_apb_map_t pwm_apb_map_table[] =
{
const pwm_apb_map_t pwm_apb_map_table[] = {
#if defined(TIM2_BASE)
{PWM_2, PWMOUT_ON_APB1},
#endif

124
targets/TARGET_STM/TARGET_STM32F3/serial_device.c
View File

@ -33,9 +33,9 @@
#include "serial_api_hal.h"
#if defined (TARGET_STM32F302x8) || defined (TARGET_STM32F303x8) || defined (TARGET_STM32F334x8)
#define UART_NUM (3)
#define UART_NUM (3)
#else
#define UART_NUM (5) // max value
#define UART_NUM (5) // max value
#endif
uint32_t serial_irq_ids[UART_NUM] = {0};
@ -55,12 +55,12 @@ static void uart_irq(UARTName uart_name)
int8_t id = get_uart_index(uart_name);
if (id >= 0) {
UART_HandleTypeDef * huart = &uart_handlers[id];
UART_HandleTypeDef *huart = &uart_handlers[id];
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) {
irq_handler(serial_irq_ids[id], TxIrq);
}
irq_handler(serial_irq_ids[id], TxIrq);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) {
@ -115,7 +115,7 @@ static void uart5_irq(void)
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
struct serial_s *obj_s = SERIAL_S(obj);
irq_handler = handler;
serial_irq_ids[obj_s->index] = id;
}
@ -246,7 +246,7 @@ void serial_break_set(serial_t *obj)
* LOCAL HELPER FUNCTIONS
******************************************************************************/
/**
/**
* Configure the TX buffer for an asynchronous write serial transaction
*
* @param obj The serial object.
@ -266,7 +266,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
obj->tx_buff.length = tx_length;
obj->tx_buff.pos = 0;
}
/**
* Configure the RX buffer for an asynchronous write serial transaction
*
@ -288,7 +288,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
obj->rx_buff.pos = 0;
}
/**
/**
* Configure events
*
* @param obj The serial object
@ -296,9 +296,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
* @param enable Set to non-zero to enable events, or zero to disable them
*/
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
{
{
struct serial_s *obj_s = SERIAL_S(obj);
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
if (enable) {
obj_s->events |= event;
@ -356,7 +356,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* MBED API FUNCTIONS
******************************************************************************/
/**
/**
* Begin asynchronous TX transfer. The used buffer is specified in the serial
* object, tx_buff
*
@ -370,28 +370,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
* @return Returns number of data transfered, or 0 otherwise
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
{
// TODO: DMA usage is currently ignored
(void) hint;
// Check buffer is ok
MBED_ASSERT(tx != (void*)0);
MBED_ASSERT(tx != (void *)0);
MBED_ASSERT(tx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
if (tx_length == 0) {
return 0;
}
// Set up buffer
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
// Set up events
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
serial_enable_event(obj, event, 1); // Set only the wanted events
// Enable interrupt
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
NVIC_ClearPendingIRQ(irq_n);
@ -401,14 +401,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
NVIC_EnableIRQ(irq_n);
// the following function will enable UART_IT_TXE and error interrupts
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
return 0;
}
return tx_length;
}
/**
/**
* Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object, rx_buff
*
@ -429,18 +429,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
/* Sanity check arguments */
MBED_ASSERT(obj);
MBED_ASSERT(rx != (void*)0);
MBED_ASSERT(rx != (void *)0);
MBED_ASSERT(rx_width == 8); // support only 8b width
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
serial_enable_event(obj, event, 1);
// set CharMatch
obj->char_match = char_match;
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
@ -450,8 +450,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
NVIC_SetVector(irq_n, (uint32_t)handler);
NVIC_EnableIRQ(irq_n);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
// following HAL function will enable the RXNE interrupt + error interrupts
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
}
/**
@ -463,10 +463,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
uint8_t serial_tx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
}
@ -479,20 +479,22 @@ uint8_t serial_tx_active(serial_t *obj)
uint8_t serial_rx_active(serial_t *obj)
{
MBED_ASSERT(obj);
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
}
}
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
}
@ -517,49 +519,49 @@ int serial_irq_handler_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
volatile int return_event = 0;
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
uint8_t i = 0;
// TX PART:
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
// Return event SERIAL_EVENT_TX_COMPLETE if requested
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
}
}
}
// Handle error events
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) {
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) {
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
}
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) {
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
}
}
HAL_UART_IRQHandler(huart);
// Abort if an error occurs
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
return return_event;
}
//RX PART
if (huart->RxXferSize != 0) {
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
@ -567,7 +569,7 @@ int serial_irq_handler_asynch(serial_t *obj)
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
}
// Check if char_match is present
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
if (buf != NULL) {
@ -581,11 +583,11 @@ int serial_irq_handler_asynch(serial_t *obj)
}
}
}
return return_event;
return return_event;
}
/**
/**
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flush TX hardware buffer if TX FIFO is used
*
@ -595,17 +597,17 @@ void serial_tx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
// reset states
huart->TxXferCount = 0;
// update handle state
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
huart->gState = HAL_UART_STATE_BUSY_RX;
} else {
huart->gState = HAL_UART_STATE_READY;
@ -622,20 +624,20 @@ void serial_rx_abort_asynch(serial_t *obj)
{
struct serial_s *obj_s = SERIAL_S(obj);
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
// disable interrupts
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
// clear flags
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag
// reset states
huart->RxXferCount = 0;
// update handle state
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
huart->RxState = HAL_UART_STATE_BUSY_TX;
} else {
huart->RxState = HAL_UART_STATE_READY;
@ -665,9 +667,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
MBED_ASSERT(obj_s->uart != (UARTName)NC);
if(type == FlowControlNone) {
if (type == FlowControlNone) {
// Disable hardware flow control
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
@ -697,7 +699,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
}
init_uart(obj);
}

11
targets/TARGET_STM/TARGET_STM32F3/spi_api.c
View File

@ -39,20 +39,21 @@
#if DEVICE_SPI_ASYNCH
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
#else
#define SPI_S(obj) (( struct spi_s *)(obj))
#define SPI_S(obj) (( struct spi_s *)(obj))
#endif
/*
* Only the frequency is managed in the family specific part
* the rest of SPI management is common to all STM32 families
*/
int spi_get_clock_freq(spi_t *obj) {
int spi_get_clock_freq(spi_t *obj)
{
struct spi_s *spiobj = SPI_S(obj);
int spi_hz = 0;
int spi_hz = 0;
/* Get source clock depending on SPI instance */
/* Get source clock depending on SPI instance */
switch ((int)spiobj->spi) {
#if defined SPI1_BASE
case SPI_1:

2
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/PinNames.h
View File

@ -169,7 +169,7 @@ typedef enum {
SWCLK = PA_14,
I2C1_SCL = PB_8,
I2C1_SDA = PB_9,
I2C1_SDA = PB_9,
I2C3_SCL = PA_8,
I2C3_SDA = PC_9,

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/onboard_modem_api.c
View File

@ -35,7 +35,7 @@ static void press_power_button(int time_ms)
void onboard_modem_init()
{
//does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed
//does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed
}
void onboard_modem_deinit()
@ -59,7 +59,7 @@ void onboard_modem_power_down()
* If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes
* place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10
* seconds only */
wait_ms(10*1000);
wait_ms(10 * 1000);
}
#endif //MODEM_ON_BOARD
#endif //MBED_CONF_NSAPI_PRESENT

2
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h
View File

@ -162,7 +162,7 @@ typedef enum {
// I2C1 and I2C3 are available on Arduino pins
I2C1_SCL = D15,
I2C1_SDA = D14,
I2C1_SDA = D14,
I2C3_SCL = D7,
I2C3_SDA = A5,

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/onboard_modem_api.c
View File

@ -35,7 +35,7 @@ static void press_power_button(int time_ms)
void onboard_modem_init()
{
//does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed
//does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed
}
void onboard_modem_deinit()
@ -59,7 +59,7 @@ void onboard_modem_power_down()
* If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes
* place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10
* seconds only */
wait_ms(10*1000);
wait_ms(10 * 1000);
}
#endif //MODEM_ON_BOARD
#endif //MBED_CONF_NSAPI_PRESENT

30
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/PinNames.h
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@ -49,15 +49,15 @@ typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT0 = PA_2 | ALT0,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT0 = PA_3 | ALT0,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT0 = PA_7 | ALT0,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -66,25 +66,25 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT0 = PB_1 | ALT0,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT0 = PB_4 | ALT0,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT0 = PB_5 | ALT0,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT0 = PB_8 | ALT0,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT0 = PB_9 | ALT0,
PB_10 = 0x1A,
PB_12 = 0x1C,
PB_13 = 0x1D,
@ -184,20 +184,20 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
USB_OTG_FS_SOF = PA_8,
USB_OTG_FS_VBUS = PA_9,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c
View File

@ -63,7 +63,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -120,7 +120,7 @@ void SetSysClock(void)
{
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0) {
while(1) {
while (1) {
// [TODO] Put something here to tell the user that a problem occured...
}
}

30
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/PinNames.h
View File

@ -49,15 +49,15 @@ typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_2_ALT0 = PA_2|ALT0,
PA_2_ALT0 = PA_2 | ALT0,
PA_3 = 0x03,
PA_3_ALT0 = PA_3|ALT0,
PA_3_ALT0 = PA_3 | ALT0,
PA_4 = 0x04,
PA_4_ALT0 = PA_4|ALT0,
PA_4_ALT0 = PA_4 | ALT0,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_7_ALT0 = PA_7|ALT0,
PA_7_ALT0 = PA_7 | ALT0,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
@ -66,25 +66,25 @@ typedef enum {
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PA_15_ALT0 = PA_15|ALT0,
PA_15_ALT0 = PA_15 | ALT0,
PB_0 = 0x10,
PB_0_ALT0 = PB_0|ALT0,
PB_0_ALT0 = PB_0 | ALT0,
PB_1 = 0x11,
PB_1_ALT0 = PB_1|ALT0,
PB_1_ALT0 = PB_1 | ALT0,
PB_2 = 0x12,
PB_3 = 0x13,
PB_3_ALT0 = PB_3|ALT0,
PB_3_ALT0 = PB_3 | ALT0,
PB_4 = 0x14,
PB_4_ALT0 = PB_4|ALT0,
PB_4_ALT0 = PB_4 | ALT0,
PB_5 = 0x15,
PB_5_ALT0 = PB_5|ALT0,
PB_5_ALT0 = PB_5 | ALT0,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_8_ALT0 = PB_8|ALT0,
PB_8_ALT0 = PB_8 | ALT0,
PB_9 = 0x19,
PB_9_ALT0 = PB_9|ALT0,
PB_9_ALT0 = PB_9 | ALT0,
PB_10 = 0x1A,
PB_12 = 0x1C,
PB_13 = 0x1D,
@ -175,20 +175,20 @@ typedef enum {
SPI_CS = PB_6,
PWM_OUT = PB_3,
/**** USB pins ****/
/**** USB pins ****/
USB_OTG_FS_DM = PA_11,
USB_OTG_FS_DP = PA_12,
USB_OTG_FS_ID = PA_10,
USB_OTG_FS_SOF = PA_8,
USB_OTG_FS_VBUS = PA_9,
/**** OSCILLATOR pins ****/
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
RCC_OSC_IN = PH_0,
RCC_OSC_OUT = PH_1,
/**** DEBUG pins ****/
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,

4
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c
View File

@ -65,7 +65,7 @@ void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
@ -125,7 +125,7 @@ void SetSysClock(void)
if (SetSysClock_PLL_HSI() == 0)
#endif
{
while(1) {
while (1) {
MBED_ASSERT(1);
}
}

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