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revert typos in external sources

pull/6149/head
Brendan McDonnell 2018-02-21 19:08:28 -05:00
parent 085c045fda
commit 7094e13891
183 changed files with 363 additions and 362 deletions
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2
features/FEATURE_BLE/ble/BLEInstanceBase.h
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@ -246,7 +246,7 @@ public:
private: private:
// this class is not a value type. // this class is not a value type.
// prohibit copy construction and copy assignment // prohibit copy construction and copy assignement
BLEInstanceBase(const BLEInstanceBase&); BLEInstanceBase(const BLEInstanceBase&);
BLEInstanceBase &operator=(const BLEInstanceBase&); BLEInstanceBase &operator=(const BLEInstanceBase&);
}; };

2
features/FEATURE_BLE/ble/pal/AttClient.h
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@ -75,7 +75,7 @@ struct AttClient {
* The mtu choosen for the connection is the minimum of the client Rx mtu * The mtu choosen for the connection is the minimum of the client Rx mtu
* and server Rx mtu values. * and server Rx mtu values.
* *
* If an error occurred then the mtu used remains the default value. * If an error occured then the mtu used remains the default value.
* *
* @param connection The handle of the connection to send this request to. * @param connection The handle of the connection to send this request to.
* *

2
features/FEATURE_BLE/ble/pal/GapEvents.h
View File

@ -75,7 +75,7 @@ struct GapEvent {
protected: protected:
GapEvent(GapEventType type) : type(type) { } GapEvent(GapEventType type) : type(type) { }
// Disable copy construction and copy assignment operations. // Disable copy construction and copy assignement operations.
GapEvent(const GapEvent&); GapEvent(const GapEvent&);
GapEvent& operator=(const GapEvent&); GapEvent& operator=(const GapEvent&);
}; };

2
features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h
View File

@ -63,7 +63,7 @@ typedef struct
/*! WSF buffer diagnostics - buffer allocation failure */ /*! WSF buffer diagnostics - buffer allocation failure */
typedef struct typedef struct
{ {
uint8_t taskId; /*! Task handler ID where failure occurred */ uint8_t taskId; /*! Task handler ID where failure occured */
uint16_t len; /*! Length of buffer being allocated */ uint16_t len; /*! Length of buffer being allocated */
} wsfBufDiagAllocFail_t; } wsfBufDiagAllocFail_t;

2
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c
View File

@ -57,7 +57,7 @@ void hal_sleep(void)
return; return;
} else { } else {
// next event will wakeup the CPU // next event will wakeup the CPU
// If an interrupt occurred between the test of SCB->ICSR and this // If an interrupt occured between the test of SCB->ICSR and this
// instruction, WFE will just not put the CPU to sleep // instruction, WFE will just not put the CPU to sleep
__WFE(); __WFE();
} }

2
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c
View File

@ -359,7 +359,7 @@ bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1,
/**@brief Event handler for events from the peer_database module. /**@brief Event handler for events from the peer_database module.
* *
* @param[in] p_event The event that has happened with peer id and flags. * @param[in] p_event The event that has happend with peer id and flags.
*/ */
static void pdb_evt_handler(pdb_evt_t const * p_event) static void pdb_evt_handler(pdb_evt_t const * p_event)
{ {

8
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h
View File

@ -152,10 +152,10 @@ typedef enum
typedef struct typedef struct
{ {
dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ dfu_update_status_code_t status_code; /**< Device Firmware Update status. */
uint16_t app_crc; /**< CRC of the received application. */ uint16_t app_crc; /**< CRC of the recieved application. */
uint32_t sd_size; /**< Size of the received SoftDevice. */ uint32_t sd_size; /**< Size of the recieved SoftDevice. */
uint32_t bl_size; /**< Size of the received BootLoader. */ uint32_t bl_size; /**< Size of the recieved BootLoader. */
uint32_t app_size; /**< Size of the received Application. */ uint32_t app_size; /**< Size of the recieved Application. */
uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */
} dfu_update_status_t; } dfu_update_status_t;

4
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h
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@ -721,7 +721,7 @@ typedef struct
/**@brief GAP event structure. */ /**@brief GAP event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
union /**< union alternative identified by evt_id in enclosing struct. */ union /**< union alternative identified by evt_id in enclosing struct. */
{ {
ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */
@ -1153,7 +1153,7 @@ SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t
* @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
* @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
* @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
* @retval ::NRF_ERROR_TIMEOUT A SMP timout has occurred, and further SMP operations on this link is prohibited. * @retval ::NRF_ERROR_TIMEOUT A SMP timout has occured, and further SMP operations on this link is prohibited.
*/ */
SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params));

2
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h
View File

@ -239,7 +239,7 @@ typedef struct
/**@brief GATTC event structure. */ /**@brief GATTC event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
union union

2
features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h
View File

@ -107,7 +107,7 @@ typedef struct
/**@brief L2CAP event callback event structure. */ /**@brief L2CAP event callback event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
union union
{ {
ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */

6
features/FEATURE_LWIP/lwip-interface/EthernetInterface.h
View File

@ -82,21 +82,21 @@ public:
/** Get the local IP address /** Get the local IP address
* *
* @return Null-terminated representation of the local IP address * @return Null-terminated representation of the local IP address
* or null if no IP address has been received * or null if no IP address has been recieved
*/ */
virtual const char *get_ip_address(); virtual const char *get_ip_address();
/** Get the local network mask /** Get the local network mask
* *
* @return Null-terminated representation of the local network mask * @return Null-terminated representation of the local network mask
* or null if no network mask has been received * or null if no network mask has been recieved
*/ */
virtual const char *get_netmask(); virtual const char *get_netmask();
/** Get the local gateways /** Get the local gateways
* *
* @return Null-terminated representation of the local gateway * @return Null-terminated representation of the local gateway
* or null if no network mask has been received * or null if no network mask has been recieved
*/ */
virtual const char *get_gateway(); virtual const char *get_gateway();

12
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h
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@ -249,7 +249,7 @@ extern "C"
#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occurred */ #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
@ -373,7 +373,7 @@ extern "C"
#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
#define EMAC_RINFO_ERR 0x80000000 /**< Error Occurred (OR of all errors) */ #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
@ -395,10 +395,10 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occurred */ #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
#define EMAC_TINFO_ERR 0x80000000 /**< Error Occurred (OR of all errors) */ #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
#ifdef MCB_LPC_1768 #ifdef MCB_LPC_1768
/* DP83848C PHY definition ------------------------------------------------------------ */ /* DP83848C PHY definition ------------------------------------------------------------ */
@ -417,7 +417,7 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Ability */ #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
#define EMAC_PHY_REG_LPNPA 0x08 #define EMAC_PHY_REG_LPNPA 0x08
@ -504,7 +504,7 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Ability */ #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */

2
features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG
View File

@ -3918,7 +3918,7 @@ HISTORY
++ Bug fixes: ++ Bug fixes:
* Fixed pool pbuf memory leak in pbuf_alloc(). * Fixed pool pbuf memory leak in pbuf_alloc().
Occurred if not enough PBUF_POOL pbufs for a packet pbuf chain. Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
Reported by Savin Zlobec. Reported by Savin Zlobec.
* PBUF_POOL chains had their tot_len field not set for non-first * PBUF_POOL chains had their tot_len field not set for non-first

2
features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c
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@ -1469,7 +1469,7 @@ snmp_complete_outbound_frame(struct snmp_request *request)
if (request->error_status == SNMP_ERR_TOOBIG) { if (request->error_status == SNMP_ERR_TOOBIG) {
request->error_index = 0; /* defined by RFC 1157 */ request->error_index = 0; /* defined by RFC 1157 */
} else if (request->error_index == 0) { } else if (request->error_index == 0) {
/* set index to varbind where error occurred (if not already set before, e.g. during GetBulk processing) */ /* set index to varbind where error occured (if not already set before, e.g. during GetBulk processing) */
request->error_index = request->inbound_varbind_enumerator.varbind_count; request->error_index = request->inbound_varbind_enumerator.varbind_count;
} }
} else { } else {

2
features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c
View File

@ -191,7 +191,7 @@ send_data(void)
ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_MAX_PAYLOAD_SIZE); ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_MAX_PAYLOAD_SIZE);
if (ret < 0) { if (ret < 0) {
send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occurred while reading the file."); send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occured while reading the file.");
close_handle(); close_handle();
return; return;
} }

2
features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c
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@ -1744,7 +1744,7 @@ static int ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) {
} }
endswitch: endswitch:
if (orc == CONFACK && /* Good CI */ if (orc == CONFACK && /* Good CI */
rc != CONFACK) /* but prior CI wasn't? */ rc != CONFACK) /* but prior CI wasnt? */
continue; /* Don't send this one */ continue; /* Don't send this one */
if (orc == CONFNAK) { /* Nak this CI? */ if (orc == CONFNAK) { /* Nak this CI? */

2
features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c
View File

@ -1011,7 +1011,7 @@ endswitch:
IPV6CPDEBUG((" (%s)\n", CODENAME(orc))); IPV6CPDEBUG((" (%s)\n", CODENAME(orc)));
if (orc == CONFACK && /* Good CI */ if (orc == CONFACK && /* Good CI */
rc != CONFACK) /* but prior CI wasn't? */ rc != CONFACK) /* but prior CI wasnt? */
continue; /* Don't send this one */ continue; /* Don't send this one */
if (orc == CONFNAK) { /* Nak this CI? */ if (orc == CONFNAK) { /* Nak this CI? */

2
features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c
View File

@ -2232,7 +2232,7 @@ static int lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree) {
endswitch: endswitch:
if (orc == CONFACK && /* Good CI */ if (orc == CONFACK && /* Good CI */
rc != CONFACK) /* but prior CI wasn't? */ rc != CONFACK) /* but prior CI wasnt? */
continue; /* Don't send this one */ continue; /* Don't send this one */
if (orc == CONFNAK) { /* Nak this CI? */ if (orc == CONFNAK) { /* Nak this CI? */

2
features/filesystem/fat/ChaN/ff.cpp
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@ -3299,7 +3299,7 @@ FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */
fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */
} while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
} }
if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */ if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */
if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */
/* An FAT volume is found (bsect). Following code initializes the filesystem object */ /* An FAT volume is found (bsect). Following code initializes the filesystem object */

2
features/lorawan/LoRaWANStack.cpp
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@ -860,7 +860,7 @@ void LoRaWANStack::mcps_confirm_handler(loramac_mcps_confirm_t *mcps_confirm)
} }
if (mcps_confirm->status != LORAMAC_EVENT_INFO_STATUS_OK) { if (mcps_confirm->status != LORAMAC_EVENT_INFO_STATUS_OK) {
// Couldn't schedule packet, ack not received in CONFIRMED case // Couldn't schedule packet, ack not recieved in CONFIRMED case
// or some other error happened. Discard buffer, unset the tx-ongoing // or some other error happened. Discard buffer, unset the tx-ongoing
// flag and let the application know // flag and let the application know
_tx_msg.tx_ongoing = false; _tx_msg.tx_ongoing = false;

2
features/mbedtls/inc/mbedtls/bignum.h
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@ -242,7 +242,7 @@ int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y );
void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y ); void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y );
/** /**
* \brief Safe conditional assignment X = Y if assign is 1 * \brief Safe conditional assignement X = Y if assign is 1
* *
* \param X MPI to conditionally assign to * \param X MPI to conditionally assign to
* \param Y Value to be assigned * \param Y Value to be assigned

6
features/mbedtls/inc/mbedtls/x509.h
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@ -76,7 +76,7 @@
#define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 /**< Allocation of memory failed. */ #define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 /**< Allocation of memory failed. */
#define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 /**< Read/write of file failed. */ #define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 /**< Read/write of file failed. */
#define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 /**< Destination buffer is too small. */ #define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 /**< Destination buffer is too small. */
#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occurred, eg the chain is too long or the vrfy callback failed. */ #define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occured, eg the chain is too long or the vrfy callback failed. */
/* \} name */ /* \} name */
/** /**
@ -249,7 +249,7 @@ int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *se
* *
* \param to mbedtls_x509_time to check * \param to mbedtls_x509_time to check
* *
* \return 1 if the given time is in the past or an error occurred, * \return 1 if the given time is in the past or an error occured,
* 0 otherwise. * 0 otherwise.
*/ */
int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ); int mbedtls_x509_time_is_past( const mbedtls_x509_time *to );
@ -263,7 +263,7 @@ int mbedtls_x509_time_is_past( const mbedtls_x509_time *to );
* *
* \param from mbedtls_x509_time to check * \param from mbedtls_x509_time to check
* *
* \return 1 if the given time is in the future or an error occurred, * \return 1 if the given time is in the future or an error occured,
* 0 otherwise. * 0 otherwise.
*/ */
int mbedtls_x509_time_is_future( const mbedtls_x509_time *from ); int mbedtls_x509_time_is_future( const mbedtls_x509_time *from );

2
features/mbedtls/src/ecp.c
View File

@ -1470,7 +1470,7 @@ cleanup:
/* /*
* For Montgomery curves, we do all the internal arithmetic in projective * For Montgomery curves, we do all the internal arithmetic in projective
* coordinates. Import/export of points uses only the x coordinates, which is * coordinates. Import/export of points uses only the x coordinates, which is
* internally represented as X / Z. * internaly represented as X / Z.
* *
* For scalar multiplication, we'll use a Montgomery ladder. * For scalar multiplication, we'll use a Montgomery ladder.
*/ */

2
features/mbedtls/src/error.c
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@ -481,7 +481,7 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen )
if( use_ret == -(MBEDTLS_ERR_X509_BUFFER_TOO_SMALL) ) if( use_ret == -(MBEDTLS_ERR_X509_BUFFER_TOO_SMALL) )
mbedtls_snprintf( buf, buflen, "X509 - Destination buffer is too small" ); mbedtls_snprintf( buf, buflen, "X509 - Destination buffer is too small" );
if( use_ret == -(MBEDTLS_ERR_X509_FATAL_ERROR) ) if( use_ret == -(MBEDTLS_ERR_X509_FATAL_ERROR) )
mbedtls_snprintf( buf, buflen, "X509 - A fatal error occurred, eg the chain is too long or the vrfy callback failed" ); mbedtls_snprintf( buf, buflen, "X509 - A fatal error occured, eg the chain is too long or the vrfy callback failed" );
#endif /* MBEDTLS_X509_USE_C || MBEDTLS_X509_CREATE_C */ #endif /* MBEDTLS_X509_USE_C || MBEDTLS_X509_CREATE_C */
// END generated code // END generated code

2
features/mbedtls/targets/TARGET_STM/aes_alt.h
View File

@ -32,7 +32,7 @@ extern "C" {
#endif #endif
#define ST_AES_TIMEOUT ((uint32_t) 0xFF) /* 255 ms timeout for the crypto processor */ #define ST_AES_TIMEOUT ((uint32_t) 0xFF) /* 255 ms timeout for the crypto processor */
#define ST_ERR_AES_BUSY (-0x0023) /* Crypto processor is busy, timeout occurred */ #define ST_ERR_AES_BUSY (-0x0023) /* Crypto processor is busy, timeout occured */
/** /**
* \brief AES context structure * \brief AES context structure
* *

2
features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h
View File

@ -68,7 +68,7 @@ protected:
/** Bind a specific address to a socket /** Bind a specific address to a socket
* *
* Binding a socket specifies the address and port on which to receive * Binding a socket specifies the address and port on which to recieve
* data. If the IP address is zeroed, only the port is bound. * data. If the IP address is zeroed, only the port is bound.
* *
* @param handle Socket handle * @param handle Socket handle

2
features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c
View File

@ -60,7 +60,7 @@ void thread_dhcpv6_client_set_address(int8_t interface_id, dhcpv6_client_server_
void thread_dhcp_client_init(int8_t interface) void thread_dhcp_client_init(int8_t interface)
{ {
// No support for multiple thread instances yet. // No support for multible thread instances yet.
dhcp_client.service_instance = dhcp_service_init(interface, DHCP_INSTANCE_CLIENT, NULL); dhcp_client.service_instance = dhcp_service_init(interface, DHCP_INSTANCE_CLIENT, NULL);
dhcp_client.interface = interface; dhcp_client.interface = interface;
dhcp_client.libDhcp_instance = libdhcpv6_nonTemporal_entry_get_unique_instance_id(); dhcp_client.libDhcp_instance = libdhcpv6_nonTemporal_entry_get_unique_instance_id();

8
features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c
View File

@ -552,7 +552,7 @@ static uint32_t reverse_bits(uint32_t num)
} }
static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* conf) static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* conf)
{ {
bool conflict_occurred = false; bool conflict_occured = false;
nwk_scan_params_t *scan_parameters_ptr; nwk_scan_params_t *scan_parameters_ptr;
nwk_pan_descriptor_t *result; nwk_pan_descriptor_t *result;
protocol_interface_info_entry_t *interface; protocol_interface_info_entry_t *interface;
@ -599,12 +599,12 @@ static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* con
if(result->pan_descriptor->CoordPANId == this->scan_ptr->panid) { //if pan id matches then send a conflict message if(result->pan_descriptor->CoordPANId == this->scan_ptr->panid) { //if pan id matches then send a conflict message
tr_debug("Same pan id was found on channel %d", result->pan_descriptor->LogicalChannel); tr_debug("Same pan id was found on channel %d", result->pan_descriptor->LogicalChannel);
set_channel_mask(this->scan_ptr->channel_mask,result->pan_descriptor->LogicalChannel,0); set_channel_mask(this->scan_ptr->channel_mask,result->pan_descriptor->LogicalChannel,0);
conflict_occurred = true; conflict_occured = true;
} }
result = result->next; result = result->next;
} while (result); } while (result);
if (conflict_occurred){ if (conflict_occured){
tr_debug("conflict occurred"); tr_debug("conflict occured");
this->scan_ptr->timer = eventOS_timeout_ms(thread_panid_conflict_timeout_cb, 2000, this); this->scan_ptr->timer = eventOS_timeout_ms(thread_panid_conflict_timeout_cb, 2000, this);
} }
thread_start_mac_with_link_configuration(interface,linkConfiguration); thread_start_mac_with_link_configuration(interface,linkConfiguration);

4
features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h
View File

@ -122,7 +122,7 @@ struct fnet_dns_params
fnet_address_family_t addr_family; /**< @brief Family of the IP Address which is queried.*/ fnet_address_family_t addr_family; /**< @brief Family of the IP Address which is queried.*/
fnet_dns_callback_resolved_t callback; /**< @brief Pointer to the callback function defined by fnet_dns_callback_resolved_t callback; /**< @brief Pointer to the callback function defined by
* @ref fnet_dns_callback_resolved_t. It is called when the * @ref fnet_dns_callback_resolved_t. It is called when the
* DNS-client resolving is finished or an error has occurred. */ * DNS-client resolving is finished or an error is occurred. */
fnet_uint32_t cookie; /**< @brief Optional application-specific parameter. @n fnet_uint32_t cookie; /**< @brief Optional application-specific parameter. @n
* It's passed to the @c callback * It's passed to the @c callback
* function as input parameter. */ * function as input parameter. */
@ -155,7 +155,7 @@ extern "C" {
* The resolved IP-address will be passed to the @ref fnet_dns_callback_resolved_t callback function, * The resolved IP-address will be passed to the @ref fnet_dns_callback_resolved_t callback function,
* which is set in @c params. @n * which is set in @c params. @n
* The DNS service is released automatically as soon as the * The DNS service is released automatically as soon as the
* resolving is finished or an error has occurred. * resolving is finished or an error is occurred.
* *
******************************************************************************/ ******************************************************************************/
fnet_return_t fnet_dns_init( struct fnet_dns_params *params ); fnet_return_t fnet_dns_init( struct fnet_dns_params *params );

4
features/unsupported/USBDevice/USBMSD/USBMSD.cpp
View File

@ -170,7 +170,7 @@ bool USBMSD::EPBULK_OUT_callback() {
} }
break; break;
// an error has occurred: stall endpoint and send CSW // an error has occured: stall endpoint and send CSW
default: default:
stallEndpoint(EPBULK_OUT); stallEndpoint(EPBULK_OUT);
csw.Status = CSW_ERROR; csw.Status = CSW_ERROR;
@ -207,7 +207,7 @@ bool USBMSD::EPBULK_IN_callback() {
stage = READ_CBW; stage = READ_CBW;
break; break;
// an error has occurred // an error has occured
default: default:
stallEndpoint(EPBULK_IN); stallEndpoint(EPBULK_IN);
sendCSW(); sendCSW();

4
features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c
View File

@ -40,7 +40,7 @@ static const char *epStatusStr[] = {
/* /*
* USBDEP_Ep0Handler() is called each time a packet has been transmitted * USBDEP_Ep0Handler() is called each time a packet has been transmitted
* or received on the default endpoint. * or recieved on the default endpoint.
* A state machine navigate us through the phases of a control transfer * A state machine navigate us through the phases of a control transfer
* according to "chapter 9" in the USB spec. * according to "chapter 9" in the USB spec.
*/ */
@ -417,7 +417,7 @@ void USBDEP_Ep0Handler( USBD_Device_TypeDef *device )
/* /*
* USBDEP_EpHandler() is called each time a packet has been transmitted * USBDEP_EpHandler() is called each time a packet has been transmitted
* or received on an endpoint other than the default endpoint. * or recieved on an endpoint other than the default endpoint.
*/ */
void USBDEP_EpHandler( uint8_t epAddr ) void USBDEP_EpHandler( uint8_t epAddr )
{ {

2
features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h
View File

@ -48,7 +48,7 @@ public:
* Pin Options: * Pin Options:
* (5, 6, 7) or (11, 12, 13) * (5, 6, 7) or (11, 12, 13)
* *
* mosi or miso can be specified as NC if not used * mosi or miso can be specfied as NC if not used
* *
* @param mosi SPI Master Out, Slave In pin * @param mosi SPI Master Out, Slave In pin
* @param miso SPI Master In, Slave Out pin * @param miso SPI Master In, Slave Out pin

6
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c
View File

@ -58,11 +58,11 @@ int ethernet_receive()
return smsc9220_peek_next_packet_size(); return smsc9220_peek_next_packet_size();
} }
/* Read from an received ethernet packet.*/ /* Read from an recevied ethernet packet.*/
/* After receive returned a number bigger than 0 it is*/ /* After receive returnd a number bigger than 0 it is*/
/* possible to read bytes from this packet.*/ /* possible to read bytes from this packet.*/
/* Read will write up to size bytes into data.*/ /* Read will write up to size bytes into data.*/
/* It is possible to use read multiple times.*/ /* It is possible to use read multible times.*/
/* Each time read will start reading after the last read byte before. */ /* Each time read will start reading after the last read byte before. */
int ethernet_read(char *data, int dlen) int ethernet_read(char *data, int dlen)
{ {

2
targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c
View File

@ -375,7 +375,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
if(rxfifo_stat != 0) { // Fetch status of this packet if(rxfifo_stat != 0) { // Fetch status of this packet
pktsize = ((rxfifo_stat >> 16) & 0x3FFF); pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
if(rxfifo_stat & (1 << 15)) { if(rxfifo_stat & (1 << 15)) {
printf("Error occurred during receiving of packets on the bus.\n"); printf("Error occured during receiving of packets on the bus.\n");
return 1; return 1;
} else { } else {
/* Below formula (recommended by SMSC9220 code) /* Below formula (recommended by SMSC9220 code)

2
targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h
View File

@ -30,7 +30,7 @@ extern "C" {
// send ethernet write buffer, returning the packet size sent // send ethernet write buffer, returning the packet size sent
int ethernet_transmission(unsigned char * pkt, unsigned int length); int ethernet_transmission(unsigned char * pkt, unsigned int length);
// receive from ethernet buffer, returning packet size, or 0 if no packet // recieve from ethernet buffer, returning packet size, or 0 if no packet
int ethernet_reception(unsigned int *recvbuf, unsigned int *index); int ethernet_reception(unsigned int *recvbuf, unsigned int *index);
// get the ethernet address // get the ethernet address

6
targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c
View File

@ -136,11 +136,11 @@ int ethernet_receive()
return 0; return 0;
} }
// Read from an received ethernet packet. // Read from an recevied ethernet packet.
// After receive returned a number bigger than 0 it is // After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet. // possible to read bytes from this packet.
// Read will write up to size bytes into data. // Read will write up to size bytes into data.
// It is possible to use read multiple times. // It is possible to use read multible times.
// Each time read will start reading after the last read byte before. // Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen) int ethernet_read(char *data, int dlen)

2
targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c
View File

@ -375,7 +375,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index)
if(rxfifo_stat != 0) { // Fetch status of this packet if(rxfifo_stat != 0) { // Fetch status of this packet
pktsize = ((rxfifo_stat >> 16) & 0x3FFF); pktsize = ((rxfifo_stat >> 16) & 0x3FFF);
if(rxfifo_stat & (1 << 15)) { if(rxfifo_stat & (1 << 15)) {
printf("Error occurred during receiving of packets on the bus.\n"); printf("Error occured during receiving of packets on the bus.\n");
return 1; return 1;
} else { } else {
/* Below formula (recommended by SMSC9220 code) /* Below formula (recommended by SMSC9220 code)

2
targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h
View File

@ -30,7 +30,7 @@ extern "C" {
// send ethernet write buffer, returning the packet size sent // send ethernet write buffer, returning the packet size sent
int ethernet_transmission(unsigned char * pkt, unsigned int length); int ethernet_transmission(unsigned char * pkt, unsigned int length);
// receive from ethernet buffer, returning packet size, or 0 if no packet // recieve from ethernet buffer, returning packet size, or 0 if no packet
int ethernet_reception(unsigned int *recvbuf, unsigned int *index); int ethernet_reception(unsigned int *recvbuf, unsigned int *index);
// get the ethernet address // get the ethernet address

6
targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c
View File

@ -136,11 +136,11 @@ int ethernet_receive()
return 0; return 0;
} }
// Read from an received ethernet packet. // Read from an recevied ethernet packet.
// After receive returned a number bigger than 0 it is // After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet. // possible to read bytes from this packet.
// Read will write up to size bytes into data. // Read will write up to size bytes into data.
// It is possible to use read multiple times. // It is possible to use read multible times.
// Each time read will start reading after the last read byte before. // Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen) int ethernet_read(char *data, int dlen)

2
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c
View File

@ -327,7 +327,7 @@ int spi_master_write(spi_t *obj, int value)
/** Write a block out in master mode and receive a value /** Write a block out in master mode and receive a value
* *
* The total number of bytes sent and received will be the maximum of * The total number of bytes sent and recieved will be the maximum of
* tx_length and rx_length. The bytes written will be padded with the * tx_length and rx_length. The bytes written will be padded with the
* value 0xff. * value 0xff.
* *

2
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c
View File

@ -303,7 +303,7 @@ ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG*
* *
* @details The timer can be configured to capture the timer value when a specific event occurs. The * @details The timer can be configured to capture the timer value when a specific event occurs. The
* list of events can be found in the hardware reference manual. The callback function specified * list of events can be found in the hardware reference manual. The callback function specified
* in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occurred. The * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The
* user can then read the captured value by calling #adi_tmr_GetCaptureCount. * user can then read the captured value by calling #adi_tmr_GetCaptureCount.
* *
* @note This function can only be called when the timer is disabled. * @note This function can only be called when the timer is disabled.

2
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c
View File

@ -1814,7 +1814,7 @@ ADI_UART_RESULT adi_uart_GetBaudRate(
#endif /* ADI_DEBUG */ #endif /* ADI_DEBUG */
/* If an error occurred during autobaud this value will be set to a /* If an error occured during autobaud this value will be set to a
non-zero value. The specific error can be found by checking against non-zero value. The specific error can be found by checking against
#ADI_UART_EVENT. #ADI_UART_EVENT.
*/ */

2
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c
View File

@ -302,7 +302,7 @@ int spi_master_write(spi_t *obj, int value)
/** Write a block out in master mode and receive a value /** Write a block out in master mode and receive a value
* *
* The total number of bytes sent and received will be the maximum of * The total number of bytes sent and recieved will be the maximum of
* tx_length and rx_length. The bytes written will be padded with the * tx_length and rx_length. The bytes written will be padded with the
* value 0xff. * value 0xff.
* *

2
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c
View File

@ -284,7 +284,7 @@ ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG
* *
* @details The timer can be configured to capture the timer value when a specific event occurs. The * @details The timer can be configured to capture the timer value when a specific event occurs. The
* list of events can be found in the hardware reference manual. The callback function specified * list of events can be found in the hardware reference manual. The callback function specified
* in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occurred. The * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The
* user can then read the captured value by calling #adi_tmr_GetCaptureCount. * user can then read the captured value by calling #adi_tmr_GetCaptureCount.
* *
* @note This function can only be called when the timer is disabled. * @note This function can only be called when the timer is disabled.

2
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c
View File

@ -1808,7 +1808,7 @@ ADI_UART_RESULT adi_uart_GetBaudRate(
#endif /* ADI_DEBUG */ #endif /* ADI_DEBUG */
/* If an error occurred during autobaud this value will be set to a /* If an error occured during autobaud this value will be set to a
non-zero value. The specific error can be found by checking against non-zero value. The specific error can be found by checking against
#ADI_UART_EVENT. #ADI_UART_EVENT.
*/ */

6
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c
View File

@ -1354,10 +1354,10 @@ enum status_code tcc_set_pattern(
* *
* \return Bitmask of \c TCC_STATUS_* flags. * \return Bitmask of \c TCC_STATUS_* flags.
* *
* \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occurred * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occured
* \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state * \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state
* \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occurred * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occured
* \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occurred * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occured
* \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present
* \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present
* \retval TCC_STATUS_SYNC_READY None of register is syncing * \retval TCC_STATUS_SYNC_READY None of register is syncing

2
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h
View File

@ -852,7 +852,7 @@ enum tcc_callback {
#define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8)) #define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8))
/** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */ /** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */
#define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16)) #define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16))
/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occurred. */ /** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */
#define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18)) #define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18))
/** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */ /** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */
#define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20)) #define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20))

2
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c
View File

@ -1024,7 +1024,7 @@ int serial_rx_irq_handler_asynch(serial_t *obj)
event |= SERIAL_EVENT_RX_CHARACTER_MATCH; event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
} }
/* Return to the call back if character match occurred */ /* Return to the call back if character match occured */
if(event != 0) { if(event != 0) {
serial_rx_abort_asynch(obj); serial_rx_abort_asynch(obj);
return event & obj->serial.events; return event & obj->serial.events;

2
targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h
View File

@ -75,7 +75,7 @@ typedef struct {
#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ #define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */
#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ #define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */
#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ #define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */
#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occurred */ #define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occured */
#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h
View File

@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
* *
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using * read FlEXCAN_ErrorFlag and distinguish which error is occur using
* @ref _flexcan_error_flags enumerations. * @ref _flexcan_error_flags enumerations.
*/ */
enum _flexcan_flags enum _flexcan_flags

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c
View File

@ -37,7 +37,7 @@ enum _qspi_transfer_state
{ {
kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */
kQSPI_TxIdle, /*!< Transfer is done. */ kQSPI_TxIdle, /*!< Transfer is done. */
kQSPI_TxError /*!< Transfer error occurred. */ kQSPI_TxError /*!< Transfer error occured. */
}; };
#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index)) #define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c
View File

@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check
* TRNG access mode in the SA-TRNG Miscellaneous Control Register. * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
* *
* Values: * Values:
* - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
* Control Register's access mode bit. * Control Register's access mode bit.
* - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
* TRNG register programming. * TRNG register programming.

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h
View File

@ -56,7 +56,7 @@ struct _sai_dma_handle
uint8_t bytesPerFrame; /*!< Bytes in a frame */ uint8_t bytesPerFrame; /*!< Bytes in a frame */
uint8_t channel; /*!< Which Data channel SAI use */ uint8_t channel; /*!< Which Data channel SAI use */
uint32_t state; /*!< SAI DMA transfer internal state */ uint32_t state; /*!< SAI DMA transfer internal state */
sai_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ sai_dma_callback_t callback; /*!< Callback for users while transfer finish or error occured */
void *userData; /*!< User callback parameter */ void *userData; /*!< User callback parameter */
sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */
size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c
View File

@ -37,7 +37,7 @@ enum _qspi_transfer_state
{ {
kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */
kQSPI_TxIdle, /*!< Transfer is done. */ kQSPI_TxIdle, /*!< Transfer is done. */
kQSPI_TxError /*!< Transfer error occurred. */ kQSPI_TxError /*!< Transfer error occured. */
}; };
#define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index)) #define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index))

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c
View File

@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check
* TRNG access mode in the SA-TRNG Miscellaneous Control Register. * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
* *
* Values: * Values:
* - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
* Control Register's access mode bit. * Control Register's access mode bit.
* - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
* TRNG register programming. * TRNG register programming.

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c
View File

@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check
* TRNG access mode in the SA-TRNG Miscellaneous Control Register. * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
* *
* Values: * Values:
* - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
* Control Register's access mode bit. * Control Register's access mode bit.
* - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
* TRNG register programming. * TRNG register programming.

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h
View File

@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
* *
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using * read FlEXCAN_ErrorFlag and distinguish which error is occur using
* @ref _flexcan_error_flags enumerations. * @ref _flexcan_error_flags enumerations.
*/ */
enum _flexcan_flags enum _flexcan_flags

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h
View File

@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
* *
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using * read FlEXCAN_ErrorFlag and distinguish which error is occur using
* @ref _flexcan_error_flags enumerations. * @ref _flexcan_error_flags enumerations.
*/ */
enum _flexcan_flags enum _flexcan_flags

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c
View File

@ -37,7 +37,7 @@ enum _sai_transfer_state
{ {
kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Busy = 0x0U, /*!< SAI is busy */
kSAI_Idle, /*!< Transfer is done. */ kSAI_Idle, /*!< Transfer is done. */
kSAI_Error /*!< Transfer error occurred. */ kSAI_Error /*!< Transfer error occured. */
}; };
/*! @brief Typedef for sai tx interrupt handler. */ /*! @brief Typedef for sai tx interrupt handler. */

2
targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h
View File

@ -75,7 +75,7 @@ void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us);
void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us);
/** /**
* @brief Check if the timeout has occurred. * @brief Check if the timeout has occured.
* @param tmr TMR module to operate on * @param tmr TMR module to operate on
* @returns E_NO_ERROR if the timeout has not occurred, E_TIME_OUT if it has. * @returns E_NO_ERROR if the timeout has not occurred, E_TIME_OUT if it has.
*/ */

4
targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h
View File

@ -129,7 +129,7 @@ int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode);
* @param dir Operation to perform, see #mxc_aes_dir_t for supported operations. * @param dir Operation to perform, see #mxc_aes_dir_t for supported operations.
* *
* @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out. * @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out.
* @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occurred. * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occured.
*/ */
int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir); int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir);
@ -143,7 +143,7 @@ int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_
* @return #E_SUCCESS Output data was written to the location pointed * @return #E_SUCCESS Output data was written to the location pointed
* to by @a *out. * to by @a *out.
* @return A @ref MXC_Error_Codes "Error Code" indicating the error that * @return A @ref MXC_Error_Codes "Error Code" indicating the error that
* occurred. * occured.
*/ */
int AES_GetOutput(uint8_t *out); int AES_GetOutput(uint8_t *out);

2
targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h
View File

@ -83,7 +83,7 @@ void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us);
void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us);
/** /**
* @brief Check if the timeout has occurred. * @brief Check if the timeout has occured.
* @param tmr TMR module to operate on * @param tmr TMR module to operate on
* @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has. * @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has.
*/ */

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h
View File

@ -283,7 +283,7 @@ typedef struct
/**@brief GATTC event structure. */ /**@brief GATTC event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
union union

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h
View File

@ -119,7 +119,7 @@ typedef struct
/**@brief L2CAP event callback event structure. */ /**@brief L2CAP event callback event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
union union
{ {
ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h
View File

@ -283,7 +283,7 @@ typedef struct
/**@brief GATTC event structure. */ /**@brief GATTC event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
union union

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h
View File

@ -119,7 +119,7 @@ typedef struct
/**@brief L2CAP event callback event structure. */ /**@brief L2CAP event callback event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
union union
{ {
ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h
View File

@ -301,7 +301,7 @@ typedef struct
/**@brief GATTC event structure. */ /**@brief GATTC event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
union union

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h
View File

@ -118,7 +118,7 @@ typedef struct
/**@brief L2CAP event callback event structure. */ /**@brief L2CAP event callback event structure. */
typedef struct typedef struct
{ {
uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t conn_handle; /**< Connection Handle on which event occured. */
union union
{ {
ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */

6
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h
View File

@ -62,7 +62,7 @@
/**@brief Error Log Data structure. /**@brief Error Log Data structure.
* *
* @details The structure contains the error, message/filename, line number as well as the current * @details The structure contains the error, message/filename, line number as well as the current
* stack, at the time where an error occurred. * stack, at the time where an error occured.
*/ */
typedef struct typedef struct
{ {
@ -82,8 +82,8 @@ typedef struct
* *
* @param[in] err_code Error code to be logged. * @param[in] err_code Error code to be logged.
* @param[in] p_message Message to be written to the flash together with stack dump, usually * @param[in] p_message Message to be written to the flash together with stack dump, usually
* the file name where the error occurred. * the file name where the error occured.
* @param[in] line_number Line number where the error occurred. * @param[in] line_number Line number where the error occured.
* *
* @return NRF_SUCCESS on successful writing of the error log. * @return NRF_SUCCESS on successful writing of the error log.
* *

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c
View File

@ -67,7 +67,7 @@ static void internal_state_reset(gccm_t * gccm)
/**@brief Event handler for events from the peer_database module. /**@brief Event handler for events from the peer_database module.
* *
* @param[in] p_event The event that has happened with peer id and flags. * @param[in] p_event The event that has happend with peer id and flags.
*/ */
static void pdb_evt_handler(pdb_evt_t const * p_event) static void pdb_evt_handler(pdb_evt_t const * p_event)
{ {

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c
View File

@ -116,7 +116,7 @@ static void service_changed_pending_set(void)
/**@brief Event handler for events from the peer_database module. /**@brief Event handler for events from the peer_database module.
* *
* @param[in] p_event The event that has happened with peer id and flags. * @param[in] p_event The event that has happend with peer id and flags.
*/ */
static void pdb_evt_handler(pdb_evt_t const * p_event) static void pdb_evt_handler(pdb_evt_t const * p_event)
{ {

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c
View File

@ -351,7 +351,7 @@ bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1,
/**@brief Event handler for events from the peer_database module. /**@brief Event handler for events from the peer_database module.
* *
* @param[in] p_event The event that has happened with peer id and flags. * @param[in] p_event The event that has happend with peer id and flags.
*/ */
static void pdb_evt_handler(pdb_evt_t const * p_event) static void pdb_evt_handler(pdb_evt_t const * p_event)
{ {

4
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h
View File

@ -13385,8 +13385,8 @@
/* Bit 0 : Overrun error */ /* Bit 0 : Overrun error */
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
/* Register: TWI_ENABLE */ /* Register: TWI_ENABLE */
/* Description: Enable TWI */ /* Description: Enable TWI */

8
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h
View File

@ -180,10 +180,10 @@ typedef enum
typedef struct typedef struct
{ {
dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ dfu_update_status_code_t status_code; /**< Device Firmware Update status. */
uint16_t app_crc; /**< CRC of the received application. */ uint16_t app_crc; /**< CRC of the recieved application. */
uint32_t sd_size; /**< Size of the received SoftDevice. */ uint32_t sd_size; /**< Size of the recieved SoftDevice. */
uint32_t bl_size; /**< Size of the received BootLoader. */ uint32_t bl_size; /**< Size of the recieved BootLoader. */
uint32_t app_size; /**< Size of the received Application. */ uint32_t app_size; /**< Size of the recieved Application. */
uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */
} dfu_update_status_t; } dfu_update_status_t;

6
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h
View File

@ -65,7 +65,7 @@ extern "C" {
/**@brief Error Log Data structure. /**@brief Error Log Data structure.
* *
* @details The structure contains the error, message/filename, line number as well as the current * @details The structure contains the error, message/filename, line number as well as the current
* stack, at the time where an error occurred. * stack, at the time where an error occured.
*/ */
typedef struct typedef struct
{ {
@ -85,8 +85,8 @@ typedef struct
* *
* @param[in] err_code Error code to be logged. * @param[in] err_code Error code to be logged.
* @param[in] p_message Message to be written to the flash together with stack dump, usually * @param[in] p_message Message to be written to the flash together with stack dump, usually
* the file name where the error occurred. * the file name where the error occured.
* @param[in] line_number Line number where the error occurred. * @param[in] line_number Line number where the error occured.
* *
* @return NRF_SUCCESS on successful writing of the error log. * @return NRF_SUCCESS on successful writing of the error log.
* *

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c
View File

@ -126,7 +126,7 @@ static void service_changed_pending_set(void)
/**@brief Event handler for events from the Peer Database module. /**@brief Event handler for events from the Peer Database module.
* This function is extern in Peer Database. * This function is extern in Peer Database.
* *
* @param[in] p_event The event that has happened with peer id and flags. * @param[in] p_event The event that has happend with peer id and flags.
*/ */
void gscm_pdb_evt_handler(pdb_evt_t const * p_event) void gscm_pdb_evt_handler(pdb_evt_t const * p_event)
{ {

2
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c
View File

@ -365,7 +365,7 @@ bool im_is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1
/**@brief Event handler for events from the Peer Database module. /**@brief Event handler for events from the Peer Database module.
* This function is extern in Peer Database. * This function is extern in Peer Database.
* *
* @param[in] p_event The event that has happened with peer id and flags. * @param[in] p_event The event that has happend with peer id and flags.
*/ */
void im_pdb_evt_handler(pdb_evt_t const * p_event) void im_pdb_evt_handler(pdb_evt_t const * p_event)
{ {

4
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h
View File

@ -11762,8 +11762,8 @@
/* Bit 0 : Overrun error */ /* Bit 0 : Overrun error */
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
/* Register: TWI_ENABLE */ /* Register: TWI_ENABLE */
/* Description: Enable TWI */ /* Description: Enable TWI */

4
targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h
View File

@ -11114,8 +11114,8 @@
/* Bit 0 : Overrun error */ /* Bit 0 : Overrun error */
#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
/* Register: TWI_ENABLE */ /* Register: TWI_ENABLE */

20
targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c
View File

@ -112,7 +112,7 @@ typedef struct {
void (*tx_asynch_handler)(); void (*tx_asynch_handler)();
uint32_t events_wanted; uint32_t events_wanted;
uint32_t events_occurred; uint32_t events_occured;
#define UART_IRQ_TX 1 #define UART_IRQ_TX 1
#define UART_IRQ_RX 2 #define UART_IRQ_RX 2
@ -165,13 +165,13 @@ void UART_IRQ_HANDLER(void)
if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH && if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH &&
rx_data == UART_CB.char_match) { rx_data == UART_CB.char_match) {
// If it does, report the match and abort further receiving. // If it does, report the match and abort further receiving.
UART_CB.events_occurred |= SERIAL_EVENT_RX_CHARACTER_MATCH; UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH;
if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) { if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) {
end_rx = true; end_rx = true;
} }
} }
if (++UART_CB.rx_pos >= UART_CB.rx_length) { if (++UART_CB.rx_pos >= UART_CB.rx_length) {
UART_CB.events_occurred |= SERIAL_EVENT_RX_COMPLETE; UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE;
end_rx = true; end_rx = true;
} }
if (end_rx) { if (end_rx) {
@ -215,7 +215,7 @@ void UART_IRQ_HANDLER(void)
// 'serial_writable' function to work properly. // 'serial_writable' function to work properly.
end_asynch_tx(); end_asynch_tx();
UART_CB.events_occurred |= SERIAL_EVENT_TX_COMPLETE; UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE;
if (UART_CB.tx_asynch_handler) { if (UART_CB.tx_asynch_handler) {
// Use local variable to make it possible to start a next // Use local variable to make it possible to start a next
// transfer from callback routine. // transfer from callback routine.
@ -239,15 +239,15 @@ void UART_IRQ_HANDLER(void)
uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE); uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE);
if (UART_CB.rx_asynch_handler) { if (UART_CB.rx_asynch_handler) {
UART_CB.events_occurred |= SERIAL_EVENT_ERROR; UART_CB.events_occured |= SERIAL_EVENT_ERROR;
if (errorsrc & NRF_UART_ERROR_PARITY_MASK) { if (errorsrc & NRF_UART_ERROR_PARITY_MASK) {
UART_CB.events_occurred |= SERIAL_EVENT_RX_PARITY_ERROR; UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR;
} }
if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) { if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) {
UART_CB.events_occurred |= SERIAL_EVENT_RX_FRAMING_ERROR; UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR;
} }
if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) { if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) {
UART_CB.events_occurred |= SERIAL_EVENT_RX_OVERRUN_ERROR; UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR;
} }
UART_CB.rx_asynch_handler(); UART_CB.rx_asynch_handler();
} }
@ -641,8 +641,8 @@ uint8_t serial_rx_active(serial_t *obj)
int serial_irq_handler_asynch(serial_t *obj) int serial_irq_handler_asynch(serial_t *obj)
{ {
(void)obj; (void)obj;
uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occurred; uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured;
UART_CB.events_occurred &= (~events_to_report); UART_CB.events_occured &= (~events_to_report);
return events_to_report; return events_to_report;
} }

2
targets/TARGET_NORDIC/TARGET_NRF5/sleep.c
View File

@ -66,7 +66,7 @@ void hal_sleep(void)
return; return;
} else { } else {
// next event will wakeup the CPU // next event will wakeup the CPU
// If an interrupt occurred between the test of SCB->ICSR and this // If an interrupt occured between the test of SCB->ICSR and this
// instruction, WFE will just not put the CPU to sleep // instruction, WFE will just not put the CPU to sleep
__WFE(); __WFE();
} }

40
targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
View File

@ -3469,7 +3469,7 @@ typedef struct {
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
* | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
* | | |The flag is set if any wake-up source has occurred. Refer Power Modes and Wake-up Sources chapter. * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
* | | |Note1: Write 1 to clear the bit to 0. * | | |Note1: Write 1 to clear the bit to 0.
* | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
* |[7] |PDEN |System Power-down Enable (Write Protect) * |[7] |PDEN |System Power-down Enable (Write Protect)
@ -25914,7 +25914,7 @@ typedef struct {
* | | |0 = DMA Disabled. * | | |0 = DMA Disabled.
* | | |1 = DMA Enabled. * | | |1 = DMA Enabled.
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |Note: If target abort has occurred, DMAEN will be cleared. * | | |Note: If target abort is occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset * |[1] |DMARST |Software Engine Reset
* | | |0 = No effect. * | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers * | | |1 = Reset internal state machine and pointers
@ -26006,7 +26006,7 @@ typedef struct {
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
* | | |When Target Abort has occurred, please reset all engine. * | | |When Target Abort is occurred, please reset all engine.
* | | |0 = No bus ERROR response received. * | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received. * | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it. * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
@ -26119,12 +26119,12 @@ typedef struct {
* | | |Note: This bit is read only, but can be cleared by writing '1' to it. * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
* | | |When CRC error has occurred, software should reset SD engine * | | |When CRC error is occurred, software should reset SD engine
* | | |Some response (ex * | | |Some response (ex
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
* | | |In this condition, software should ignore CRC error and clears this bit manually. * | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error has occurred. * | | |0 = No CRC error is occurred.
* | | |1 = CRC error has occurred. * | | |1 = CRC error is occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it. * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only) * |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in * | | |SD host will check CRC7 correctness during each response in
@ -27705,60 +27705,60 @@ typedef struct {
* | | |This bit conveys the interrupt status for USB specific events endpoint * | | |This bit conveys the interrupt status for USB specific events endpoint
* | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[1] |CEPIF |Control Endpoint Interrupt * |[1] |CEPIF |Control Endpoint Interrupt
* | | |This bit conveys the interrupt status for control endpoint * | | |This bit conveys the interrupt status for control endpoint
* | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[2] |EPAIF |Endpoint a Interrupt * |[2] |EPAIF |Endpoint a Interrupt
* | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[3] |EPBIF |Endpoint B Interrupt * |[3] |EPBIF |Endpoint B Interrupt
* | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[4] |EPCIF |Endpoint C Interrupt * |[4] |EPCIF |Endpoint C Interrupt
* | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[5] |EPDIF |Endpoint D Interrupt * |[5] |EPDIF |Endpoint D Interrupt
* | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[6] |EPEIF |Endpoint E Interrupt * |[6] |EPEIF |Endpoint E Interrupt
* | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[7] |EPFIF |Endpoint F Interrupt * |[7] |EPFIF |Endpoint F Interrupt
* | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[8] |EPGIF |Endpoint G Interrupt * |[8] |EPGIF |Endpoint G Interrupt
* | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[9] |EPHIF |Endpoint H Interrupt * |[9] |EPHIF |Endpoint H Interrupt
* | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[10] |EPIIF |Endpoint I Interrupt * |[10] |EPIIF |Endpoint I Interrupt
* | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[11] |EPJIF |Endpoint J Interrupt * |[11] |EPJIF |Endpoint J Interrupt
* | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[12] |EPKIF |Endpoint K Interrupt * |[12] |EPKIF |Endpoint K Interrupt
* | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[13] |EPLIF |Endpoint L Interrupt * |[13] |EPLIF |Endpoint L Interrupt
* | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* @var HSUSBD_T::GINTEN * @var HSUSBD_T::GINTEN
* Offset: 0x08 Global Interrupt Enable Register * Offset: 0x08 Global Interrupt Enable Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------

6
targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h
View File

@ -10976,18 +10976,18 @@ typedef struct {
* |[0] |BUS_STS |BUS Interrupt Status * |[0] |BUS_STS |BUS Interrupt Status
* | | |The BUS event means there is bus suspense or bus resume in the bus. * | | |The BUS event means there is bus suspense or bus resume in the bus.
* | | |This bit is used to indicate that there is one of events in the bus. * | | |This bit is used to indicate that there is one of events in the bus.
* | | |0 = No BUS event has occurred. * | | |0 = No BUS event is occurred.
* | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0]. * | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0].
* |[1] |USB_STS |USB Interrupt Status * |[1] |USB_STS |USB Interrupt Status
* | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus. * | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus.
* | | |This bit is used to indicate that there is one of events in the bus. * | | |This bit is used to indicate that there is one of events in the bus.
* | | |0 = No USB event has occurred. * | | |0 = No USB event is occurred.
* | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7. * | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7.
* |[2] |FLD_STS |Floating Interrupt Status * |[2] |FLD_STS |Floating Interrupt Status
* | | |0 = There is not attached event in the USB. * | | |0 = There is not attached event in the USB.
* | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2]. * | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2].
* |[3] |WKEUP_STS |Wake-Up Interrupt Status * |[3] |WKEUP_STS |Wake-Up Interrupt Status
* | | |0 = No wake-up event has occurred. * | | |0 = No wake-up event is occurred.
* | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3]. * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3].
* |[16] |EPEVT0 |USB Event Status On EP0 * |[16] |EPEVT0 |USB Event Status On EP0
* | | |0 = No event occurred in Endpoint 0. * | | |0 = No event occurred in Endpoint 0.

40
targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h
View File

@ -20502,7 +20502,7 @@ typedef struct {
* | | |Note: This bit is only cleared by writing 1 to it. * | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow Or Underflow Flag * |[2] |OVUNF |QEI Counter Overflow Or Underflow Flag
* | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode. * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode.
* | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT. * | | |Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT.
* | | |0 = No overflow or underflow occurs in QEI counter. * | | |0 = No overflow or underflow occurs in QEI counter.
* | | |1 = QEI counter occurs counting overflow or underflow. * | | |1 = QEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it. * | | |Note: This bit is only cleared by writing 1 to it.
@ -22305,7 +22305,7 @@ typedef struct {
* | | |0 = DMA Disabled. * | | |0 = DMA Disabled.
* | | |1 = DMA Enabled. * | | |1 = DMA Enabled.
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |Note: If target abort has occurred, DMAEN will be cleared. * | | |Note: If target abort is occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset * |[1] |DMARST |Software Engine Reset
* | | |0 = No effect. * | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers. * | | |1 = Reset internal state machine and pointers.
@ -22432,7 +22432,7 @@ typedef struct {
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation.
* | | |When Target Abort has occurred, please reset all engine. * | | |When Target Abort is occurred, please reset all engine.
* | | |0 = No bus ERROR response received. * | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received. * | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it. * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
@ -22583,12 +22583,12 @@ typedef struct {
* | | |Note: This bit is read only, but can be cleared by writing '1' to it. * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only) * |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer.
* | | |When CRC error has occurred, software should reset SD engine. * | | |When CRC error is occurred, software should reset SD engine.
* | | |Some response (ex. * | | |Some response (ex.
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag. * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag.
* | | |In this condition, software should ignore CRC error and clears this bit manually. * | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error has occurred. * | | |0 = No CRC error is occurred.
* | | |1 = CRC error has occurred. * | | |1 = CRC error is occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it. * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only) * |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in. * | | |SD host will check CRC7 correctness during each response in.
@ -27165,60 +27165,60 @@ typedef struct {
* | | |This bit conveys the interrupt status for USB specific events endpoint. * | | |This bit conveys the interrupt status for USB specific events endpoint.
* | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[1] |CEPIF |Control Endpoint Interrupt * |[1] |CEPIF |Control Endpoint Interrupt
* | | |This bit conveys the interrupt status for control endpoint. * | | |This bit conveys the interrupt status for control endpoint.
* | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[2] |EPAIF |Endpoints A Interrupt * |[2] |EPAIF |Endpoints A Interrupt
* | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[3] |EPBIF |Endpoints B Interrupt * |[3] |EPBIF |Endpoints B Interrupt
* | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[4] |EPCIF |Endpoints C Interrupt * |[4] |EPCIF |Endpoints C Interrupt
* | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[5] |EPDIF |Endpoints D Interrupt * |[5] |EPDIF |Endpoints D Interrupt
* | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[6] |EPEIF |Endpoints E Interrupt * |[6] |EPEIF |Endpoints E Interrupt
* | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[7] |EPFIF |Endpoints F Interrupt * |[7] |EPFIF |Endpoints F Interrupt
* | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[8] |EPGIF |Endpoints G Interrupt * |[8] |EPGIF |Endpoints G Interrupt
* | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[9] |EPHIF |Endpoints H Interrupt * |[9] |EPHIF |Endpoints H Interrupt
* | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[10] |EPIIF |Endpoints I Interrupt * |[10] |EPIIF |Endpoints I Interrupt
* | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[11] |EPJIF |Endpoints J Interrupt * |[11] |EPJIF |Endpoints J Interrupt
* | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[12] |EPKIF |Endpoints K Interrupt * |[12] |EPKIF |Endpoints K Interrupt
* | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
* |[13] |EPLIF |Endpoints L Interrupt * |[13] |EPLIF |Endpoints L Interrupt
* | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred. * | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event has occurred. * | | |1 = The related interrupt event is occurred.
*/ */
__I uint32_t GINTSTS; __I uint32_t GINTSTS;
uint32_t RESERVE0[1]; uint32_t RESERVE0[1];

2
targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c
View File

@ -204,7 +204,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {

2
targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c
View File

@ -187,7 +187,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {

2
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c
View File

@ -197,7 +197,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {

2
targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c
View File

@ -197,7 +197,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {

30
targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c
View File

@ -172,7 +172,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
#define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_GIANT 0x00000400 /* Giant Frame */
#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
/* ENET Device Revision ID */ /* ENET Device Revision ID */
#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
@ -540,8 +540,8 @@ void ethernet_free() {
// if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
// TxProduceIndex - The buffer that will be / is being fileld by driver, s/w increment // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
// TxConsumeIndex - The buffer that will be / is being sent by hardware // TxConsumeIndex - The buffer that will/is beign sent by hardware
int ethernet_write(const char *data, int slen) { int ethernet_write(const char *data, int slen) {
@ -651,22 +651,22 @@ int ethernet_send() {
#endif #endif
} }
// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
// //
// if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
// Receives an arrived ethernet packet. // Recevies an arrived ethernet packet.
// Receiving an ethernet packet will drop the last received ethernet packet // Receiving an ethernet packet will drop the last received ethernet packet
// and make a new ethernet packet ready to read. // and make a new ethernet packet ready to read.
// Returns size of packet, else 0 if nothing to receive // Returns size of packet, else 0 if nothing to receive
// We read from RxConsumeIndex from position rx_consume_offset // We read from RxConsumeIndex from position rx_consume_offset
// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
// rx_consume_offset = -1 // no frame // rx_consume_offset = -1 // no frame
// rx_consume_offset = 0 // start of frame // rx_consume_offset = 0 // start of frame
// Assumption: A fragment should always be a whole frame // Assumption: A fragment should alway be a whole frame
int ethernet_receive() { int ethernet_receive() {
#if NEW_LOGIC #if NEW_LOGIC
@ -722,11 +722,11 @@ int ethernet_receive() {
#endif #endif
} }
// Read from an received ethernet packet. // Read from an recevied ethernet packet.
// After receive returned a number bigger than 0 it is // After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet. // possible to read bytes from this packet.
// Read will write up to size bytes into data. // Read will write up to size bytes into data.
// It is possible to use read multiple times. // It is possible to use read multible times.
// Each time read will start reading after the last read byte before. // Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen) { int ethernet_read(char *data, int dlen) {

2
targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c
View File

@ -204,7 +204,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {

34
targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c
View File

@ -100,7 +100,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Pressure / No Backoff */ #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
/* Back-to-Back Inter-Packet-Gap Register */ /* Back-to-Back Inter-Packet-Gap Register */
@ -166,13 +166,13 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define TSV0_CRC_ERR 0x00000001 /* CRC error */ #define TSV0_CRC_ERR 0x00000001 /* CRC error */
#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
#define TSV0_DONE 0x00000008 /* Transmission Completed */ #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
#define TSV0_MCAST 0x00000010 /* Multicast Destination */ #define TSV0_MCAST 0x00000010 /* Multicast Destination */
#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
#define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_GIANT 0x00000400 /* Giant Frame */
#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
/* ENET Device Revision ID */ /* ENET Device Revision ID */
#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
@ -565,8 +565,8 @@ void ethernet_free() {
// if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
// TxProduceIndex - The buffer that will be / is being filled by driver, s/w increment // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
// TxConsumeIndex - The buffer that will be / is being sent by hardware // TxConsumeIndex - The buffer that will/is beign sent by hardware
int ethernet_write(const char *data, int slen) { int ethernet_write(const char *data, int slen) {
@ -676,22 +676,22 @@ int ethernet_send() {
#endif #endif
} }
// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
// //
// if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
// Receives an arrived ethernet packet. // Recevies an arrived ethernet packet.
// Receiving an ethernet packet will drop the last received ethernet packet // Receiving an ethernet packet will drop the last received ethernet packet
// and make a new ethernet packet ready to read. // and make a new ethernet packet ready to read.
// Returns size of packet, else 0 if nothing to receive // Returns size of packet, else 0 if nothing to receive
// We read from RxConsumeIndex from position rx_consume_offset // We read from RxConsumeIndex from position rx_consume_offset
// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
// rx_consume_offset = -1 // no frame // rx_consume_offset = -1 // no frame
// rx_consume_offset = 0 // start of frame // rx_consume_offset = 0 // start of frame
// Assumption: A fragment should always be a whole frame // Assumption: A fragment should alway be a whole frame
int ethernet_receive() { int ethernet_receive() {
#if NEW_LOGIC #if NEW_LOGIC
@ -747,11 +747,11 @@ int ethernet_receive() {
#endif #endif
} }
// Read from an received ethernet packet. // Read from an recevied ethernet packet.
// After receive returned a number bigger than 0 it is // After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet. // possible to read bytes from this packet.
// Read will write up to size bytes into data. // Read will write up to size bytes into data.
// It is possible to use read multiple times. // It is possible to use read multible times.
// Each time read will start reading after the last read byte before. // Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen) { int ethernet_read(char *data, int dlen) {

2
targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c
View File

@ -224,7 +224,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status; int count, status;

30
targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c
View File

@ -172,7 +172,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
#define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_GIANT 0x00000400 /* Giant Frame */
#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
//#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
/* ENET Device Revision ID */ /* ENET Device Revision ID */
#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
@ -565,8 +565,8 @@ void ethernet_free() {
// if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
// TxProduceIndex - The buffer that will be / is being fileld by driver, s/w increment // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
// TxConsumeIndex - The buffer that will be / is being sent by hardware // TxConsumeIndex - The buffer that will/is beign sent by hardware
int ethernet_write(const char *data, int slen) { int ethernet_write(const char *data, int slen) {
@ -676,22 +676,22 @@ int ethernet_send() {
#endif #endif
} }
// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
// //
// if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
// Receives an arrived ethernet packet. // Recevies an arrived ethernet packet.
// Receiving an ethernet packet will drop the last received ethernet packet // Receiving an ethernet packet will drop the last received ethernet packet
// and make a new ethernet packet ready to read. // and make a new ethernet packet ready to read.
// Returns size of packet, else 0 if nothing to receive // Returns size of packet, else 0 if nothing to receive
// We read from RxConsumeIndex from position rx_consume_offset // We read from RxConsumeIndex from position rx_consume_offset
// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
// rx_consume_offset = -1 // no frame // rx_consume_offset = -1 // no frame
// rx_consume_offset = 0 // start of frame // rx_consume_offset = 0 // start of frame
// Assumption: A fragment should always be a whole frame // Assumption: A fragment should alway be a whole frame
int ethernet_receive() { int ethernet_receive() {
#if NEW_LOGIC #if NEW_LOGIC
@ -747,11 +747,11 @@ int ethernet_receive() {
#endif #endif
} }
// Read from an received ethernet packet. // Read from an recevied ethernet packet.
// After receive returned a number bigger than 0 it is // After receive returnd a number bigger than 0 it is
// possible to read bytes from this packet. // possible to read bytes from this packet.
// Read will write up to size bytes into data. // Read will write up to size bytes into data.
// It is possible to use read multiple times. // It is possible to use read multible times.
// Each time read will start reading after the last read byte before. // Each time read will start reading after the last read byte before.
int ethernet_read(char *data, int dlen) { int ethernet_read(char *data, int dlen) {

2
targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c
View File

@ -210,7 +210,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
// 2) on error, we use the standard error mechanisms to report/debug // 2) on error, we use the standard error mechanisms to report/debug
// //
// Therefore an I2C transaction should always complete. If it doesn't it is usually // Therefore an I2C transaction should always complete. If it doesn't it is usually
// because something is setup wrong (e.g. wiring), and we don't need to programmatically // because something is setup wrong (e.g. wiring), and we don't need to programatically
// check for that // check for that
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count, status; int count, status;

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