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a few grammar corrections

pull/6149/head
Brendan McDonnell 2018-02-20 20:33:53 -05:00
parent c4f10aafee
commit 085c045fda
11 changed files with 51 additions and 51 deletions
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4
features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h
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@ -122,7 +122,7 @@ struct fnet_dns_params
fnet_address_family_t addr_family; /**< @brief Family of the IP Address which is queried.*/
fnet_dns_callback_resolved_t callback; /**< @brief Pointer to the callback function defined by
* @ref fnet_dns_callback_resolved_t. It is called when the
* DNS-client resolving is finished or an error is occurred. */
* DNS-client resolving is finished or an error has occurred. */
fnet_uint32_t cookie; /**< @brief Optional application-specific parameter. @n
* It's passed to the @c callback
* function as input parameter. */
@ -155,7 +155,7 @@ extern "C" {
* The resolved IP-address will be passed to the @ref fnet_dns_callback_resolved_t callback function,
* which is set in @c params. @n
* The DNS service is released automatically as soon as the
* resolving is finished or an error is occurred.
* resolving is finished or an error has occurred.
*
******************************************************************************/
fnet_return_t fnet_dns_init( struct fnet_dns_params *params );

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h
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@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
*
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
* @ref _flexcan_error_flags enumerations.
*/
enum _flexcan_flags

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h
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@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
*
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
* @ref _flexcan_error_flags enumerations.
*/
enum _flexcan_flags

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h
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@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable
*
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
* @ref _flexcan_error_flags enumerations.
*/
enum _flexcan_flags

40
targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
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@ -3469,7 +3469,7 @@ typedef struct {
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
* | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
* | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.
* | | |The flag is set if any wake-up source has occurred. Refer Power Modes and Wake-up Sources chapter.
* | | |Note1: Write 1 to clear the bit to 0.
* | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
* |[7] |PDEN |System Power-down Enable (Write Protect)
@ -25914,7 +25914,7 @@ typedef struct {
* | | |0 = DMA Disabled.
* | | |1 = DMA Enabled.
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |Note: If target abort is occurred, DMAEN will be cleared.
* | | |Note: If target abort has occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers
@ -26006,7 +26006,7 @@ typedef struct {
* | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
* | | |When Target Abort is occurred, please reset all engine.
* | | |When Target Abort has occurred, please reset all engine.
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
@ -26119,12 +26119,12 @@ typedef struct {
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
* | | |When CRC error is occurred, software should reset SD engine
* | | |When CRC error has occurred, software should reset SD engine
* | | |Some response (ex
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
* | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error is occurred.
* | | |1 = CRC error is occurred.
* | | |0 = No CRC error has occurred.
* | | |1 = CRC error has occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in
@ -27705,60 +27705,60 @@ typedef struct {
* | | |This bit conveys the interrupt status for USB specific events endpoint
* | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[1] |CEPIF |Control Endpoint Interrupt
* | | |This bit conveys the interrupt status for control endpoint
* | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[2] |EPAIF |Endpoint a Interrupt
* | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[3] |EPBIF |Endpoint B Interrupt
* | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[4] |EPCIF |Endpoint C Interrupt
* | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[5] |EPDIF |Endpoint D Interrupt
* | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[6] |EPEIF |Endpoint E Interrupt
* | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[7] |EPFIF |Endpoint F Interrupt
* | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[8] |EPGIF |Endpoint G Interrupt
* | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[9] |EPHIF |Endpoint H Interrupt
* | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[10] |EPIIF |Endpoint I Interrupt
* | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[11] |EPJIF |Endpoint J Interrupt
* | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[12] |EPKIF |Endpoint K Interrupt
* | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[13] |EPLIF |Endpoint L Interrupt
* | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* @var HSUSBD_T::GINTEN
* Offset: 0x08 Global Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------

6
targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h
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@ -10976,18 +10976,18 @@ typedef struct {
* |[0] |BUS_STS |BUS Interrupt Status
* | | |The BUS event means there is bus suspense or bus resume in the bus.
* | | |This bit is used to indicate that there is one of events in the bus.
* | | |0 = No BUS event is occurred.
* | | |0 = No BUS event has occurred.
* | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0].
* |[1] |USB_STS |USB Interrupt Status
* | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus.
* | | |This bit is used to indicate that there is one of events in the bus.
* | | |0 = No USB event is occurred.
* | | |0 = No USB event has occurred.
* | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7.
* |[2] |FLD_STS |Floating Interrupt Status
* | | |0 = There is not attached event in the USB.
* | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2].
* |[3] |WKEUP_STS |Wake-Up Interrupt Status
* | | |0 = No wake-up event is occurred.
* | | |0 = No wake-up event has occurred.
* | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3].
* |[16] |EPEVT0 |USB Event Status On EP0
* | | |0 = No event occurred in Endpoint 0.

38
targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h
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@ -22305,7 +22305,7 @@ typedef struct {
* | | |0 = DMA Disabled.
* | | |1 = DMA Enabled.
* | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
* | | |Note: If target abort is occurred, DMAEN will be cleared.
* | | |Note: If target abort has occurred, DMAEN will be cleared.
* |[1] |DMARST |Software Engine Reset
* | | |0 = No effect.
* | | |1 = Reset internal state machine and pointers.
@ -22432,7 +22432,7 @@ typedef struct {
* | :----: | :----: | :---- |
* |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation.
* | | |When Target Abort is occurred, please reset all engine.
* | | |When Target Abort has occurred, please reset all engine.
* | | |0 = No bus ERROR response received.
* | | |1 = Bus ERROR response received.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
@ -22583,12 +22583,12 @@ typedef struct {
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
* | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer.
* | | |When CRC error is occurred, software should reset SD engine.
* | | |When CRC error has occurred, software should reset SD engine.
* | | |Some response (ex.
* | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag.
* | | |In this condition, software should ignore CRC error and clears this bit manually.
* | | |0 = No CRC error is occurred.
* | | |1 = CRC error is occurred.
* | | |0 = No CRC error has occurred.
* | | |1 = CRC error has occurred.
* | | |Note: This bit is read only, but can be cleared by writing '1' to it.
* |[2] |CRC7 |CRC7 Check Status (Read Only)
* | | |SD host will check CRC7 correctness during each response in.
@ -27165,60 +27165,60 @@ typedef struct {
* | | |This bit conveys the interrupt status for USB specific events endpoint.
* | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[1] |CEPIF |Control Endpoint Interrupt
* | | |This bit conveys the interrupt status for control endpoint.
* | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[2] |EPAIF |Endpoints A Interrupt
* | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[3] |EPBIF |Endpoints B Interrupt
* | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[4] |EPCIF |Endpoints C Interrupt
* | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[5] |EPDIF |Endpoints D Interrupt
* | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[6] |EPEIF |Endpoints E Interrupt
* | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[7] |EPFIF |Endpoints F Interrupt
* | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[8] |EPGIF |Endpoints G Interrupt
* | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[9] |EPHIF |Endpoints H Interrupt
* | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[10] |EPIIF |Endpoints I Interrupt
* | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[11] |EPJIF |Endpoints J Interrupt
* | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[12] |EPKIF |Endpoints K Interrupt
* | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
* |[13] |EPLIF |Endpoints L Interrupt
* | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
* | | |0 = No interrupt event occurred.
* | | |1 = The related interrupt event is occurred.
* | | |1 = The related interrupt event has occurred.
*/
__I uint32_t GINTSTS;
uint32_t RESERVE0[1];

2
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h
View File

@ -75,7 +75,7 @@ enum _mcan_status
*
* This provides constants for the MCAN status flags for use in the MCAN functions.
* Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to
* read MCAN_ErrorFlag and distinguish which error is occur using
* read MCAN_ErrorFlag and distinguish which error has occurred using
* @ref _mcan_error_flags enumerations.
*/
enum _mcan_flags

2
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h
View File

@ -240,7 +240,7 @@ enum _flexcan_interrupt_enable
*
* This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
* Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to
* read FlEXCAN_ErrorFlag and distinguish which error is occur using
* read FlEXCAN_ErrorFlag and distinguish which error has occurred using
* @ref _flexcan_error_flags enumerations.
*/
enum _flexcan_flags

2
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h
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@ -59,7 +59,7 @@ extern "C" {
uint32_t TIDLE; /*!< The status of TXDx pin after output of the
last bit */
uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error
is occurred in SCLK input mode */
has occurred in SCLK input mode */
uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK
input mode */
uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which

2
targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c
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@ -1121,7 +1121,7 @@ void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitSt
tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK);
tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE);
/* Set status of TXDx pin when an under run error is occurred
/* Set status of TXDx pin when an under run error has occurred
and The last bit hold time of TXDx pin in SCLK input mode */
if (IOClkSel == SIO_CLK_SCLKINPUT) {
tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK);