2017-11-23 01:12:13 +00:00
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/* mbed Microcontroller Library
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2018-08-21 08:05:08 +00:00
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* Copyright (c) 2006-2018 ARM Limited
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2017-11-23 01:12:13 +00:00
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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2017-11-27 22:52:32 +00:00
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2017-11-23 01:12:13 +00:00
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#include "drivers/QSPI.h"
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#include "platform/mbed_critical.h"
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2018-02-16 14:19:51 +00:00
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#include <string.h>
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2017-11-23 01:12:13 +00:00
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#if DEVICE_QSPI
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2017-11-27 22:52:32 +00:00
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2017-11-23 01:12:13 +00:00
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namespace mbed {
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2018-08-21 08:39:05 +00:00
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QSPI *QSPI::_owner = NULL;
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2017-12-05 14:21:22 +00:00
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SingletonPtr<PlatformMutex> QSPI::_mutex;
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2017-12-06 13:15:24 +00:00
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2018-08-21 08:39:05 +00:00
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QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
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2017-12-01 20:32:42 +00:00
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{
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2017-11-23 01:12:13 +00:00
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_qspi_io0 = io0;
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_qspi_io1 = io1;
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_qspi_io2 = io2;
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_qspi_io3 = io3;
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_qspi_clk = sclk;
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2017-11-27 22:52:32 +00:00
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_qspi_cs = ssel;
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_inst_width = QSPI_CFG_BUS_SINGLE;
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_address_width = QSPI_CFG_BUS_SINGLE;
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_address_size = QSPI_CFG_ADDR_SIZE_24;
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_alt_width = QSPI_CFG_BUS_SINGLE;
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2017-11-23 09:24:31 +00:00
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_alt_size = QSPI_CFG_ALT_SIZE_8;
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2017-11-27 22:52:32 +00:00
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_data_width = QSPI_CFG_BUS_SINGLE;
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2018-03-30 12:55:33 +00:00
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_num_dummy_cycles = 0;
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2018-03-30 09:50:11 +00:00
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_mode = mode;
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2017-12-01 20:32:42 +00:00
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_hz = ONE_MHZ;
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_initialized = false;
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2017-12-05 14:21:22 +00:00
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2017-12-01 20:32:42 +00:00
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//Go ahead init the device here with the default config
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2018-08-21 08:05:08 +00:00
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bool success = _initialize();
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MBED_ASSERT(success);
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2017-11-23 01:12:13 +00:00
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}
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2017-12-05 14:21:22 +00:00
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2018-03-30 09:50:11 +00:00
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qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
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2017-12-06 13:15:24 +00:00
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{
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qspi_status_t ret_status = QSPI_STATUS_OK;
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2017-12-05 14:21:22 +00:00
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2017-11-23 01:12:13 +00:00
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lock();
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2017-11-30 17:46:25 +00:00
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_inst_width = inst_width;
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_address_width = address_width;
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_address_size = address_size;
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_alt_width = alt_width;
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_alt_size = alt_size;
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2017-12-05 14:21:22 +00:00
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_data_width = data_width;
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2018-03-30 12:55:33 +00:00
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_num_dummy_cycles = dummy_cycles;
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2017-12-05 14:21:22 +00:00
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2017-11-23 01:12:13 +00:00
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unlock();
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2017-12-05 14:21:22 +00:00
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2017-12-01 20:32:42 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-08-21 08:39:05 +00:00
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qspi_status_t QSPI::set_frequency(int hz)
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2017-12-01 20:32:42 +00:00
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{
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2017-12-05 14:21:22 +00:00
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qspi_status_t ret_status = QSPI_STATUS_OK;
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2017-12-06 13:15:24 +00:00
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if (_initialized) {
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2017-12-01 20:32:42 +00:00
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lock();
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_hz = hz;
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//If the same owner, just change freq.
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//Otherwise we may have to change mode as well, so call _acquire
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if (_owner == this) {
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK != qspi_frequency(&_qspi, _hz)) {
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2017-12-01 20:32:42 +00:00
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ret_status = QSPI_STATUS_ERROR;
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}
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} else {
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_acquire();
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2017-11-27 22:52:32 +00:00
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}
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2017-12-01 20:32:42 +00:00
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unlock();
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2017-11-23 01:12:13 +00:00
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} else {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_ERROR;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-05 14:21:22 +00:00
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2017-11-27 22:52:32 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-09-05 11:59:03 +00:00
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qspi_status_t QSPI::read(int address, char *rx_buffer, size_t *rx_length)
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2017-12-01 20:32:42 +00:00
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{
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2017-12-05 14:21:22 +00:00
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qspi_status_t ret_status = QSPI_STATUS_ERROR;
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2017-12-06 13:15:24 +00:00
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if (_initialized) {
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if ((rx_length != NULL) && (rx_buffer != NULL)) {
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if (*rx_length != 0) {
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2017-12-01 20:32:42 +00:00
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lock();
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2017-12-06 13:15:24 +00:00
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if (true == _acquire()) {
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2018-03-30 12:55:33 +00:00
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_build_qspi_command(-1, address, -1);
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_OK;
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2017-12-01 20:32:42 +00:00
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}
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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unlock();
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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} else {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_INVALID_PARAMETER;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-04 19:06:39 +00:00
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}
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2017-12-05 14:21:22 +00:00
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2017-11-27 22:52:32 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-09-05 11:59:03 +00:00
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qspi_status_t QSPI::write(int address, const char *tx_buffer, size_t *tx_length)
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2017-12-01 20:32:42 +00:00
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{
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2017-12-05 14:21:22 +00:00
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qspi_status_t ret_status = QSPI_STATUS_ERROR;
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2018-08-21 08:39:05 +00:00
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2017-12-06 13:15:24 +00:00
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if (_initialized) {
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if ((tx_length != NULL) && (tx_buffer != NULL)) {
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if (*tx_length != 0) {
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2017-12-01 20:32:42 +00:00
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lock();
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2017-12-06 13:15:24 +00:00
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if (true == _acquire()) {
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2018-03-30 12:55:33 +00:00
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_build_qspi_command(-1, address, -1);
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK == qspi_write(&_qspi, &_qspi_command, tx_buffer, tx_length)) {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_OK;
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2017-12-01 20:32:42 +00:00
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}
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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unlock();
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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} else {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_INVALID_PARAMETER;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-04 19:06:39 +00:00
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}
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2017-12-05 14:21:22 +00:00
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2017-11-27 22:52:32 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-09-05 11:59:03 +00:00
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qspi_status_t QSPI::read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length)
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2017-12-01 20:32:42 +00:00
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{
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2017-12-05 14:21:22 +00:00
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qspi_status_t ret_status = QSPI_STATUS_ERROR;
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2017-12-06 13:15:24 +00:00
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if (_initialized) {
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2018-08-21 08:39:05 +00:00
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if ((rx_length != NULL) && (rx_buffer != NULL)) {
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2017-12-06 13:15:24 +00:00
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if (*rx_length != 0) {
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2017-12-01 20:32:42 +00:00
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lock();
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2018-08-21 08:39:05 +00:00
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if (true == _acquire()) {
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2018-03-30 12:55:33 +00:00
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_build_qspi_command(instruction, address, alt);
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_OK;
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2017-12-01 20:32:42 +00:00
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}
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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unlock();
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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} else {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_INVALID_PARAMETER;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-04 19:06:39 +00:00
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}
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2018-08-21 08:39:05 +00:00
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2017-11-27 22:52:32 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-09-05 11:59:03 +00:00
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qspi_status_t QSPI::write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length)
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2017-12-01 20:32:42 +00:00
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{
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2017-12-05 14:21:22 +00:00
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qspi_status_t ret_status = QSPI_STATUS_ERROR;
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2018-08-21 08:39:05 +00:00
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2017-12-06 13:15:24 +00:00
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if (_initialized) {
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2018-08-21 08:39:05 +00:00
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if ((tx_length != NULL) && (tx_buffer != NULL)) {
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2017-12-06 13:15:24 +00:00
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if (*tx_length != 0) {
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2017-12-01 20:32:42 +00:00
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lock();
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2017-12-06 13:15:24 +00:00
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if (true == _acquire()) {
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2018-03-30 12:55:33 +00:00
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_build_qspi_command(instruction, address, alt);
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK == qspi_write(&_qspi, &_qspi_command, tx_buffer, tx_length)) {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_OK;
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2017-12-01 20:32:42 +00:00
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}
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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unlock();
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2017-11-23 01:12:13 +00:00
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}
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2017-12-01 20:32:42 +00:00
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} else {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_INVALID_PARAMETER;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-04 19:06:39 +00:00
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}
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2018-08-21 08:39:05 +00:00
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2017-11-27 22:52:32 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-09-05 11:59:03 +00:00
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qspi_status_t QSPI::command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
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2017-12-01 20:32:42 +00:00
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{
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2017-12-05 14:21:22 +00:00
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qspi_status_t ret_status = QSPI_STATUS_ERROR;
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2018-08-21 08:39:05 +00:00
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2017-12-06 13:15:24 +00:00
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if (_initialized) {
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2017-12-01 20:32:42 +00:00
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lock();
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2017-12-06 13:15:24 +00:00
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if (true == _acquire()) {
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2018-03-30 12:55:33 +00:00
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_build_qspi_command(instruction, address, -1); //We just need the command
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK == qspi_command_transfer(&_qspi, &_qspi_command, (const void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length)) {
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2017-12-05 14:21:22 +00:00
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ret_status = QSPI_STATUS_OK;
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2017-12-01 20:32:42 +00:00
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}
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2018-08-21 08:39:05 +00:00
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}
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2017-12-01 20:32:42 +00:00
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unlock();
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2017-12-04 19:06:39 +00:00
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}
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2018-08-21 08:39:05 +00:00
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2017-11-27 22:52:32 +00:00
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return ret_status;
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2017-11-23 01:12:13 +00:00
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}
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2018-08-21 08:39:05 +00:00
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void QSPI::lock()
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2017-12-01 20:32:42 +00:00
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{
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2017-11-23 01:12:13 +00:00
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_mutex->lock();
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}
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2018-08-21 08:39:05 +00:00
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void QSPI::unlock()
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2017-12-01 20:32:42 +00:00
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{
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2017-11-23 01:12:13 +00:00
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_mutex->unlock();
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}
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2017-12-01 20:32:42 +00:00
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// Note: Private helper function to initialize qspi HAL
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2018-08-21 08:39:05 +00:00
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bool QSPI::_initialize()
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2017-12-01 20:32:42 +00:00
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{
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2018-08-21 08:05:08 +00:00
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if (_mode != 0 && _mode != 1) {
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_initialized = false;
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return _initialized;
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}
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2018-03-30 09:50:11 +00:00
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2018-08-21 08:39:05 +00:00
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qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode);
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2017-12-06 13:15:24 +00:00
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if (QSPI_STATUS_OK == ret) {
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2017-12-01 20:32:42 +00:00
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_initialized = true;
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} else {
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_initialized = false;
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}
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2018-08-21 08:39:05 +00:00
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2017-12-01 20:32:42 +00:00
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return _initialized;
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}
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// Note: Private function with no locking
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2018-08-21 08:39:05 +00:00
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bool QSPI::_acquire()
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2017-12-01 20:32:42 +00:00
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{
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2017-11-23 01:12:13 +00:00
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if (_owner != this) {
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//This will set freq as well
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2017-12-01 20:32:42 +00:00
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_initialize();
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2017-11-23 01:12:13 +00:00
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_owner = this;
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}
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2018-08-21 08:39:05 +00:00
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2017-12-01 20:32:42 +00:00
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return _initialized;
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2017-11-23 01:12:13 +00:00
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}
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2018-08-21 08:39:05 +00:00
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void QSPI::_build_qspi_command(int instruction, int address, int alt)
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2017-12-01 20:32:42 +00:00
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{
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2018-08-21 08:39:05 +00:00
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memset(&_qspi_command, 0, sizeof(qspi_command_t));
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2017-11-23 01:12:13 +00:00
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//Set up instruction phase parameters
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2017-12-05 14:21:22 +00:00
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_qspi_command.instruction.bus_width = _inst_width;
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2017-12-06 13:15:24 +00:00
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if (instruction != -1) {
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2017-12-05 14:21:22 +00:00
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_qspi_command.instruction.value = instruction;
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2017-11-23 09:24:31 +00:00
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_qspi_command.instruction.disabled = false;
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2017-11-23 01:12:13 +00:00
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} else {
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2017-11-23 09:24:31 +00:00
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_qspi_command.instruction.disabled = true;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-05 14:21:22 +00:00
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2017-11-23 01:12:13 +00:00
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//Set up address phase parameters
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_qspi_command.address.bus_width = _address_width;
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_qspi_command.address.size = _address_size;
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2017-12-06 13:15:24 +00:00
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if (address != -1) {
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2017-12-05 14:21:22 +00:00
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_qspi_command.address.value = address;
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2017-11-23 09:24:31 +00:00
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_qspi_command.address.disabled = false;
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2017-11-23 01:12:13 +00:00
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} else {
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2017-11-23 09:24:31 +00:00
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_qspi_command.address.disabled = true;
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2017-11-23 01:12:13 +00:00
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}
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2017-12-05 14:21:22 +00:00
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2017-11-23 01:12:13 +00:00
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//Set up alt phase parameters
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2017-12-05 14:21:22 +00:00
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_qspi_command.alt.bus_width = _alt_width;
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2017-11-23 01:12:13 +00:00
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_qspi_command.alt.size = _alt_size;
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2017-12-06 13:15:24 +00:00
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if (alt != -1) {
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2018-08-21 08:39:05 +00:00
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_qspi_command.alt.value = alt;
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2017-11-23 09:24:31 +00:00
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_qspi_command.alt.disabled = false;
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2017-11-23 01:12:13 +00:00
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} else {
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2017-11-23 09:24:31 +00:00
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_qspi_command.alt.disabled = true;
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2017-11-23 01:12:13 +00:00
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}
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2018-03-20 17:50:43 +00:00
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2018-03-30 12:55:33 +00:00
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_qspi_command.dummy_count = _num_dummy_cycles;
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2017-12-05 14:21:22 +00:00
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2017-11-23 01:12:13 +00:00
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//Set up bus width for data phase
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_qspi_command.data.bus_width = _data_width;
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}
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} // namespace mbed
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#endif
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