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astyle fixes on QSPI API/driver/tests

pull/7783/head
Maciej Bocianski 2018-08-21 10:39:05 +02:00
parent ad49388888
commit 883ea2f1d1
6 changed files with 72 additions and 74 deletions
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27
TESTS/mbed_hal/qspi/main.cpp
View File

@ -99,12 +99,11 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
int erase_time = 0, write_time = 0, read_time = 0;
size_t buf_len = data_size;
for (uint32_t tc = 0; tc < test_count; tc++)
{
for (uint32_t tc = 0; tc < test_count; tc++) {
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
srand (ticker_read(get_us_ticker_data()));
for(uint32_t i = 0; i < data_size; i++) {
srand(ticker_read(get_us_ticker_data()));
for (uint32_t i = 0; i < data_size; i++) {
tx_buf[i] = (uint8_t)(rand() & 0xFF);
}
@ -127,8 +126,7 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
}
const uint32_t write_size = data_size / write_count;
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size)
{
for (uint32_t wc = 0, write_start = flash_addr; wc < write_count; wc++, write_start += write_size) {
ret = write_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
@ -157,8 +155,7 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width,
memset(rx_buf, 0, sizeof(rx_buf));
const uint32_t read_size = data_size / read_count;
qspi.cmd.configure(read_inst_width, read_addr_width, read_data_width, read_alt_width, read_addr_size, read_alt_size, read_dummy_cycles);
for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size)
{
for (uint32_t rc = 0, read_start = flash_addr; rc < read_count; rc++, read_start += read_size) {
timer.reset();
timer.start();
@ -226,14 +223,14 @@ void qspi_write_read_test(void)
flash_init(qspi);
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = dual_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = quad_enable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
@ -270,14 +267,14 @@ void qspi_write_read_test(void)
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = dual_disable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
}
if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) ||
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) {
ret = quad_disable(qspi);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
WAIT_FOR(WRSR_MAX_TIME, qspi);
@ -352,21 +349,21 @@ void qspi_frequency_test(void)
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/2);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 2);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/4);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 4);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);
flash_init(qspi);
_qspi_write_read_test(qspi, WRITE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, WRITE_SINGLE, READ_1_1_1, ADDR_SIZE_24, ALT_SIZE_8, QSPI_NONE, READ_SINGLE, TEST_REPEAT_SINGLE, DATA_SIZE_256, TEST_FLASH_ADDRESS);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY/8);
ret = qspi_frequency(&qspi.handle, QSPI_COMMON_MAX_FREQUENCY / 8);
TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret);
// check if the memory is working properly
qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8);

6
TESTS/mbed_hal/qspi/qspi_test_utils.cpp
View File

@ -32,7 +32,7 @@ void QspiCommand::configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_w
qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
int dummy_cycles)
{
memset(&_cmd, 0, sizeof(qspi_command_t) );
memset(&_cmd, 0, sizeof(qspi_command_t));
_cmd.instruction.disabled = _cmd.address.disabled = _cmd.alt.disabled = true;
_cmd.instruction.bus_width = inst_width;
@ -62,7 +62,7 @@ void QspiCommand::build(int instruction, int address, int alt)
}
}
qspi_command_t* QspiCommand::get()
qspi_command_t *QspiCommand::get()
{
return &_cmd;
}
@ -175,7 +175,7 @@ void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str)
for (uint32_t j = 0; j < reg_size; j++) {
utest_printf("%s byte %u (MSB first): ", str != NULL ? str : "", j);
for(int i = 0; i < 8; i++) {
for (int i = 0; i < 8; i++) {
utest_printf("%s ", ((reg[j] & (1 << (7 - i))) & 0xFF) == 0 ? "0" : "1");
}
utest_printf("\r\n");

2
TESTS/mbed_hal/qspi/qspi_test_utils.h
View File

@ -36,7 +36,7 @@ public:
void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
qspi_command_t * get();
qspi_command_t *get();
private:
qspi_command_t _cmd;

56
drivers/QSPI.cpp
View File

@ -22,10 +22,10 @@
namespace mbed {
QSPI* QSPI::_owner = NULL;
QSPI *QSPI::_owner = NULL;
SingletonPtr<PlatformMutex> QSPI::_mutex;
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
{
_qspi_io0 = io0;
_qspi_io1 = io1;
@ -67,7 +67,7 @@ qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width
return ret_status;
}
qspi_status_t QSPI::set_frequency(int hz)
qspi_status_t QSPI::set_frequency(int hz)
{
qspi_status_t ret_status = QSPI_STATUS_OK;
@ -91,7 +91,7 @@ qspi_status_t QSPI::set_frequency(int hz)
return ret_status;
}
qspi_status_t QSPI::read(unsigned int address, char *rx_buffer, size_t *rx_length)
qspi_status_t QSPI::read(unsigned int address, char *rx_buffer, size_t *rx_length)
{
qspi_status_t ret_status = QSPI_STATUS_ERROR;
@ -115,10 +115,10 @@ qspi_status_t QSPI::read(unsigned int address, char *rx_buffer, size_t *rx_lengt
return ret_status;
}
qspi_status_t QSPI::write(unsigned int address, const char *tx_buffer, size_t *tx_length)
qspi_status_t QSPI::write(unsigned int address, const char *tx_buffer, size_t *tx_length)
{
qspi_status_t ret_status = QSPI_STATUS_ERROR;
if (_initialized) {
if ((tx_length != NULL) && (tx_buffer != NULL)) {
if (*tx_length != 0) {
@ -139,15 +139,15 @@ qspi_status_t QSPI::write(unsigned int address, const char *tx_buffer, size_t *t
return ret_status;
}
qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned int address, char *rx_buffer, size_t *rx_length)
qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned int address, char *rx_buffer, size_t *rx_length)
{
qspi_status_t ret_status = QSPI_STATUS_ERROR;
if (_initialized) {
if ( (rx_length != NULL) && (rx_buffer != NULL) ) {
if ((rx_length != NULL) && (rx_buffer != NULL)) {
if (*rx_length != 0) {
lock();
if ( true == _acquire()) {
if (true == _acquire()) {
_build_qspi_command(instruction, address, alt);
if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
ret_status = QSPI_STATUS_OK;
@ -159,16 +159,16 @@ qspi_status_t QSPI::read(unsigned int instruction, unsigned int alt, unsigned in
ret_status = QSPI_STATUS_INVALID_PARAMETER;
}
}
return ret_status;
}
qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned int address, const char *tx_buffer, size_t *tx_length)
qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned int address, const char *tx_buffer, size_t *tx_length)
{
qspi_status_t ret_status = QSPI_STATUS_ERROR;
if (_initialized) {
if ( (tx_length != NULL) && (tx_buffer != NULL) ) {
if ((tx_length != NULL) && (tx_buffer != NULL)) {
if (*tx_length != 0) {
lock();
if (true == _acquire()) {
@ -183,14 +183,14 @@ qspi_status_t QSPI::write(unsigned int instruction, unsigned int alt, unsigned i
ret_status = QSPI_STATUS_INVALID_PARAMETER;
}
}
return ret_status;
}
qspi_status_t QSPI::command_transfer(unsigned int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
qspi_status_t QSPI::command_transfer(unsigned int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
{
qspi_status_t ret_status = QSPI_STATUS_ERROR;
if (_initialized) {
lock();
if (true == _acquire()) {
@ -198,56 +198,56 @@ qspi_status_t QSPI::command_transfer(unsigned int instruction, int address, cons
if (QSPI_STATUS_OK == qspi_command_transfer(&_qspi, &_qspi_command, (const void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length)) {
ret_status = QSPI_STATUS_OK;
}
}
}
unlock();
}
return ret_status;
}
void QSPI::lock()
void QSPI::lock()
{
_mutex->lock();
}
void QSPI::unlock()
void QSPI::unlock()
{
_mutex->unlock();
}
// Note: Private helper function to initialize qspi HAL
bool QSPI::_initialize()
bool QSPI::_initialize()
{
if (_mode != 0 && _mode != 1) {
_initialized = false;
return _initialized;
}
qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode );
qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode);
if (QSPI_STATUS_OK == ret) {
_initialized = true;
} else {
_initialized = false;
}
return _initialized;
}
// Note: Private function with no locking
bool QSPI::_acquire()
bool QSPI::_acquire()
{
if (_owner != this) {
//This will set freq as well
_initialize();
_owner = this;
}
return _initialized;
}
void QSPI::_build_qspi_command(int instruction, int address, int alt)
void QSPI::_build_qspi_command(int instruction, int address, int alt)
{
memset( &_qspi_command, 0, sizeof(qspi_command_t) );
memset(&_qspi_command, 0, sizeof(qspi_command_t));
//Set up instruction phase parameters
_qspi_command.instruction.bus_width = _inst_width;
if (instruction != -1) {
@ -271,7 +271,7 @@ void QSPI::_build_qspi_command(int instruction, int address, int alt)
_qspi_command.alt.bus_width = _alt_width;
_qspi_command.alt.size = _alt_size;
if (alt != -1) {
_qspi_command.alt.value = alt;
_qspi_command.alt.value = alt;
_qspi_command.alt.disabled = false;
} else {
_qspi_command.alt.disabled = true;

45
drivers/QSPI.h
View File

@ -28,13 +28,13 @@
#define ONE_MHZ 1000000
namespace mbed {
/** \addtogroup drivers */
/** A QSPI Driver, used for communicating with QSPI slave devices
*
* The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
* Most QSPI devices will also require Chip Select which is indicated by ssel.
* Most QSPI devices will also require Chip Select which is indicated by ssel.
*
* @note Synchronization level: Thread safe
*
@ -49,10 +49,10 @@ namespace mbed {
*
*
* int main() {
* char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
* char rx_buf[4];
* int buf_len = sizeof(tx_buf);
*
* char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
* char rx_buf[4];
* int buf_len = sizeof(tx_buf);
*
* int result = qspi_device.write( 0x12 , 0x100000 , 0 , tx_buf, &buf_len );
* if( !result ) printf("Write failed");
* int result = qspi_device.read( 0x13 , 0x100000 , 0 , rx_buf, &buf_len );
@ -80,7 +80,7 @@ public:
* default value = 0
*
*/
QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel=NC, int mode=0);
QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
/** Configure the data transmission format
*
@ -93,13 +93,13 @@ public:
* @param dummy_cycles Number of dummy clock cycles to be used after alt phase
*
*/
qspi_status_t configure_format(qspi_bus_width_t inst_width,
qspi_bus_width_t address_width,
qspi_address_size_t address_size,
qspi_bus_width_t alt_width,
qspi_alt_size_t alt_size,
qspi_bus_width_t data_width,
int dummy_cycles);
qspi_status_t configure_format(qspi_bus_width_t inst_width,
qspi_bus_width_t address_width,
qspi_address_size_t address_size,
qspi_bus_width_t alt_width,
qspi_alt_size_t alt_size,
qspi_bus_width_t data_width,
int dummy_cycles);
/** Set the qspi bus clock frequency
*
@ -112,7 +112,7 @@ public:
/** Read from QSPI peripheral with the preset read_instruction and alt_value
*
* @param address Address to be accessed in QSPI peripheral
* @param rx_buffer Buffer for data to be read from the peripheral
* @param rx_buffer Buffer for data to be read from the peripheral
* @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
*
* @returns
@ -123,7 +123,7 @@ public:
/** Write to QSPI peripheral using custom write instruction
*
* @param address Address to be accessed in QSPI peripheral
* @param tx_buffer Buffer containing data to be sent to peripheral
* @param tx_buffer Buffer containing data to be sent to peripheral
* @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
*
* @returns
@ -136,7 +136,7 @@ public:
* @param instruction Instruction value to be used in instruction phase
* @param alt Alt value to be used in instruction phase
* @param address Address to be accessed in QSPI peripheral
* @param rx_buffer Buffer for data to be read from the peripheral
* @param rx_buffer Buffer for data to be read from the peripheral
* @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
*
* @returns
@ -149,7 +149,7 @@ public:
* @param instruction Instruction value to be used in instruction phase
* @param alt Alt value to be used in instruction phase
* @param address Address to be accessed in QSPI peripheral
* @param tx_buffer Buffer containing data to be sent to peripheral
* @param tx_buffer Buffer containing data to be sent to peripheral
* @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
*
* @returns
@ -161,9 +161,9 @@ public:
*
* @param instruction Instruction value to be used in instruction phase
* @param address Some instruction might require address. Use -1 for ignoring the address value
* @param tx_buffer Buffer containing data to be sent to peripheral
* @param tx_buffer Buffer containing data to be sent to peripheral
* @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
* @param rx_buffer Buffer for data to be read from the peripheral
* @param rx_buffer Buffer for data to be read from the peripheral
* @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
*
* @returns
@ -181,7 +181,8 @@ protected:
virtual void unlock(void);
public:
virtual ~QSPI() {
virtual ~QSPI()
{
}
protected:
@ -210,7 +211,7 @@ private:
bool _acquire(void);
bool _initialize();
/*
/*
* This function builds the qspi command struct to be send to Hal
*/
inline void _build_qspi_command(int instruction, int address, int alt);

10
hal/qspi_api.h
View File

@ -38,8 +38,8 @@ extern "C" {
typedef struct qspi_s qspi_t;
/** QSPI Bus width
*
* Some parts of commands provide variable bus width
*
* Some parts of commands provide variable bus width
*/
typedef enum qspi_bus_width {
QSPI_CFG_BUS_SINGLE,
@ -101,10 +101,10 @@ typedef enum qspi_status {
QSPI_STATUS_OK = 0, /**< Function executed sucessfully >*/
} qspi_status_t;
/** Initialize QSPI peripheral.
/** Initialize QSPI peripheral.
*
* It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode. The clock for the peripheral should be enabled
*
*
* @param obj QSPI object
* @param io0 Data pin 0
* @param io1 Data pin 1
@ -167,7 +167,7 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void
QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
QSPI_STATUS_ERROR otherwise
*/
qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size);
qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size);
/** Receive a command and block of data
*