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mbed-os/TESTS/mbed_hal_fpga_ci_test_shield
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Steven Cooreman f6a70b2028 Increase ADC test tolerance to 5% 
During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Voltage rail differences between target and FPGA
Extension of lesser-resolution ADC's to 16-bit results
 		2019-07-10 14:12:46 +01:00
..
analogin Increase ADC test tolerance to 5% 2019-07-10 14:12:46 +01:00
analogout FPGA test shield: Allow any defined form factor 2019-07-08 09:42:30 +02:00
gpio Merge pull request #10975 from fkjagodzinski/fix-fpga_ci_test_shield-tests 2019-07-08 13:47:55 +01:00
gpio_irq Merge pull request #10975 from fkjagodzinski/fix-fpga_ci_test_shield-tests 2019-07-08 13:47:55 +01:00
i2c FPGA test shield: Allow any defined form factor 2019-07-08 09:42:30 +02:00
pwm FPGA test shield: Allow any defined form factor 2019-07-08 09:42:30 +02:00
spi FPGA SPI test: Fix typo 2019-07-08 15:23:21 +02:00
uart FPGA test shield: Allow any defined form factor 2019-07-08 09:42:30 +02:00