mirror of https://github.com/ARMmbed/mbed-os.git
532 lines
31 KiB
C
532 lines
31 KiB
C
/* MPS2 CMSIS Library
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*
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* Copyright (c) 2006-2018 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __FVP_MPS2_H
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#define __FVP_MPS2_H
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#include "peripherallink.h" /* device specific header file */
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************/
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/* FPGA System Register declaration */
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/******************************************************************************/
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typedef struct
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{
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__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
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// [31:2] : Reserved
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// [1:0] : LEDs
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uint32_t RESERVED1[1];
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__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
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// [31:2] : Reserved
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// [1:0] : Buttons
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uint32_t RESERVED2[1];
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__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
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__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
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__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
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// Increments when 32-bit prescale counter reach zero
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uint32_t RESERVED3[1];
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__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
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// Bit[31:0] : reload value for prescale counter
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__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
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// current value of the pre-scaler counter
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// The Cycle Up Counter increment when the prescale down counter reach 0
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// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
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uint32_t RESERVED4[9];
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__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
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// [31:10] : Reserved
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// [9] : SHIELD_1_SPI_nCS
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// [8] : SHIELD_0_SPI_nCS
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// [7] : ADC_SPI_nCS
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// [6] : CLCD_BL_CTRL
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// [5] : CLCD_RD
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// [4] : CLCD_RS
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// [3] : CLCD_RESET
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// [2] : RESERVED
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// [1] : SPI_nSS
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// [0] : CLCD_CS
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} MPS2_FPGAIO_TypeDef;
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// MISC register bit definitions
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#define CLCD_CS_Pos 0
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#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
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#define SPI_nSS_Pos 1
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#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
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#define CLCD_RESET_Pos 3
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#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
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#define CLCD_RS_Pos 4
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#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
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#define CLCD_RD_Pos 5
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#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
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#define CLCD_BL_Pos 6
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#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
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#define ADC_nCS_Pos 7
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#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
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#define SHIELD_0_nCS_Pos 8
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#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
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#define SHIELD_1_nCS_Pos 9
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#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
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/******************************************************************************/
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/* SCC Register declaration */
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/******************************************************************************/
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typedef struct //
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{
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__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
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// [31:1] : Reserved
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// [0] 1 : REMAP BlockRam to ZBT
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__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
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// [31:8] : Reserved
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// [7:0] : MCC LEDs
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uint32_t RESERVED0[1];
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__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
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// [31:8] : Reserved
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// [7:0] : These bits indicate state of the MCC switches
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__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
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// [31:4] : Reserved
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// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
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uint32_t RESERVED1[35];
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__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
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// [31:0] : Data
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__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
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// [31:0] : Data
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__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
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// [31] : Start (generates interrupt on write to this bit)
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// [30] : R/W access
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// [29:26] : Reserved
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// [25:20] : Function value
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// [19:12] : Reserved
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// [11:0] : Device (value of 0/1/2 for supported clocks)
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__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
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// [31:2] : Reserved
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// [1] : Error
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// [0] : Complete
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__IO uint32_t RESERVED2[20];
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__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
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// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
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// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
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// [15:1] : Reserved
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// [0] : This bit indicates if all enabled DLLs are locked
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uint32_t RESERVED3[957];
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__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
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// [31:24] : FPGA build number
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// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
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// [19:11] : Reserved
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// [10] : if “1” SCC_SW register has been implemented
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// [9] : if “1” SCC_LED register has been implemented
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// [8] : if “1” DLL lock register has been implemented
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// [7:0] : number of SCC configuration register
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__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
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// [31:24] : Implementer ID: 0x41 = ARM
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// [23:20] : Application note IP variant number
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// [19:16] : IP Architecture: 0x4 =AHB
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// [15:4] : Primary part number: 386 = AN386
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// [3:0] : Application note IP revision number
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} MPS2_SCC_TypeDef;
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/******************************************************************************/
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/* SSP Peripheral declaration */
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/******************************************************************************/
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typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
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{
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__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
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// [31:16] : Reserved
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// [15:8] : Serial clock rate
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// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
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// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
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// [5:4] : Frame format
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// [3:0] : Data Size Select
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__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
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// [31:4] : Reserved
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// [3] : Slave-mode output disable
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// [2] : Master or slave mode select
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// [1] : Synchronous serial port enable
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// [0] : Loop back mode
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__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
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// [31:16] : Reserved
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// [15:0] : Transmit/Receive FIFO
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__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
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// [31:5] : Reserved
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// [4] : PrimeCell SSP busy flag
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// [3] : Receive FIFO full
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// [2] : Receive FIFO not empty
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// [1] : Transmit FIFO not full
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// [0] : Transmit FIFO empty
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__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
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// [31:8] : Reserved
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// [8:0] : Clock prescale divisor
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__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
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// [31:4] : Reserved
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// [3] : Transmit FIFO interrupt mask
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// [2] : Receive FIFO interrupt mask
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// [1] : Receive timeout interrupt mask
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// [0] : Receive overrun interrupt mask
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__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
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// [31:4] : Reserved
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// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
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// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
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// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
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// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
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__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
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// [31:4] : Reserved
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// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
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// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
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// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
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// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
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__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
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// [31:2] : Reserved
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// [1] : Clears the SSPRTINTR interrupt
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// [0] : Clears the SSPRORINTR interrupt
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__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
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// [31:2] : Reserved
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// [1] : Transmit DMA Enable
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// [0] : Receive DMA Enable
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} MPS2_SSP_TypeDef;
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// SSP_CR0 Control register 0
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#define SSP_CR0_DSS_Pos 0 // Data Size Select
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#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
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#define SSP_CR0_FRF_Pos 4 // Frame Format Select
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#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
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#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
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#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
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#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
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#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
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#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
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#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
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#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
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#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
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#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
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#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
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// SSP_CR1 Control register 1
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#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
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#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
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#define SSP_CR1_SSE_Pos 1 // Serial port enable
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#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
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#define SSP_CR1_MS_Pos 2 // Master or Slave mode
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#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
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#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
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#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
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// SSP_SR Status register
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#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
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#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
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#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
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#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
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#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
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#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
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#define SSP_SR_RFF_Pos 3 // Receive FIFO full
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#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
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#define SSP_SR_BSY_Pos 4 // Busy
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#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
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// SSP_CPSR Clock prescale register
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#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
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#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
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#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
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// SSPIMSC Interrupt mask set and clear register
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#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
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#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
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#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
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#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
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#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
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#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
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#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
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#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
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// SSPRIS Raw interrupt status register
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#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
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#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
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#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
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#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
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#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
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#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
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#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
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#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
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// SSPMIS Masked interrupt status register
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#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
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#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
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#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
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#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
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#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
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#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
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#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
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#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
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// SSPICR Interrupt clear register
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#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
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#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
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#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
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#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
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// SSPDMACR DMA control register
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#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
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#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
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#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
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#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
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/******************************************************************************/
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/* Audio and Touch Screen (I2C) Peripheral declaration */
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/******************************************************************************/
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typedef struct
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{
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union {
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__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
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__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
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};
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__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
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} MPS2_I2C_TypeDef;
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#define SDA 1 << 1
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#define SCL 1 << 0
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/******************************************************************************/
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/* Audio I2S Peripheral declaration */
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/******************************************************************************/
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typedef struct
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{
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/*!< Offset: 0x000 CONTROL Register (R/W) */
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__IO uint32_t CONTROL; // <h> CONTROL </h>
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// <o.0> TX Enable
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// <0=> TX disabled
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// <1=> TX enabled
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// <o.1> TX IRQ Enable
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// <0=> TX IRQ disabled
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// <1=> TX IRQ enabled
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// <o.2> RX Enable
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// <0=> RX disabled
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// <1=> RX enabled
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// <o.3> RX IRQ Enable
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// <0=> RX IRQ disabled
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// <1=> RX IRQ enabled
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// <o.10..8> TX Buffer Water Level
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// <0=> / IRQ triggers when any space available
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// <1=> / IRQ triggers when more than 1 space available
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// <2=> / IRQ triggers when more than 2 space available
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// <3=> / IRQ triggers when more than 3 space available
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// <4=> Undefined!
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// <5=> Undefined!
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// <6=> Undefined!
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// <7=> Undefined!
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// <o.14..12> RX Buffer Water Level
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// <0=> Undefined!
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// <1=> / IRQ triggers when less than 1 space available
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// <2=> / IRQ triggers when less than 2 space available
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// <3=> / IRQ triggers when less than 3 space available
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// <4=> / IRQ triggers when less than 4 space available
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// <5=> Undefined!
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// <6=> Undefined!
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// <7=> Undefined!
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// <o.16> FIFO reset
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// <0=> Normal operation
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// <1=> FIFO reset
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// <o.17> Audio Codec reset
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// <0=> Normal operation
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// <1=> Assert audio Codec reset
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/*!< Offset: 0x004 STATUS Register (R/ ) */
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__I uint32_t STATUS; // <h> STATUS </h>
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// <o.0> TX Buffer alert
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// <0=> TX buffer don't need service yet
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// <1=> TX buffer need service
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// <o.1> RX Buffer alert
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// <0=> RX buffer don't need service yet
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// <1=> RX buffer need service
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// <o.2> TX Buffer Empty
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// <0=> TX buffer have data
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// <1=> TX buffer empty
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// <o.3> TX Buffer Full
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// <0=> TX buffer not full
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// <1=> TX buffer full
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// <o.4> RX Buffer Empty
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// <0=> RX buffer have data
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// <1=> RX buffer empty
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// <o.5> RX Buffer Full
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// <0=> RX buffer not full
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// <1=> RX buffer full
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union {
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/*!< Offset: 0x008 Error Status Register (R/ ) */
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__I uint32_t ERROR; // <h> ERROR </h>
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// <o.0> TX error
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// <0=> Okay
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// <1=> TX overrun/underrun
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// <o.1> RX error
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// <0=> Okay
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// <1=> RX overrun/underrun
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/*!< Offset: 0x008 Error Clear Register ( /W) */
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__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
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// <o.0> TX error
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// <0=> Okay
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// <1=> Clear TX error
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// <o.1> RX error
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// <0=> Okay
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// <1=> Clear RX error
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};
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/*!< Offset: 0x00C Divide ratio Register (R/W) */
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__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
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// <o.9..0> TX error (default 0x80)
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/*!< Offset: 0x010 Transmit Buffer ( /W) */
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__O uint32_t TXBUF; // <h> Transmit buffer </h>
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// <o.15..0> Right channel
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// <o.31..16> Left channel
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/*!< Offset: 0x014 Receive Buffer (R/ ) */
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__I uint32_t RXBUF; // <h> Receive buffer </h>
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// <o.15..0> Right channel
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// <o.31..16> Left channel
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uint32_t RESERVED1[186];
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__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
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// <o.0> ITEN
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// <0=> Normal operation
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// <1=> Integration Test mode enable
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__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
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// <o.0> SDIN
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__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
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// <o.0> SDOUT
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// <o.1> SCLK
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// <o.2> LRCK
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// <o.3> IRQOUT
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} MPS2_I2S_TypeDef;
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#define I2S_CONTROL_TXEN_Pos 0
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#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
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#define I2S_CONTROL_TXIRQEN_Pos 1
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#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
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#define I2S_CONTROL_RXEN_Pos 2
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#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
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|
|
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#define I2S_CONTROL_RXIRQEN_Pos 3
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#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
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|
|
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#define I2S_CONTROL_TXWLVL_Pos 8
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#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
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|
|
#define I2S_CONTROL_RXWLVL_Pos 12
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|
#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
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|
/* FIFO reset*/
|
|
#define I2S_CONTROL_FIFORST_Pos 16
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|
#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
|
|
/* Codec reset*/
|
|
#define I2S_CONTROL_CODECRST_Pos 17
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|
#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
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|
|
|
#define I2S_STATUS_TXIRQ_Pos 0
|
|
#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
|
|
|
|
#define I2S_STATUS_RXIRQ_Pos 1
|
|
#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
|
|
|
|
#define I2S_STATUS_TXEmpty_Pos 2
|
|
#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
|
|
|
|
#define I2S_STATUS_TXFull_Pos 3
|
|
#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
|
|
|
|
#define I2S_STATUS_RXEmpty_Pos 4
|
|
#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
|
|
|
|
#define I2S_STATUS_RXFull_Pos 5
|
|
#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
|
|
|
|
#define I2S_ERROR_TXERR_Pos 0
|
|
#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
|
|
|
|
#define I2S_ERROR_RXERR_Pos 1
|
|
#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
|
|
|
|
|
|
/******************************************************************************/
|
|
/* Peripheral memory map */
|
|
/******************************************************************************/
|
|
|
|
#define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
|
|
#define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
|
|
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
|
|
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
|
|
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
|
|
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
|
|
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
|
|
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
|
|
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
|
|
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
|
|
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
|
|
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
|
|
|
|
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
|
|
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
|
|
|
|
/******************************************************************************/
|
|
/* Peripheral declaration */
|
|
/******************************************************************************/
|
|
|
|
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
|
|
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
|
|
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
|
|
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
|
|
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
|
|
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
|
|
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
|
|
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
|
|
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
|
|
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
|
|
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
|
|
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
|
|
|
|
/******************************************************************************/
|
|
/* General Function Definitions */
|
|
/******************************************************************************/
|
|
|
|
|
|
/******************************************************************************/
|
|
/* General MACRO Definitions */
|
|
/******************************************************************************/
|
|
|
|
|
|
|
|
#endif /* __FVP_MPS2_H */
|