/* MPS2 CMSIS Library * * Copyright (c) 2006-2018 ARM Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the copyright holder nor the names of its contributors * may be used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ #ifndef __FVP_MPS2_H #define __FVP_MPS2_H #include "peripherallink.h" /* device specific header file */ #if defined ( __CC_ARM ) #pragma anon_unions #endif /******************************************************************************/ /* FPGA System Register declaration */ /******************************************************************************/ typedef struct { __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved // [1:0] : LEDs uint32_t RESERVED1[1]; __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons // [31:2] : Reserved // [1:0] : Buttons uint32_t RESERVED2[1]; __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter // Increments when 32-bit prescale counter reach zero uint32_t RESERVED3[1]; __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler // Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter // The Cycle Up Counter increment when the prescale down counter reach 0 // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ // [31:10] : Reserved // [9] : SHIELD_1_SPI_nCS // [8] : SHIELD_0_SPI_nCS // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS // [3] : CLCD_RESET // [2] : RESERVED // [1] : SPI_nSS // [0] : CLCD_CS } MPS2_FPGAIO_TypeDef; // MISC register bit definitions #define CLCD_CS_Pos 0 #define CLCD_CS_Msk (1UL< CONTROL // TX Enable // <0=> TX disabled // <1=> TX enabled // TX IRQ Enable // <0=> TX IRQ disabled // <1=> TX IRQ enabled // RX Enable // <0=> RX disabled // <1=> RX enabled // RX IRQ Enable // <0=> RX IRQ disabled // <1=> RX IRQ enabled // TX Buffer Water Level // <0=> / IRQ triggers when any space available // <1=> / IRQ triggers when more than 1 space available // <2=> / IRQ triggers when more than 2 space available // <3=> / IRQ triggers when more than 3 space available // <4=> Undefined! // <5=> Undefined! // <6=> Undefined! // <7=> Undefined! // RX Buffer Water Level // <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available // <2=> / IRQ triggers when less than 2 space available // <3=> / IRQ triggers when less than 3 space available // <4=> / IRQ triggers when less than 4 space available // <5=> Undefined! // <6=> Undefined! // <7=> Undefined! // FIFO reset // <0=> Normal operation // <1=> FIFO reset // Audio Codec reset // <0=> Normal operation // <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */ __I uint32_t STATUS; // STATUS // TX Buffer alert // <0=> TX buffer don't need service yet // <1=> TX buffer need service // RX Buffer alert // <0=> RX buffer don't need service yet // <1=> RX buffer need service // TX Buffer Empty // <0=> TX buffer have data // <1=> TX buffer empty // TX Buffer Full // <0=> TX buffer not full // <1=> TX buffer full // RX Buffer Empty // <0=> RX buffer have data // <1=> RX buffer empty // RX Buffer Full // <0=> RX buffer not full // <1=> RX buffer full union { /*!< Offset: 0x008 Error Status Register (R/ ) */ __I uint32_t ERROR; // ERROR // TX error // <0=> Okay // <1=> TX overrun/underrun // RX error // <0=> Okay // <1=> RX overrun/underrun /*!< Offset: 0x008 Error Clear Register ( /W) */ __O uint32_t ERRORCLR; // ERRORCLR // TX error // <0=> Okay // <1=> Clear TX error // RX error // <0=> Okay // <1=> Clear RX error }; /*!< Offset: 0x00C Divide ratio Register (R/W) */ __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock // TX error (default 0x80) /*!< Offset: 0x010 Transmit Buffer ( /W) */ __O uint32_t TXBUF; // Transmit buffer // Right channel // Left channel /*!< Offset: 0x014 Receive Buffer (R/ ) */ __I uint32_t RXBUF; // Receive buffer // Right channel // Left channel uint32_t RESERVED1[186]; __IO uint32_t ITCR; // Integration Test Control Register // ITEN // <0=> Normal operation // <1=> Integration Test mode enable __O uint32_t ITIP1; // Integration Test Input Register 1 // SDIN __O uint32_t ITOP1; // Integration Test Output Register 1 // SDOUT // SCLK // LRCK // IRQOUT } MPS2_I2S_TypeDef; #define I2S_CONTROL_TXEN_Pos 0 #define I2S_CONTROL_TXEN_Msk (1UL<