mirror of https://github.com/ARMmbed/mbed-os.git
177 lines
5.9 KiB
C
177 lines
5.9 KiB
C
/**************************************************************************//**
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* @file adc.c
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* @version V1.00
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* $Revision: 13 $
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* $Date: 14/05/29 1:13p $
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* @brief NUC472/NUC442 ADC driver source file
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*
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* @note
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* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "NUC472_442.h"
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/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
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@{
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*/
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/** @addtogroup NUC472_442_ADC_Driver ADC Driver
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@{
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*/
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/** @addtogroup NUC472_442_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
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@{
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*/
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/**
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* @brief This API configures ADC module to be ready for convert the input from selected channel
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* @param[in] adc Base address of ADC module
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* @param[in] u32InputMode Input mode (single-end/differential). Valid values are:
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* - \ref ADC_INPUT_MODE_SINGLE_END
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* - \ref ADC_INPUT_MODE_DIFFERENTIAL
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* @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are:
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* - \ref ADC_OPERATION_MODE_SINGLE
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* - \ref ADC_OPERATION_MODE_SINGLE_CYCLE
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* - \ref ADC_OPERATION_MODE_CONTINUOUS
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* @param[in] u32ChMask Channel enable bit. Valid values are:
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* - \ref ADC_CH_0_MASK
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* - \ref ADC_CH_1_MASK
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* - \ref ADC_CH_2_MASK
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* - \ref ADC_CH_3_MASK
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* - \ref ADC_CH_4_MASK
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* - \ref ADC_CH_5_MASK
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* - \ref ADC_CH_6_MASK
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* - \ref ADC_CH_7_MASK
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* - \ref ADC_CH_8_MASK
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* - \ref ADC_CH_9_MASK
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* - \ref ADC_CH_10_MASK
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* - \ref ADC_CH_11_MASK
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* - \ref ADC_CH_TS_MASK
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* - \ref ADC_CH_BG_MASK
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* @return None
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* @note This API does not turn on ADC power nor does trigger ADC conversion
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*/
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void ADC_Open(ADC_T *adc,
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uint32_t u32InputMode,
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uint32_t u32OpMode,
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uint32_t u32ChMask)
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{
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ADC->CTL |= u32InputMode;
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ADC->CTL |= u32OpMode;
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ADC->CHEN = (ADC->CHEN & ~(ADC_CHEN_CHEN_Msk | ADC_CHEN_ADBGEN_Msk | ADC_CHEN_ADTSEN_Msk)) | u32ChMask;
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return;
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}
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/**
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* @brief Disable ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_Close(ADC_T *adc)
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{
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SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
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SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
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return;
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}
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/**
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* @brief Configure the hardware trigger condition and enable hardware trigger
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* @param[in] adc Base address of ADC module
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* @param[in] u32Source Decides the hardware trigger source. Valid values are:
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* - \ref ADC_TRIGGER_BY_EXT_PIN
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* - \ref ADC_TRIGGER_BY_PWM
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* @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
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* trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
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* time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
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* is used to set trigger condition. Valid values are:
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* - \ref ADC_LOW_LEVEL_TRIGGER
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* - \ref ADC_HIGH_LEVEL_TRIGGER
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* - \ref ADC_FALLING_EDGE_TRIGGER
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* - \ref ADC_RISING_EDGE_TRIGGER
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* @return None
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*/
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void ADC_EnableHWTrigger(ADC_T *adc,
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uint32_t u32Source,
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uint32_t u32Param)
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{
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ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
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if(u32Source == ADC_TRIGGER_BY_EXT_PIN) {
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ADC->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_HWTRGCOND_Msk);
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ADC->CTL |= u32Source | u32Param | ADC_CTL_HWTRGEN_Msk;
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} else {
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ADC->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_PWMTRGDLY_Msk);
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ADC->CTL |= u32Source | (u32Param << ADC_CTL_PWMTRGDLY_Pos) | ADC_CTL_HWTRGEN_Msk;
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}
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return;
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}
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/**
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* @brief Disable hardware trigger ADC function.
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_DisableHWTrigger(ADC_T *adc)
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{
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ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
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return;
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}
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/**
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* @brief Enable the interrupt(s) selected by u32Mask parameter.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
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* corresponds to a interrupt status. This parameter decides which
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* interrupts will be enabled.
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* - \ref ADC_ADF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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*/
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void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
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{
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if(u32Mask & ADC_ADF_INT)
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ADC->CTL |= ADC_CTL_ADCIEN_Msk;
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if(u32Mask & ADC_CMP0_INT)
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ADC->CMP[0] |= ADC_CMP0_ADCMPIE_Msk;
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if(u32Mask & ADC_CMP1_INT)
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ADC->CMP[1] |= ADC_CMP1_ADCMPIE_Msk;
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return;
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}
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/**
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* @brief Disable the interrupt(s) selected by u32Mask parameter.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
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* corresponds to a interrupt status. This parameter decides which
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* interrupts will be disabled.
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* - \ref ADC_ADF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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*/
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void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
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{
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if(u32Mask & ADC_ADF_INT)
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ADC->CTL &= ~ADC_CTL_ADCIEN_Msk;
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if(u32Mask & ADC_CMP0_INT)
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ADC->CMP[0] &= ~ADC_CMP0_ADCMPIE_Msk;
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if(u32Mask & ADC_CMP1_INT)
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ADC->CMP[1] &= ~ADC_CMP1_ADCMPIE_Msk;
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return;
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}
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/*@}*/ /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NUC472_442_ADC_Driver */
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/*@}*/ /* end of group NUC472_442_Device_Driver */
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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