mirror of https://github.com/ARMmbed/mbed-os.git
388 lines
18 KiB
C
388 lines
18 KiB
C
/**
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*******************************************************************************
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* @file system_TMPM46B.c
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
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* TOSHIBA 'TMPM46B' Device Series
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* @version V2.0.2.4
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* @date 2018/3/15
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
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*
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* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
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*******************************************************************************
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*/
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#include "TMPM46B.h"
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/*-------- <<< Start of configuration section >>> ----------------------------*/
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/* Watchdog Timer (WD) Configuration */
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#define WD_SETUP (1U)
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#define WDMOD_Val (0x00000000UL)
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#define WDCR_Val (0x000000B1UL)
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/* Clock Generator (CG) Configuration */
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#define CLOCK_SETUP (1U)
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#define SYSCR_Val (0x00010000UL)
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#define OSCCR_Val (0x00020501UL) /* OSCCR<OSCSEL> = 1, OSCCR<XEN2> = 0, OSCCR<XEN1> = 1, <HOSCON> = 1 */
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#define STBYCR_Val (0x00000003UL)
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#define CG_8M_MUL_4_FPLL (0x00006A0FUL<<1U)
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#define CG_8M_MUL_5_FPLL (0x00006A13UL<<1U)
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#define CG_8M_MUL_6_FPLL (0x00006917UL<<1U)
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#define CG_8M_MUL_10_FPLL (0x00006A26UL<<1U)
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#define CG_8M_MUL_12_FPLL (0x0000692EUL<<1U)
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#define CG_10M_MUL_4_FPLL (0x00006A0FUL<<1U)
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#define CG_10M_MUL_5_FPLL (0x00006A13UL<<1U)
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#define CG_10M_MUL_6_FPLL (0x00006917UL<<1U)
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#define CG_10M_MUL_8_FPLL (0x00006A1EUL<<1U)
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#define CG_10M_MUL_10_FPLL (0x00006A26UL<<1U)
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#define CG_10M_MUL_12_FPLL (0x0000692EUL<<1U)
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#define CG_12M_MUL_4_FPLL (0x00006A0FUL<<1U)
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#define CG_12M_MUL_5_FPLL (0x00006A13UL<<1U)
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#define CG_12M_MUL_8_FPLL (0x00006A1EUL<<1U)
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#define CG_12M_MUL_10_FPLL (0x00006A26UL<<1U)
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#define CG_16M_MUL_4_FPLL (0x00006A0FUL<<1U)
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#define CG_PLLSEL_PLLON_SET ((uint32_t)0x00010000)
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#define CG_PLLSEL_PLLON_CLEAR ((uint32_t)0xFFFEFFFF)
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#define CG_PLLSEL_PLLSEL_SET ((uint32_t)0x00020000)
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#define CG_PLLSEL_PLLST_MASK ((uint32_t)0x00040000)
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#define CG_OSCCR_XEN1_SET ((uint32_t)0x00000001)
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#define CG_OSCCR_XEN2_CLEAR ((uint32_t)0xFFFFFFFD)
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#define CG_OSCCR_HOSCON_SET ((uint32_t)0x00000400)
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#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
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#define CG_WUP_START_SET ((uint32_t)0x00004000)
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#define CG_WUEF_VALUE_MASK ((uint32_t)0x00008000)
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#define CG_OSCCR_WUPSEL2_SET ((uint32_t)0x00020000)
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#define CG_OSCCR_WUPSEL1_CLEAR ((uint32_t)0xFFFEFFFF)
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#define CG_OSCCR_OSCF_MASK ((uint32_t)0x00000200)
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#define WD_MOD_WDTE_SET ((uint32_t)0x00000080)
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//#define PLLSEL_Ready CG_16M_MUL_5_FPLL /* -M46BSTK */
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#define PLLSEL_Ready CG_12M_MUL_5_FPLL /* +M46BSTK */
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#define PLLSEL_Val (PLLSEL_Ready|0x00030000UL)
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#define PLLSEL_MASK (0x0000FFFEUL)
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/*-------- <<< End of configuration section >>> ------------------------------*/
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/*-------- DEFINES -----------------------------------------------------------*/
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/* Define clocks */
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#define OSC_8M ( 8000000UL)
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#define OSC_10M (10000000UL)
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#define OSC_12M (12000000UL)
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#define OSC_16M (16000000UL)
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//#define EXTALH OSC_16M /* External high-speed oscillator freq */ /* -M46BSTK */
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#define EXTALH OSC_12M /* External high-speed oscillator freq */ /* +M46BSTK */
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#define XTALH OSC_10M /* Internal high-speed oscillator freq */
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/* Configure Warm-up time */
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#define HZ_1M (1000000UL)
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#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
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#define WU_TIME_PLL (100UL) /* warm-up time for PLL is 100us */
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#define OSCCR_WUPT_MASK (0x000FFFFFUL)
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#define OSCCR_WUPT_EXT ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
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#define OSCCR_WUPT_PLL ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U)
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#if (CLOCK_SETUP) /* Clock(external) Setup */
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/* Determine core clock frequency according to settings */
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/* System clock is high-speed clock*/
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#if (OSCCR_Val & (1U<<8U))
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#define CORE_TALH (EXTALH)
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#else
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#define CORE_TALH (XTALH)
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#endif
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#if ((PLLSEL_Val & (1U<<16U)) && (PLLSEL_Val & (1U<<17U))) /* If PLL selected and enabled */
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#if (CORE_TALH == OSC_8M) /* If input is 8MHz */
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#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_4_FPLL))
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#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 32MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_5_FPLL))
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#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 40MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_6_FPLL))
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#define __CORE_CLK (CORE_TALH * 6U ) /* output clock is 48MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_8_FPLL))
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#define __CORE_CLK (CORE_TALH * 8U ) /* output clock is 64MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_10_FPLL))
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#define __CORE_CLK (CORE_TALH * 10U ) /* output clock is 80MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL))
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#define __CORE_CLK (CORE_TALH * 12U ) /* output clock is 96MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 8MHz */
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#elif (CORE_TALH == OSC_10M) /* If input is 10MHz */
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#if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_4_FPLL))
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#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 40MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_5_FPLL))
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#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 50MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_6_FPLL))
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#define __CORE_CLK (CORE_TALH * 6U ) /* output clock is 60MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL))
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#define __CORE_CLK (CORE_TALH * 8U ) /* output clock is 80MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_10_FPLL))
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#define __CORE_CLK (CORE_TALH * 10U ) /* output clock is 100MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_12_FPLL))
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#define __CORE_CLK (CORE_TALH * 12U ) /* output clock is 120MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 10MHz */
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#elif (CORE_TALH == OSC_12M) /* If input is 12MHz */
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#if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_4_FPLL)
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#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 48MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_5_FPLL)
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#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 60MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_6_FPLL)
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#define __CORE_CLK (CORE_TALH * 6U ) /* output clock is 72MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL)
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#define __CORE_CLK (CORE_TALH * 8U ) /* output clock is 96MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_10_FPLL)
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#define __CORE_CLK (CORE_TALH * 10U ) /* output clock is 120MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 12MHz */
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#elif (CORE_TALH == OSC_16M) /* If input is 16MHz */
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#if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_4_FPLL)
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#define __CORE_CLK (CORE_TALH * 4U ) /* output clock is 64MHz */
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#elif ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_5_FPLL)
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#define __CORE_CLK (CORE_TALH * 5U ) /* output clock is 80MHz */
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#else /* fc -> reserved */
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#define __CORE_CLK (0U)
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#endif /* End input is 16MHz */
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#else /* input clock not known */
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#define __CORE_CLK (0U)
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#error "Core Oscillator Frequency invalid!"
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#endif /* End switch input clock */
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#else
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#define __CORE_CLK (CORE_TALH)
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#endif
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#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
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#define __CORE_SYS (__CORE_CLK)
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#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/2 */
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#define __CORE_SYS (__CORE_CLK / 2U)
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#elif ((SYSCR_Val & 7U) == 5U) /* Gear -> fc/4 */
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#define __CORE_SYS (__CORE_CLK / 4U)
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#elif ((SYSCR_Val & 7U) == 6U) /* Gear -> fc/8 */
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#define __CORE_SYS (__CORE_CLK / 8U)
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#elif ((SYSCR_Val & 7U) == 7U) /* Gear -> fc/16 */
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#define __CORE_SYS (__CORE_CLK / 16U)
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#else /* Gear -> reserved */
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#define __CORE_SYS (0U)
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#endif
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#else
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#define __CORE_SYS (XTALH)
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#endif /* clock Setup */
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/* Clock Variable definitions */
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uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Update SystemCoreClock according register values.
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*/
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void SystemCoreClockUpdate(void)
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{ /* Get Core Clock Frequency */
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uint32_t CoreClock = 0U;
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uint32_t CoreClockInput = 0U;
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uint32_t regval = 0U;
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uint32_t oscsel = 0U;
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uint32_t pllsel = 0U;
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uint32_t pllon = 0U;
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/* Determine clock frequency according to clock register values */
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/* System clock is high-speed clock */
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regval = TSB_CG->OSCCR;
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oscsel = regval & CG_OSCCR_OSCSEL_SET;
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if (oscsel) { /* If system clock is External high-speed oscillator freq */
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CoreClock = EXTALH;
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} else { /* If system clock is Internal high-speed oscillator freq */
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CoreClock = XTALH;
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}
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regval = TSB_CG->PLLSEL;
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pllsel = regval & CG_PLLSEL_PLLSEL_SET;
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pllon = regval & CG_PLLSEL_PLLON_SET;
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if (pllsel && pllon) { /* If PLL enabled */
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if (CoreClock == OSC_8M) { /* If input is 8MHz */
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if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_4_FPLL) {
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CoreClockInput = CoreClock * 4U; /* output clock is 32MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_5_FPLL) {
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CoreClockInput = CoreClock * 5U; /* output clock is 40MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_6_FPLL) {
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CoreClockInput = CoreClock * 6U; /* output clock is 48MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_10_FPLL) {
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CoreClockInput = CoreClock * 10U; /* output clock is 80MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) {
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CoreClockInput = CoreClock * 12U; /* output clock is 96MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == OSC_10M) { /* If input is 10MHz */
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if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_4_FPLL) {
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CoreClockInput = CoreClock * 4U; /* output clock is 40MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_5_FPLL) {
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CoreClockInput = CoreClock * 5U; /* output clock is 50MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_6_FPLL) {
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CoreClockInput = CoreClock * 6U; /* output clock is 60MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) {
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CoreClockInput = CoreClock * 8U; /* output clock is 80MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_10_FPLL) {
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CoreClockInput = CoreClock * 10U; /* output clock is 100MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_12_FPLL) {
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CoreClockInput = CoreClock * 12U; /* output clock is 120MHz */
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}else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == OSC_12M) { /* If input is 12MHz */
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if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_4_FPLL) {
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CoreClockInput = CoreClock * 4U; /* output clock is 48MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_5_FPLL) {
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CoreClockInput = CoreClock * 5U; /* output clock is 60MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) {
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CoreClockInput = CoreClock * 8U; /* output clock is 96MHz */
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} else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_10_FPLL) {
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CoreClockInput = CoreClock * 10U; /* output clock is 120MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else if (CoreClock == OSC_16M) { /* If input is 16MHz */
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if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_16M_MUL_4_FPLL) {
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CoreClockInput = CoreClock * 4U; /* output clock is 64MHz */
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} else {
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CoreClockInput = 0U; /* fc -> reserved */
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}
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} else {
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CoreClockInput = 0U;
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}
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} else {
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CoreClockInput = CoreClock;
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}
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switch (TSB_CG->SYSCR & 7U) {
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case 0U:
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SystemCoreClock = CoreClockInput; /* Gear -> fc */
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break;
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case 1U:
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case 2U:
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case 3U: /* Gear -> reserved */
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SystemCoreClock = 0U;
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break;
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case 4U: /* Gear -> fc/2 */
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SystemCoreClock = CoreClockInput / 2U;
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break;
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case 5U: /* Gear -> fc/4 */
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SystemCoreClock = CoreClockInput / 4U;
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break;
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case 6U: /* Gear -> fc/8 */
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SystemCoreClock = CoreClockInput / 8U;
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break;
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case 7U: /* Gear -> fc/16 */
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if (CoreClockInput >= OSC_16M){
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SystemCoreClock = CoreClockInput / 16U;
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} else{
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SystemCoreClock = 0U;
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}
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break;
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default:
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SystemCoreClock = 0U;
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break;
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}
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit(void)
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{
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uint32_t regval = 0U;
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volatile uint32_t pllst = 0U;
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volatile uint32_t wuef = 0U;
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volatile uint32_t oscf = 0U;
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uint32_t wdte = 0U;
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#if defined ( __CC_ARM )/*Enable FPU for Keil*/
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#if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */
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/* enable FPU if available and used */
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SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
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(3UL << 11*2) ); /* set CP11 Full Access */
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#endif
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#endif
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#if (WD_SETUP) /* Watchdog Setup */
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while (TSB_WD->FLG != 0U) {
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} /* When writing to WDMOD or WDCR, confirm "0" of WDFLG<FLG>. */
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TSB_WD->MOD = WDMOD_Val;
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regval = TSB_WD->MOD;
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wdte = regval & WD_MOD_WDTE_SET;
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if (!wdte) { /* If watchdog is to be disabled */
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TSB_WD->CR = WDCR_Val;
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} else {
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/*Do nothing*/
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}
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#endif
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#if (CLOCK_SETUP) /* Clock(external) Setup */
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TSB_CG->SYSCR = SYSCR_Val;
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TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
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TSB_CG->OSCCR |= OSCCR_WUPT_EXT;
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TSB_CG->OSCCR |= CG_OSCCR_HOSCON_SET;
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TSB_CG->OSCCR |= CG_OSCCR_XEN1_SET;
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TSB_CG->OSCCR |= CG_OSCCR_WUPSEL2_SET;
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TSB_CG->OSCCR &= CG_OSCCR_WUPSEL1_CLEAR;
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TSB_CG->OSCCR |= CG_WUP_START_SET;
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wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
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while (wuef) {
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wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
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} /* Warm-up */
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TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
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oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
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while (oscf != CG_OSCCR_OSCF_MASK) {
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oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
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} /* Confirm CGOSCCR<OSCF>="1" */
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/* TSB_CG->OSCCR &= CG_OSCCR_XEN2_CLEAR ; */ /* IHOSC should be not stopped for using WDT. */
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TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
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TSB_CG->OSCCR |= OSCCR_WUPT_PLL;
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TSB_CG->PLLSEL &= CG_PLLSEL_PLLON_CLEAR;
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TSB_CG->PLLSEL = PLLSEL_Ready;
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TSB_CG->OSCCR |= CG_WUP_START_SET;
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wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
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while (wuef) {
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wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
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} /* Warm-up */
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TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
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TSB_CG->OSCCR |= OSCCR_WUPT_PLL;
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TSB_CG->PLLSEL |= CG_PLLSEL_PLLON_SET; /* PLL enabled */
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TSB_CG->STBYCR = STBYCR_Val;
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TSB_CG->OSCCR |= CG_WUP_START_SET;
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wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
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while (wuef) {
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wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
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} /* Warm-up */
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TSB_CG->PLLSEL |= CG_PLLSEL_PLLSEL_SET;
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pllst = TSB_CG->PLLSEL & CG_PLLSEL_PLLST_MASK;
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while (pllst != CG_PLLSEL_PLLST_MASK) {
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pllst = TSB_CG->PLLSEL & CG_PLLSEL_PLLST_MASK;
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} /*Confirm CGPLLSEL<PLLST> = "1" */
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#endif
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}
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