* Setting the PWM period now correctly updates all other channels to keep their duty cycle
* No longer keep values in RAM that can be read directly from a register
* Setting the PWM duty cycle to 100% no longer makes the signal glitch on every period
* Code condensation
* Added PD9 back in (for some reason it was at some point removed from the pinmap, not sure why because it is a usable pin when you remove the on-board sensor or use the Pearl chip standalone)
* Fixed PWM locations to match the pin-CC channel combinations.
Allows clocking the device from RC oscillators (HFRCO, LFRCO).
Note that we can not use the em_cmu.h enums directly as the
preprocessor can not do comparisons on them.
Related changes in serial_api, so that LEUART clock is within
acceptable limits on Pearl.
Contains quite a bit of indentation changes to make the preprocessor
logic more readable so recommend viewing the diff in ignore whitespace
mode.
Keep a counter of sleeps blocked for every device, and do not try
to unblock sleep modes we did not block. This fixes problems where
serial events would cause EM1/EM2 to be unblocked too early,
causing the MCU to go to EM3 and not being able to wake up.
When initializing for use with the board controller, the LEUART must
be clocked from HF clock as the baud rate is otherwise too high.
Do this by first initializing to "standard" 9600, then call serial_baud
which will handle setting up the clocks and dividers.
Switch caused a phantom 0xFF frame to appear on the line when we switched
from LEUART to USART due to a baud rate was increase. This was short
enough that it was only visible at high (~115kbps) speeds.
As a fix, skip disabling the GPIO pins (as their configuration does not
change), and defer disabling the LEUART routing until at the very last
moment. Additionally, do not call serial_format, but immediately
initialize the UART to correct params.
- Do not attempt to disable the transmitter. Did not find a robust
way to do so - see comment in file for more info.
- Do not unblock sleep when abort is called externally, this leads
to jams as EM1 block gets disabled and the next sleep call places
the hardware to directly to EM3.
- Retain more status when switching over from LEUART to USART in
Pearl: keep registered IRQ handlers and other IRQ status.
Changed SPI implementation: #1 To avoid clearing data from buffers, during splitted DMA transfer
RX/TX buffer clear is done only when transfer is started.
USART transmit is completed instead of DMA/LDMA transfer completed.
When doing a large transfer over the LDMA it is required to wait TX to be completed
before transferring the next part of the data. Added a loop, to wait until TXC flag is set in function USART_STATUS_TXC.
+ minor code cleanup and EM1 sleep is allowed again.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Steven Cooreman
Mikko Polojarvi
Aksel Skauge Mellbye
jhokajar