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17120 Commits (f0c4e949c5254cf3d3ef8073a26f3d0ce3b3b51f)

Author SHA1 Message Date
ccli8 e9a7d88456 Change pinout to meet NuMaker-PFM-M2351 V1.1 2018-07-27 13:30:07 -05:00
ccli8 ae64129c47 Change secure flash/SRAM to 256KB/32KB as default 
This is to compilant with CMSIS pack.
 2018-07-27 13:30:07 -05:00
ccli8 f268b12ba2 Change secure/non-secure stack/heap size 
1. Change RTOS-less main stack/RTOS ISR stack size to 2KiB
2. Change secure/non-secure heap size to 16KiB/32KiB for IAR
 2018-07-27 13:30:07 -05:00
ccli8 9fac970523 Meet new RTC HAL spec (Mbed OS 5.9) 
1. Power down RTC access from CPU domain in rtc_free. After rtc_free, RTC gets
   inaccessible from CPU domain but keeps counting.
2. Fix RTC cannot cross reset cycle.
 2018-07-27 13:30:07 -05:00
ccli8 d5d8c233d0 Meet new lp_ticker HAL spec (Mbed OS 5.9) 
1. Add LPTICKER in device_has option of targets.json file.
2. Disable interrupt in lp_ticker_init
3. Add lp_ticker_free
4. Enable interrupt in lp_ticker_set_interrupt/lp_ticker_fire_interrupt
5. Disable interupt in ISR
 2018-07-27 13:30:07 -05:00
ccli8 543f72d7bd Meet new us_ticker HAL spec (Mbed OS 5.9) 
1. Add USTICKER in device_has option of targets.json file.
2. Disable interrupt in us_ticker_init
3. Add us_ticker_free
4. Enable interrupt in us_ticker_set_interrupt/us_ticker_fire_interrupt
5. Disable interrupt in ISR
 2018-07-27 13:30:07 -05:00
ccli8 18ce2e1b6b Add secure gateway functions SYS_LockReg_S/SYS_UnlockReg_S 2018-07-27 13:30:07 -05:00
ccli8 c91f71b0dc Add SD pinmap 2018-07-27 13:30:07 -05:00
ccli8 754589b6a6 Default MBED_TZ_DEFAULT_ACCESS to 1 to control secure SYS/CLK regions from non-secure threads 
To initialize/uninitialize H/W module, we need to control secure SYS/CLK regions through secure functions.
For a new thread to call these secure functions, we need to allocate secure context for it.
 2018-07-27 13:30:07 -05:00
ccli8 0e6a76f113 Replace __attribute__((cmse_nonsecure_entry)) with compiler agnostic __NONSECURE_ENTRY 2018-07-27 13:30:07 -05:00
ccli8 07b21b42e5 Support TrustZone and bootloader for IAR 2018-07-27 13:30:07 -05:00
ccli8 ad5772a425 Fix part number in IAR export 2018-07-27 13:30:07 -05:00
ccli8 f6642cbfd3 Add consistency check for CRYPTO/CRPT's secure attribute and TRNG/Mbed TLS H/W 2018-07-27 13:30:06 -05:00
ccli8 5839431812 Remove dead code with '#if 0' in SPI 2018-07-27 13:30:06 -05:00
ccli8 d611a3c9b0 Add GPIO debounce configuration in targets.json 2018-07-27 13:30:06 -05:00
ccli8 b1b57d24af Support PWM out 2018-07-27 13:30:06 -05:00
ccli8 6b811afb73 Support analog-in 2018-07-27 13:30:06 -05:00
ccli8 bce2b6460d Support TRNG 
To change TRNG security state, we need to:
1. Change CRPT/CRYPTO bit in NVIC/SCU in partition_M2351.h
2. Add/remove TRNG in device_has list in targets.json to match partition_M2351.h
 2018-07-27 13:30:06 -05:00
ccli8 b86c957c0d Centralize size configuration for secure flash, secure SRAM, NSC, and bootloader 2018-07-27 13:30:06 -05:00
ccli8 3950b12a82 Change NSC location 
NSC location has the following requirements:
1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
 2018-07-27 13:30:06 -05:00
ccli8 1e7b6eec89 Upgrade partition format 
Following BSP, this upgrade makes partitioning flash/SRAM clear.
flash_api.c relies on flash partition, so it is updated accordingly.
 2018-07-27 13:30:06 -05:00
ccli8 d2f5548269 Fix page size in flash IAP 
In Mbed OS, page size is program unit, which is different than FMC definition.
After fixing page size, we can pass NVSTORE test (mbed-os-features-nvstore-tests-nvstore-functionality).
 2018-07-27 13:30:06 -05:00
ccli8 3ac5e48d40 Support flash IAP 2018-07-27 13:30:06 -05:00
ccli8 68b8db1a1e Add missing delay in lp_ticker 2018-07-27 13:30:06 -05:00
ccli8 c34d8aeab2 Trim HIRC48 to 48M against LXT 2018-07-27 13:30:06 -05:00
ccli8 c7ed684285 Support I2C 2018-07-27 13:30:06 -05:00
ccli8 ffe1e23ba0 Support SPI 2018-07-27 13:30:06 -05:00
ccli8 a8ed3ff5cd Refine UART code 
1. Replace SYS_ResetModule/CLK_SetModuleClock/CLK_EnableModuleClock/CLK_DisableModuleClock with TrustZone-aware versions.
2. Configure all UART to secure
3. Support asynchronous transfer
4. Remove sleep management code, which has been replaced with Sleep Manager.
 2018-07-27 13:30:06 -05:00
ccli8 61a021ca9a Support PDMA 2018-07-27 13:30:06 -05:00
cyliangtw 2cd825d463 Rework us_ticker and lp_ticker 
The rework includes the following:
1. Remove ticker overflow handling because upper layer (mbed_ticker_api.c) has done with it.
   This makes us_ticker/lp_ticker implementation more succinct and avoids potential error.
2. Refine timer register access with low-power clock source
 2018-07-27 13:30:06 -05:00
ccli8 7cf3501935 Remove peripheral sleep management from hal_sleep/hal_deepsleep 
The upper layer has introduced Sleep Manager to handle the task.
 2018-07-27 13:30:06 -05:00
ccli8 a1c8803c7d Rework RTC 
The rework includes the following:
1. Support year range beyond H/W RTC 2000~2099.
2. Refine RTC register access with low-power clock source
 2018-07-27 13:30:06 -05:00
ccli8 3f4da6166d Fix GPIO to be TrustZone-aware 
1. Revise NU_PORT_BASE to be TrustZone-aware
2. Add TrustZone-aware NU_GET_GPIO_PIN_DATA/NU_SET_GPIO_PIN_DATA to replace GPIO_PIN_DATA
3. Revise pin_function to be TrustZone-aware
 2018-07-27 13:30:06 -05:00
ccli8 160c26847a Fix SystemCoreClockUpdate isn't called in non-secure domain 2018-07-27 13:30:06 -05:00
ccli8 7f0e35f5ad Fix HCLK clock source 
There is a reset halt issue with PLL in A version.
Work around it by using HIRC48 instead of PLL as HCLK clock source.
 2018-07-27 13:30:06 -05:00
ccli8 001aa01a6d Add secure BSP driver function 
SYS_ResetModule_S
CLK_SetModuleClock_S
CLK_EnableModuleClock_S
CLK_DisableModuleClock_S
 2018-07-27 13:30:06 -05:00
ccli8 07548bdc07 Unify secure/non-secure peripheral base based on partition file 2018-07-27 13:30:06 -05:00
ccli8 e51be32292 Configure most modules to non-secure 
All modules are configured to non-secure except:
1. TIMER0/1 hard-wired to secure and TIMER2/3 reserved for non-secure.
2. PDMA0 hard-wired to secure and PDMA1 reserved for non-secure.
3. RTC configured to secure and shared to non-secure through NSC.
4. CRYPTO configured to secure and shared to non-secure through NSC.
 2018-07-27 13:30:06 -05:00
ccli8 dbaf7ea0dd Fix STDIO UART 2018-07-27 13:30:06 -05:00
ccli8 f5029ff739 Fix target configuration 
1. NUMAKER_PFM_M2351 defaults to non-secure
2. Add NUMAKER_PFM_M2351_S/NUMAKER_PFM_M2351_NS which are for secure/non-secure build respectively.
3. Change output format to Intel HEX
4. Fix device name to M2351KIAAEES from M2351K1AAEES
5. Add detect_code
 2018-07-27 13:30:06 -05:00
cyliangtw f861923709 To fulfill _rtc_localtime one more argument 2018-07-27 13:30:05 -05:00
deepikabhavnani d710ee0d4e Disabled fault handler support 2018-07-27 13:30:05 -05:00
cyliangtw db4048d199 Add gpio_is_connected 2018-07-27 13:30:05 -05:00
cyliangtw 4561c86a4e Set secure SRAM size as 24KB in SAU & SCU 2018-07-27 13:30:05 -05:00
cyliangtw 6e799ec9e4 Set 48KB SRAM and UART0 as non-secure 2018-07-27 13:30:05 -05:00
cyliangtw 1f891fc2d6 Resolve reset halt issue in MP chip A version 2018-07-27 13:30:05 -05:00
cyliangtw 602aac8813 Sync IRQ arrangement to fulfill MP version 2018-07-27 13:30:05 -05:00
cyliangtw 2bd15eac69 Remove redundant GetPC 2018-07-27 13:30:05 -05:00
cyliangtw f3afbf2e00 Migrate for MP chip version, build sucessfully 2018-07-27 13:30:05 -05:00
Deepika 7a48a74967 Support TrustZone in port_read/port_write 2018-07-27 13:30:05 -05:00