This automated test makes sure that the serial
syncrhonous API ensures a full transmission before
the function returns. The complete string sent by
printf shall be completely transferred before printf
returns and the sleep modes are called.
mbed Issue #1849
Added CAN API support for NUCLEO_L476RG target.
"stm32l476xx.h" file was changed to avoid compilation errors.
Change-Id: Ifadf7048f6c72c0311ec915e47ce2190460ede68
Added CAN API support for DISCO_L476VG target.
*stm32l476xx.h* file was changed to avoid compilation errors.
NOTE: MBED_29 or MBED_30 cannot be tested on this platform because CAN pins are
soldered to USB, GYRO and others.
Change-Id: I2e85bd36dc45872b1ab617f072de98164f2c96f8
We're ensuring target and host start-up sync here in 2 ways:
1) adding a delay on host side to make sure the serial
initialization can happen before sending a character is sent to target
2) in case of serial_nc_rx_auto.py test, we're sending a
first character S which will trigger the move from rx+tx
to NC+rx.
This should avoid any crossing case due to HSOT being faster than target or vice-versa
During initialization phase of the 2 NC serial tests,
there is a character being sent from host to target,
based on MBED_HOSTTEST_START. The problem is that
the target firmware then creates a "new" serial on the
same serial interface. the new or should, or at least may,
induce a reset of the IP, so that the character sent by host
would be lost. So we're moving the new earlier.
the real testing part happens later, to check the next
character is not received or sent.
- Resetting in LPCXpresso IDE did not reset the LCD controller which
sometimes could cause strange behaviour
- The ROM_LAT bit in the MATRIXARB register must be set in order to
prevent a HardFault when debugging
- The change of compiler in LPCXpresso IDE to ARM launchpad GCC5 was
causing build errors due to multiply defined timeval symbol.
- The exporters for LPCXpresso IDE did not set the FPU_PRESENT define
for assembler, only for c/c++. This caused very strange behaviour
in the RTOS code (e.g. timeouts no longer working, context switches
failing etc.)
We need to remove *can_api.c* file accordingly to new directory structure.
Without that we can't compile any CAN mBed test.
Change-Id: I3d4f798ad75ec1b4c4a1d7ed877e71b7db6bf60f
Added CAN API support for NUCLEO_F302R8 target.
*stm32f302x8.h* file was changed to avoid compilation errors.
Change-Id: Ia4ee8a90fe3f0ad6955dde21e78ea4a6c05e4fcd
Added CAN API support for NUCLEO_F303K8 target.
*stm32f303x8.h* file was changed to avoid compilation errors.
Change-Id: If093c84f19c5a5ef68938af4653a25271c1108ba
Added CAN API support for NUCLEO_F303RE target.
*stm32f303xe.h* file was changed to avoid compilation errors.
Change-Id: Ia6519c982261d43165dbce73cab7cfc0617474e2
Added CAN API support for NUCLEO_F334R8 target.
*stm32f334x8.h* file was changed to avoid compilation errors.
Change-Id: Ic7b3273ffe24940ecdc189d2566a6a7f66825ce6
Added CAN API support for NUCLEO_F042K6 target.
"stm32f042x6.h" file was changed to avoid compilation errors.
Change-Id: I9622a233775fc6834201a322740bf5026244d50e
Added CAN API support for NUCLEO_F072RB target.
*stm32f072xb.h* file was changed to avoid compilation errors.
Change-Id: I9da75fde29fd19f0326d554acc1dbb5386b08317
Added CAN API suport for NUCLEO_F091RC target.
*stm32f091xc.h* file was changed to avoid compilation errors.
Change-Id: I9207575a0e2ad0f8e3a4bb78eb23d1e7b4a94171
we changed the sequence of ROM section to "<ro code> <ro data>" when compiled with the IAR.
When the ROM area is large, PC could not jump properly in the program area.
The other development environment of this sequence ("ro code, ro data").
https://github.com/mbedmicro/mbed/pull/1702
In this PR, rtx has updated, the macro into the code were changed.
However, by this macro, the process of task generation in Cortex-A9 can no longer be run.
So, we solve the task generation problem by changing the macro into Tread.cpp again.
* [STM32F4] Get PCLK1 clock and set initial CAN frequency
CAN bus opperates on APB1 peripheral clock due to that we need to get PCLK1 freq
in *can_frequency()* function to properly calculate CAN speed and reconfigure
BS1, BS2, SJW bits.
Also to fully communicate with other ST platform we set the initical CAN
frequency to 100kb/s to be able to work with the slowest platform which supports
CAN, which is NUCLEO_F303K8 (APB1 is 32MHz).
Change-Id: I10af3aa8d715dd61c9d1b216ef813193449fecbd
* [STM32F4] Fix for CAN2 interrupt index
CAN2 interrupt index was wrong leading to not properly registering interrupt.
Having this fix allow us to pass MBED_30 test.
Change-Id: I33f9ca7c81286f7746a8f8352619e213bdf9756a
With PR #1707 all STM32F4 targets with UART4 and UART5 are broken, a several typos in function definition.
Seems to be a bug in STM32Fcube HAL, not only in the (older) mbed versin but also in current version
* [STM32F1 F4] Fix#1705 MBED_37
The transmit data register needs to be flushed at the initialisation of
the uart.
In case previous transmission was interrupted by a uart init, uart may
contain a char that will be transmitted at the next start.
This is the case in MBED_37 test (serial_auto_nc_rx).
The MCU is writting {{start}}\n
At the moment of the \n the main program is handling 'new serial'. The
next time the main program is handling a printf, the previous \n is
still present in the uart->DR register and is transmitted.
This cannot happen anymore with this commit
* [STM32_F1] Fix#1705 MBED_37 by resetting the uart
This causing a warning in the rt_cmsis.c, as they use preprocessor
to redefine a type. A fix is to move the macro above, as it should not
change anything else. This should be removed, and use a cast, however I am
not fully familiar why they do this macro trick.
2 new macros were introduced to capture changes in the kernel. We used toolchains/__init__
script to capture those, which is not in the sync with actual sources. This fix introduces
those macros in the source, rather than a script.
We will further eliminate those macros to be used outside of RTX kernel (c++ API).
This enables the stack info methods to be supported for Cortex-M
targets. The rt_TypeDef required one small change - rename new structure
member as this is a reserved keyword in C++.
We need to ask for tid everytime we need to use tcb, do not expose internal
RTX details, we keep it within Thread.cpp file.
Cherry pick commit d587474778 -
"RTX: Support stacks larger than 64k"
This allows the latest version of the RTOS to run mbed client over
ethernet without crashing.
Thread - stack methods are not available for now, as tcb pointer was removed from
internal structure. To obtain it, we could get it from the kernel, but this should be
reconsidered. Either RTOS should provide it, or these methods will become deprecated.
Changes to the original kernel:
Cortex-M requires to define __CMSIS_OS_RTX, and __MBED_CMSIS_RTOS_CM. The macro __MBED_CMSIS_RTOS_CM
is mbed specific macro, to track changes to the kernel. This should keep us aware what has changed. For instance,
one breaking change was thread adding instances variable, which were not in mbed. This can be find as
it's protected via __MBED_CMSIS_RTOS_CM ifdef.
```
// added for mbed compatibility
// original RTX code
```
Startup for toolchains - mbed defines own stack pointer (set_main_stack()), therefore it should be called in the startup.
IAR added low level init calls and dynamic intialization to the IAR startup. All defined in RTX_CM_lib.h.
The timer thread has task id 0x01, main task 0x02. There are exception for main task not to check for
overflows. This is mbed specific, was reapplied from mbed code base.
IAR fixed SVC calls, this fix had to be reapplied (repo mbed PR 736 for more information).
There are 28 filter banks which are shared between CAN1 and CAN2. By default
they are divided in half:
* CAN1 -> 0 ... 13
* CAN2 -> 14 ... 27
that's why we need to decied which filter number has to be chosen.
Change-Id: If5f0da035c1435c61d4748b12d6617e9005cfd83
For some reason STACKHEAP block was placed in SRAM2 section which lead to
*Error[Lp011]: section placement failed - unable to allocate space for sections/
block* error. This patch modifies the STM32L4 linker script and places STACKHEAP
into SRAM1 section which was previously unused.
Change-Id: Ibe6ca52a9fe7af232a3eade2f6b1f2ce28c9bd49
Introducing the prescaler management allows a wider period range support,
from about 65ms before now up to about 32s. We're also introducing
asserts in case the period or prescaler is truncated as the HW registers
are 16 bits large.
Sam Grove
Erwan GOURIOU
Laurent Meunier
Brian Daniels
svastm
Martin Kojtal
Russ Butler
Christopher Haster
Vincent Coubard
Bartosz Szczepanski
Steven Cooreman
Anders Lindvall
Mihail Stoyanov
Mihail Stoyanov
Mahadevan Mahesh
TomoYamanaka
ohagendorf
adustm
bcostm
neilt6
Helmut Tschemernjak
adustm
Mahadevan Mahesh-R9AADQ