Generalized handling of dns servers when brought up with both ipv4 and
ipv6 addresses. Falls back to google dns servers if not dns server is
found through dhcp.
Also added support for the `add_dns_server` method to lwip to support
custom servers.
depending on timing and HW, there might be some delay before the master
request gets notified, so better loop in while than a single call
to slave.receive()
STM32 supported targets have 2 possible versions of I2C.
This patch makes the start / stop / read and write byte work ok for IP V2.
This was not working before and does not seem to be widely used.
PR to update RTX to v4.80 for Cortex-A.
In the latest CI test, three tests result in an error. The cause is mainly three points
- Unsupport RTX v4.80 for Cortex-A
- Insufficient stack size of thread defined in test
- A few Lack of Malloc API in GCC
Therefore, I supported to these. For the stack size for test, @c1728p9 already supported in PR #3362.
Reference for issue of test error is here.
https://github.com/ARMmbed/mbed-os/issues/3273
Reference for PR to update RTX for Cortex-M.
https://github.com/ARMmbed/mbed-os/pull/1702
PR to update RTX to v4.80 for Cortex-A.
In the latest CI test, three tests result in an error. The cause is mainly three points
- Unsupport RTX v4.80 for Cortex-A
- Insufficient stack size of thread defined in test
- A few Lack of Malloc API in GCC
Therefore, I supported to these. For the stack size for test, @Russ already supported in PR #3362.
Reference for issue of test error is here.
https://github.com/ARMmbed/mbed-os/issues/3273
Reference for PR to update RTX for Cortex-M.
https://github.com/ARMmbed/mbed-os/pull/1702
1. Add targets into build_travis.py and tests.py.
2. Add target SPI pins into SPI SD test samples.
3. Rename target TOOLCHAIN_GCC_ARM/retarget.c to avoid name collision of compiled retarget.o with platform/retargets.cpp.
This change was spurred by a confusing error. I attempted to compile for
the RZ_A1H (a Cortex-A device), and I had the standalone ARM compiler in
my system path, which supports Cortex-A. However, the default path for
the ARM compiler in settings.py uses a Keil installation, which only
supports Cortex-M. It found my Keil installation and used that instead.
This change proposes to remove this default behavior and instead
requires the user to explicitly set the intended compiler, either by a
settings file, mbed CLI, environment variables, or by placing the
compiler in your PATH.
Previously, the RTOS threads test was conditionally change the thread
stack size for all test cases based on the target. Now, it uses the
default stack size for all targets when threads are created serially,
and uses a 512 byte stack for the threads that are created in parallel.
To allow a network stack to support both NSAPI and its own options, try to make
sure the NSAPI levels don't collide with level numbers likely to be used by
network stacks.
Distinguish between socket and stack options, and tighten up documentation. Add
IP MRU stack options as an example (implementation not immediately planned for
any stack, but could be useful).
A few new error codes are added to nsapi_error_t and
support for non-blocking socket connect is added.
Nanostack's connect call will be non-blocking.
Whereas LWIP connect call is currently blocking, and it could be changed now
to be non-blocking.
Brian Daniels
Franz Schnyder
Christopher Haster
ccli8
bcostm
Richard Lin
Adrien Chardon
Laurent MEUNIER
tomoyuki yamanaka
Martin Kojtal
Anna Bridge
Mahadevan Mahesh
Jaakko Kukkohovi
Bartek Szatkowski
Jimmy Brisson
Amanda Butler
adustm
Sam Lin
Hasnain Virk
jeromecoutant