Any driver with attach or async API should be considered for deep sleep.
Add locking to those that require in most cases
high-frequency clocks:
- CAN
- I2C
- SPI
- Serial
- Ticker/Timeout/Timer
Sleep manager provides API to lock/unlock deepsleep. This API allows a user to
control deep sleep.
This API should be done via atomic operations (to be IRQ/thread safe).
If NVIC_NUM_VECTORS is larger than the space allocated by the vector
table in ram (__ram_vector_table_size__) then the call to mbed_cpy_nvic
during boot will corrupt valid data, which can lead to a crash. This
patch fixes the declared number of vectors on the KL27Z, KL43Z and
KL82Z to fix this crash.
To allow components with a simple need to schedule a few events to not
have to create their own threads, with all the associated memory
overhead, add 2 central calls to get shared normal and an
interrupt-deferral event queues, each dispatched on their own shared
threads.
For non-RTOS systems, just the normal event queue is provided, and the
application would have to dispatch this itself. This
application-dispatch is also available via a config option, to
potentially save memory by reusing the main thread.
Possible future improvement: the ability for separate components to
request a minimum stack size, and have the JSON combine these requests.
(Analogous tooling has already been mooted for mbed TLS config options
like key size).
Update directory structure to include RTX for only cortex targets, and
for all cortex targets. This patch accomplishes this by moving mbed-os
specific RTX files and RTX itself into rtos/TARGET_CORTEX along with
removing TARGET_CORTEX_M from the RTX5 directory.
The old directory structure:
rtos/rtx5/<mbed-os specific RTX files>
rtos/rtx5/TARGET_CORTEX_M/*
rtos/rtx4/*
rtos/<mbed-os specific RTX files>
Is re-arranged to:
rtos/TARGET_CORTEX/rtx5/*
rtos/TARGET_CORTEX/rtx4/*
rtos/TARGET_CORTEX/<mbed-os specific rtx files>
This both encapsulates RTX code more cleanly and makes it easier to
experiment with non-cortex cmsis-os2 backends, such as a posix
based cmsis-os2 backend.
Note - A potentially better name for the CORTEX_M directory would be
something like FEATURE_RTX5 since this directory only contains RTX5
related files. This cannot be done because there is not an easy way
to turn this feature on, since it cannot be done from mbed_lib.json.
In case the target supports a page size of 1 byte, i.e. is able to
program flash 1 byte at a time, which is the case of STM32 F4 targets,
there is no reason for flash_device.program to return an error when
trying to write on an "unaligned" address.
Adding flash API support to STM32F7 family. The code is derived from
F4 family one. The memory topology is described in flash_data.h files
and the flash_api.c implementation manages the 2 possible memory types (1
or 2 banks).
Users of FlashIAP usually get the minimum programable size
by calling flash.get_page_size(), so let's return the minimum
to allows a most efficient usage of flash.
For F4 devices, this is 1 byte.
For L0 and L1 devices, this is a word (4 bytes).
For L4 devices, this is a double word (8 bytes).
First add the flash_data.h that describe the flash memory topology,
and also activate FLASH support for the corresponding targets.
This is a 1,5MB flash memory device which contains 15 sectors, where
sectors 12 to 15 are 128KB sectors. So flash_api.c needed has been
updated to differentiate between this flash memory and the 2MB ones
by checking existence of sector 16 instead of sector 12.
Martin Kojtal
Russ Butler
Kevin Bracey
Antti Yli-Tokola
Deepika
Jimmy Brisson
Laurent MEUNIER
Christopher Haster
Shrikant Tudavekar
Arto Kinnunen