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13 Commits (e1d891b8582a02fb7746bad69a7dbfd479cac8e8)

Author SHA1 Message Date
ccli8 0c1098483f [NUC472/M487] Refine flow control code between crypto start and crypto ISR 2018-01-05 09:18:24 +08:00
ccli8 6464649c41 [NUC472/M487] Coordinate crypto interrupt handler among AES/PRNG 2018-01-05 09:18:20 +08:00
ccli8 d66074fecc [NUC472/M487] Coordinate crypto init among AES/DES/SHA/PRNG 
Add counter to track crypto init among crypto sub-modules. It includes:
1. Enable crypto clock
2. Enable crypto interrupt

As counter gets zero, crypto clock is disabled to save power.
 2018-01-05 09:18:18 +08:00
cyliangtw d8a9e35a0c [M487/NUC472] Refine trng_get_bytes for consistency and readability 2017-11-13 12:11:08 +08:00
cyliangtw 2ee058be53 [M487/NUC472] Refine for correctness control 2017-11-10 16:22:35 +08:00
cyliangtw e252b10148 [M487/NUC472] zeroize random data on the stack memory 2017-11-09 16:01:14 +08:00
cyliangtw 76c2c19853 [M487/NUC472] Unified code-path for remaining bytes of TRNG_Get 2017-11-08 19:56:12 +08:00
cyliangtw 4118afa259 [M487/NUC472] TRN_Get support 32 bytes unalignment 2017-11-08 14:23:05 +08:00
ccli8 99d12b1eb8 [M487] Fix compile warnings with GCC_ARM toolchain 2017-08-03 11:10:15 +08:00
ccli8 ed5ef0cc54 [M487] Refine coding style 2017-08-01 10:37:16 +08:00
ccli8 90e35febc1 [M487] Alpha support for real chip 
Real chip is incompatible with test chip due to change of pinout. From this on, test chip is unsupported.
 2017-08-01 10:23:43 +08:00
cyliangtw b91f064be7 [M487] Add CAN, AES and Eth 2017-08-01 10:18:54 +08:00
ccli8 98a79c872b [M487] Support NuMaker-PFM-M487 board 2017-08-01 10:14:24 +08:00