Add a pulse when using hardware chip select for SPI transmissions.
CS is at low level when a transmission is on-going.
Be careful, this is not compatible with all modes. It will work only
if PHA is 0, ie spi mode is 0 or 2. See stm32xx reference manual,
chapter "NSS pulse mode" for more details.
Fix#10671
Signed-off-by: Vincent Veron <vincent.veron@st.com>
The DEVICE_FOO macros are always defined (either 0 or 1).
This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
This patch handles the case of SPI slave mode without MISO (NC).
In case MISO is not connected, we consider that SPI will be configured in
3 wires mode (CLK / MOSI / CS, but no MISO). In this case, the MOSI line
is bi-directional : SPI_DIRECTION_1LINE.
But as this is not supported yet in slave mode, we force it to
SPI_DIRECTION_2LINES. In this case slave SPI will receive data on MOSI
but nothing will be sent back to master as MISO is not connected.
Enabling SPI causes the clock to be output by default.
Most devices will not care about extra clock cycles, especially as long
as chip select is not active, nevertheless this may cause side issues
with other devices especially during init phase.
This was actually the case with a 3 wire device (LPS22HB sensor).
In case MISO is not passed at SPI init, then we consider a 3 wires SPI
configuration is requested, which corresponds to SPI_DIRECTION_1LINE
configuration parameter in STM32 HAL layer.
We're then handling this specific case of SPI_DIRECTION_1LINE,
in spi_master_write or spi_master_block_write, we call to HAL API
This commit implements a SPI mode which will offer better performance
thanks to usage of Lower Layer API which use fewer registers access,
at the cost of lower robustness (no error management).
There is an easy default implementation of spi_master_block_write that
just calls spi_master_write in a loop, so the default implementation
of spi_master_block_write has been added to all targets.
Default timeout of 10ms was reported as an issue in #4300
There seems to be conditions or use cases where the system is loaded with
higher priority tasks so that SPI transfer would be delayed more than 10ms.
Recommendation from MBED team is to not implement any timeout at all as
there is no defined API in MBED to inform application of error cases.
In case the selected frequency is higher than the requested one, it is
better to send a debug warning rather than an blocking error.
In case of such warning, user may need to redefine the clock tree setting
at higher level (reducing peripheral's input clocks during init phase).
In case of prescaler_rank was 0, a -1 index was being used,
which resulted in initialization of the Init.BaudRatePrescaler with
random values.
Now let's better check index and avoid -1 operation, so that prescaler_rank
can be only from 0 to "last_index".
In case Rx is not initiliased its content might be random from stack.
This is causing problem in case of 8 bits read only as the left-side 8 bits
of the returned int value may contain this random byte data. This was for
instance detected when using SDFileSystem Lib.
ASYNCH SPI transfer support has been added based on STM HAL services.
To have both ASYNCH and SYNCH work together, we're also moving the
write API to STM HAL instead of direct registers access.
the SPI_ASYNCH feature has been already activated for STM32F4.
This patchset makes it supported on all STM32 families by:
- moving spi_s structure at family level instead of board level
- using the F4 spi_api.c reference implementation and making it a common
stm_spi_api.c file which makes maintenance a lot easier.
- the only part that needs to be implemented for each family is the computation
of the clock frequency input to the spi peripheral which is not the same
accross families. So this is what remains in the spi_api.c of each family.
Because of the introduction of the common file, all the above modifications
needs to be done at once.
int_szyk
Vincent Veron
jeromecoutant
Jarno Lamsa
Russ Butler
Martin Kojtal
Alastair D'Silva
bcostm
Paul Thompson
Laurent MEUNIER
mapellil
Deepika
Sam Grove
Martin Kojtal
Laurent MEUNIER