Three main issues:
1) The 0x13 special case section in write data in ncs36510_i2c.c didn't have a write++ command.
2) In the same write function, the WDAT8 command was put before the 0x13 section and this is not correct
3) Needed to add wait_us(0) before and after the register writes for apparent clock domain crossing delay times until registers are stable in HW
There were also a handful of other tweaks related to general code maintenance and moving some status register checks to the proper locations.
Changing this to none as result of build failures. Wifi needs own configuration
per an enviroment. By setting this to none, net tests are skipped for Realtek
platform.
TIMER2_7_IRQ is shared among several timer sources, including
us_ticker. Raising TIMER2_7_IRQ pending bit will trigger the timer
interrupt, but the timer interrupt handler will not know which timer
source this interrupt is for. This patch sets timer load value to one
tick and force us_ticker to fire almost "immediately".
TIMER2_7_IRQ is handled through a common interrupt handler, and
is automatically cleared. Therefore, there is no need to clear IRQ.
The underlying timer HAL treats load value as micro-seconds and does
conversion internally. Therefore, simply pass micro-seconds to timer
HAL without converting to tick first.
Signed-off-by: Tony Wu <tung7970@gmail.com>
Various RTOS classes were storing their CMSIS-RTOS creation attribute
structure as a member, when it's not required after construction. Reduce
memory by eliminating this member.
Cribbed from 4bf42f2e20
I'm not sure if if there are any copyright issues here with what is
effectively a set of config files. A few folks have been bugging me (and
the redbear folks) for these changes, so I wanted them somewhere
centralized.
uVisor doesn't set the PSP of the target thread. The RTOS sets the PSP
of the target thread from the target thread's TCB. However, when
interrupts of higher priority than PendSV happen between the call to
uVisor to switch boxes, and the RTOS setting PSP, the uVisor vIRQ
interrupt handler will attempt to use an invalid PSP (the PSP from
before the box and thread switch). This leads to a crash. Make box and
thread switching atomic by disabling interrupts immediately before the
box switching until immediately after the new PSP is set.
OsEventObserver objects expect a context to be maintained per thread on
their behalf. Add this context to the thread control block and extend
the thread creation functions with the ability to supply a context.
Marcus Chang
danclement
Martin Kojtal
Yuguo Zou
Tony Wu
Jimmy Brisson
Vincent Coubard
Laurent MEUNIER
Jammu Kekkonen
Maciej Bocianski
Kevin Bracey
jeromecoutant
Filip Jagodzinski
Russ Butler
Russ Butler
johnny
Boting Ren
Dave Wu
deepikabhavnani
Kevin Gilbert
Jaeden Amero