Allows clocking the device from RC oscillators (HFRCO, LFRCO).
Note that we can not use the em_cmu.h enums directly as the
preprocessor can not do comparisons on them.
Related changes in serial_api, so that LEUART clock is within
acceptable limits on Pearl.
Contains quite a bit of indentation changes to make the preprocessor
logic more readable so recommend viewing the diff in ignore whitespace
mode.
Keep a counter of sleeps blocked for every device, and do not try
to unblock sleep modes we did not block. This fixes problems where
serial events would cause EM1/EM2 to be unblocked too early,
causing the MCU to go to EM3 and not being able to wake up.
When initializing for use with the board controller, the LEUART must
be clocked from HF clock as the baud rate is otherwise too high.
Do this by first initializing to "standard" 9600, then call serial_baud
which will handle setting up the clocks and dividers.
Switch caused a phantom 0xFF frame to appear on the line when we switched
from LEUART to USART due to a baud rate was increase. This was short
enough that it was only visible at high (~115kbps) speeds.
As a fix, skip disabling the GPIO pins (as their configuration does not
change), and defer disabling the LEUART routing until at the very last
moment. Additionally, do not call serial_format, but immediately
initialize the UART to correct params.
- Do not attempt to disable the transmitter. Did not find a robust
way to do so - see comment in file for more info.
- Do not unblock sleep when abort is called externally, this leads
to jams as EM1 block gets disabled and the next sleep call places
the hardware to directly to EM3.
- Retain more status when switching over from LEUART to USART in
Pearl: keep registered IRQ handlers and other IRQ status.
Changed SPI implementation: #1 To avoid clearing data from buffers, during splitted DMA transfer
RX/TX buffer clear is done only when transfer is started.
USART transmit is completed instead of DMA/LDMA transfer completed.
When doing a large transfer over the LDMA it is required to wait TX to be completed
before transferring the next part of the data. Added a loop, to wait until TXC flag is set in function USART_STATUS_TXC.
+ minor code cleanup and EM1 sleep is allowed again.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Conditional when dispatching LEUART irq would always select the RX
side due to a bitwise AND being typoed as a logical AND.
Second, the TX interrupt was not cleared after processing, causing
it to stay in an infinite loop.
Previously, all pins in an mbed Port were set to the same value.
Use GPIO_PortOutSetVal to directly write the desired value to
the pins.
During port initialization the pin mode for input pins was set incorrectly.
Now, input pins are directly set to Input (gpioModeInput) and output pins to
PushPull (gpioModePushPull).
GPIO_IntEnable/Disable was called with incorrect params due
to missing parens. Operator precedence of & vs << caused the
call to be blank if the port (MSB) nibble of pin was not zero.
spi_buffer_tx_write fixed to work correctly with 9-16 bit frames,
if transfer length > 1. If frame is 9-16 bit client can use uint16_t or
uint32_t buffer for data storage, spi_api's default is to use uint16_t.
Added precompiler condition USE_UINT16_BUFFER to change assumption for
DMA and IRQ -transfers.
LDMA descriptor fixed to support 9-16 bit long frames. Prevented
sleepstate EM1, because USART requires EM0, and entering to EM1
during transfer can crash the system.
Previous comment on issuing a TXDIS command was incorrect. Actual
root cause was a non-DMA RX interrupt causing the code to run the
TXC handling code as long as the TX DMA interrupt had fired,
which was too early.
Reenable usage of TXDIS on Pearl.
Pearl STK is offically known as SLSTK3401A, but we well go
with the same naming convention as with Happy so Pearl's
name in Mbed will be STK3401.
Renames all files and directories that previously had the
placeholder STKXXXX. Build, target and export scripts
modified accordingly.
Serial HAL now allocates the LEUART first, and will switch
to using a standard UART only if the parameters require it.
Note that this switch can currently only happen one way, from
LEUART to USART. So once a higher baudrate or invalid frame
bit amount has been used, that instance of Serial object
will be locked to using an USART.
TODO: Parts of the UART (re)initialization code are now spread
between three places. They should be combined into single,
generic function.
Part of condition to detect active TX was not only incorrect
but also not needed in the first place. TX active state is
now always detected only via active TXBL/TXC interrupt.
UARTs are no longer fixed to certain pins on Pearl, so
we need to allocate them as needed, and allow for free
pin selection.
TX and RX pin locations in the main serial struct have been
separated, and pin routing modified accordingly.
serial_api_HAL.h interface keeps track of which UARTS are
currently in use, and provides alloc/free functions. Serial
and SPI components modified to use the new API.
TODO: Magic to support LEUART. This code will also need to
be able to dynamically switch from LEUART to standard USART
if the user later sets params (baud rate or format) that can
not be supported on LEUART.
Issuing a CLEARTX to LEUART command together or after TXEN caused
the DMA transfer to jam or cause repeated interrupts.
Also cleanup duplicated interrupt clears and add correct LEUART
branches when disabling RX/TX.
- Allow emlib to read the HFPER clock when initializing
USART. This corrects the baud rate on the serial line.
- Always use the TXC interrupt to signal when a transmission
is over when using (L)DMA. Removes a race condition
between flipping from TXBL to TXC, and TXC activating.
- With the previous change, serial_tx_active can now poll
the TXBL/TXC interrupts to see if a transmission is active.
previous code would fail in cases that the DMA transfer
had ended, but TX was still active, occasionally leading
to partial transfers when CLEARTX command was issued on
the next transfer.
- Add some sync points (SYNCBUSY poll) when twiddling around
LEUART registers.
Known issue: Using LEUART and DMA transfer on (at least) Leopard
causes the device to enter an infinite DMA interrupt loop.
When the requested timeout was not a integer multiple of the
LF clock tick the timestamp was set too short due to rounding,
sometimes causing the ticker event to be missed.
Steven Cooreman
Aksel Skauge Mellbye
Mikko Polojarvi
jhokajar