Change the lpspi default transfer delays to fix the data corruption
issue.
Add the loop and judgement to retry transfer when spi bus is busy.
Add the judgement statement to fix the hang issue.
Signed-off-by: TimWang <tim.wang@nxp.com>
For the application(firmware) booted by bootloader(OTA),
the image doesn't need the "flash_config" and "ivt" header.
So update the link file to support both kinds of application
(firmware) booted by bootROM and bootloader.
In default, the compilation will get the image with
"flash_config" and "ivt" header, for example the bootloader
compiling.
When compiling the OTA application image, please add the
line as below in the mbed_app.json file.
"target.macros_add" : ["MBED_APP_COMPILE"]
This will remove the "flash_config" and "ivt" header in the
final image.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
Update the flash driver to support both Hyper Flash
and QSPI Flash.
In addition, the static function cannot be linked to
SRAM even defined by AT_QUICKACCESS_SECTION_CODE macro.
So remove all "static" modifier for the FLASHIAP
functions.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
The memset function from c library will be linked in flash
space, it's risk for FLASHIAP. So I wrote flexspi_memset
to replace the memset for IMX FLASHIAP, and put the function
into targets/.../TARGET_IMX/flash_api.c file. All IMX Soc
platforms can declare it as extern and use in their Soc
flexspi driver files.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
The flash access may fail when implementing flash
initialization. So there is risk for interrupt handler
which linked in flash space.
Add the critical section to avoid the risk.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
NXP MIMXRT1050 EVK can support Hyper Flash or QSPI Flash with
small hardware reworks. Modify the XIP file to support boot
from the two kinds of Flash device. The Hyper Flash should be
the default device and defined in tartgets.json with the macro
"HYPERFLASH_BOOT". To select the QSPI Flash, just remove the
macro with the below line in any overriding json file.
"target.macros_remove" : ["HYPERFLASH_BOOT"]
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
- Update psoc6pdl to version 1.4.1.2240
- Update psoc6 core_lib to version 1.1.1.11109.
- Update psoc6hal to 1.1.1.11145.
- Store RTC century and RTC state information in persistent BREG register.
- Remove CY8CMOD_062_4343W and merge into CY8CPROTO_062_4343W.
- Remove CY8CMOD_062S2_43012 and merge into CY8CKIT_062S2_43012.
- Remove CY8CMOD_062S3_4343W and merge into CY8CPROTO_062S3_4343W.
- Removed CY8CMODs from targets.json.
- Removed unnecessary PSOC6Code.complete post binary hook from cypress targets.
- Remove wounding for the hardware CRYPTO block. The PSoC 6 MPN CYW9P62S1_43012EVB_01 was revised
to add the hardware crypto block.
- Add missing error checks for emac power up.
- Add a multiplied by 2 in the SDIO clock divider calculation to account for internal UDB divider.
Note: Fixes issues with intermittent WiFi firmware load failures on CY8CKIT_062_WIFI_BT,
CYW943012P6EVB_01, CYW9P62S1_43012EVB_01, CYW9P62S1_43438EVB_01.
Changed set_match api to use an absolute ticks rather than delayed tick to match api name.
Added api set_delay to delay by a specific amount of ticks. Removed unused set_time api.
Simplified the logic for computing interrupts match value for cascading counters.
Fixed an issue when incorrect base time would be read when trying to set match values.
1. Do not disable and enable osillators during deep sleep
entry and exit
2. Increase the deep sleep to pass tests
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The SDK header provides separate arrays for high and low
GPIO interrupts in place of the previous combined array
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. No need to copy RAM functions, this is done in the startup file
2. Update memory config for the FLASH section
3. Configure the PMIC_STDBY pin
4. Update UART clock setting
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>