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Revert "Backport #12603: Add CYSBSYSKIT_01" 

This reverts commit 4e6692b529.
There are issues with wifi connectivity on this target that mean
it is not ready to ship with 5.15.2.
pull/12780/head
Kyle Kearney 2020-04-08 14:14:11 -07:00
parent 757f14b807
commit 6554e3951e
46 changed files with 1 additions and 9242 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
View File

@ -69,8 +69,7 @@
defined(TARGET_CY8CPROTO_062S2_43012) || \
defined(TARGET_CY8CPROTO_062S3_4343W) || \
defined(TARGET_CYW943012P6EVB_01) || \
defined(TARGET_CYW9P62S1_43438EVB_01) || \
defined(TARGET_CYSBSYSKIT_01))
defined(TARGET_CYW9P62S1_43438EVB_01))
#include "S25FL512S_config.h"
#elif defined(TARGET_CYW9P62S1_43012EVB_01)

328
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp
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@ -1,328 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <cstring>
#include <algorithm>
#include <vector>
#include "SclSTAInterface.h"
#include "nsapi.h"
#include "lwipopts.h"
#include "lwip/etharp.h"
#include "lwip/ethip6.h"
#include "rtos.h"
#include "scl_emac.h"
#include "scl_ipc.h"
#include "mbed_wait_api.h"
/** @file
* Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects
*/
struct scl_tx_nw_credentials {
nsapi_security_t network_security_type;
int ssid_len;
int pass_len;
const char *network_ssid;
const char *network_passphrase;
} scl_tx_nw_credentials_t;
network_params_t network_parameter;
int scl_toerror(scl_result_t res)
{
switch (res) {
case SCL_SUCCESS:
return NSAPI_ERROR_OK;
case SCL_UNSUPPORTED:
return NSAPI_ERROR_UNSUPPORTED;
case SCL_BADARG:
return NSAPI_ERROR_PARAMETER;
case SCL_INVALID_JOIN_STATUS:
return NSAPI_ERROR_NO_CONNECTION;
case SCL_BUFFER_UNAVAILABLE_PERMANENT:
case SCL_BUFFER_UNAVAILABLE_TEMPORARY:
case SCL_RX_BUFFER_ALLOC_FAIL:
case SCL_BUFFER_ALLOC_FAIL:
case SCL_MALLOC_FAILURE:
return NSAPI_ERROR_NO_MEMORY;
case SCL_ACCESS_POINT_NOT_FOUND:
case SCL_NETWORK_NOT_FOUND:
return NSAPI_ERROR_NO_SSID;
case SCL_NOT_AUTHENTICATED:
case SCL_INVALID_KEY:
case SCL_NOT_KEYED:
return NSAPI_ERROR_AUTH_FAILURE;
case SCL_PENDING:
case SCL_JOIN_IN_PROGRESS:
return NSAPI_ERROR_IN_PROGRESS;
case SCL_CONNECTION_LOST:
return NSAPI_ERROR_CONNECTION_LOST;
case SCL_TIMEOUT:
case SCL_EAPOL_KEY_PACKET_M1_TIMEOUT:
case SCL_EAPOL_KEY_PACKET_M3_TIMEOUT:
case SCL_EAPOL_KEY_PACKET_G1_TIMEOUT:
return NSAPI_ERROR_CONNECTION_TIMEOUT;
default:
return -res;
}
}
nsapi_security_t scl_tosecurity(scl_security_t sec)
{
switch (sec) {
case SCL_SECURITY_OPEN:
return NSAPI_SECURITY_NONE;
case SCL_SECURITY_WEP_PSK:
case SCL_SECURITY_WEP_SHARED:
return NSAPI_SECURITY_WEP;
case SCL_SECURITY_WPA_TKIP_PSK:
case SCL_SECURITY_WPA_TKIP_ENT:
return NSAPI_SECURITY_WPA;
case SCL_SECURITY_WPA2_MIXED_PSK:
return NSAPI_SECURITY_WPA_WPA2;
case SCL_SECURITY_WPA2_AES_PSK:
case SCL_SECURITY_WPA2_AES_ENT:
case SCL_SECURITY_WPA2_FBT_PSK:
case SCL_SECURITY_WPA2_FBT_ENT:
return NSAPI_SECURITY_WPA2;
default:
return NSAPI_SECURITY_UNKNOWN;
}
}
scl_security_t scl_fromsecurity(nsapi_security_t sec)
{
switch (sec) {
case NSAPI_SECURITY_NONE:
return SCL_SECURITY_OPEN;
case NSAPI_SECURITY_WEP:
return SCL_SECURITY_WEP_PSK;
case NSAPI_SECURITY_WPA:
return SCL_SECURITY_WPA_MIXED_PSK;
case NSAPI_SECURITY_WPA2:
return SCL_SECURITY_WPA2_AES_PSK;
case NSAPI_SECURITY_WPA_WPA2:
return SCL_SECURITY_WPA2_MIXED_PSK;
default:
return SCL_SECURITY_UNKNOWN;
}
}
SclSTAInterface::SclSTAInterface(SCL_EMAC &emac, OnboardNetworkStack &stack)
: EMACInterface(emac, stack),
_ssid("\0"),
_pass("\0"),
_security(NSAPI_SECURITY_NONE),
_scl_emac(emac)
{
}
nsapi_error_t SclSTAInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel)
{
int err = set_channel(channel);
if (err) {
return err;
}
err = set_credentials(ssid, pass, security);
if (err) {
return err;
}
return connect();
}
nsapi_error_t SclSTAInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security)
{
if ((ssid == NULL) ||
(strlen(ssid) == 0) ||
(pass == NULL && (security != NSAPI_SECURITY_NONE)) ||
(strlen(pass) == 0 && (security != NSAPI_SECURITY_NONE)) ||
(strlen(pass) > 63 && (security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA || security == NSAPI_SECURITY_WPA_WPA2))
) {
return NSAPI_ERROR_PARAMETER;
}
memset(_ssid, 0, sizeof(_ssid));
strncpy(_ssid, ssid, sizeof(_ssid));
memset(_pass, 0, sizeof(_pass));
strncpy(_pass, pass, sizeof(_pass));
_security = security;
return NSAPI_ERROR_OK;
}
nsapi_error_t SclSTAInterface::connect()
{
uint32_t delay_timeout = 0;
scl_result_t ret_val;
nsapi_error_t interface_status;
uint32_t connection_status = 0;
scl_tx_nw_credentials_t.network_ssid = _ssid;
if (strlen(_ssid) < MAX_SSID_LENGTH) {
scl_tx_nw_credentials_t.ssid_len = strlen(_ssid);
}
scl_tx_nw_credentials_t.network_passphrase = _pass;
if (strlen(_pass) < MAX_PASSWORD_LENGTH) {
scl_tx_nw_credentials_t.pass_len = strlen(_pass);
}
scl_tx_nw_credentials_t.network_security_type = _security;
ret_val = scl_send_data(SCL_TX_CONNECT, (char *)&scl_tx_nw_credentials_t, TIMER_DEFAULT_VALUE);
if (ret_val == SCL_SUCCESS) {
SCL_LOG(("wifi provisioning in progress"));
}
network_parameter.connection_status = NSAPI_STATUS_DISCONNECTED;
//Get the network parameter from NP
while ((network_parameter.connection_status != NSAPI_STATUS_GLOBAL_UP) && delay_timeout < NW_CONNECT_TIMEOUT) {
ret_val = scl_get_nw_parameters(&network_parameter);
wait_us(NW_DELAY_TIME_US);
delay_timeout++;
}
if (delay_timeout >= NW_CONNECT_TIMEOUT || ret_val != SCL_SUCCESS) {
return NSAPI_ERROR_NO_CONNECTION;
}
if (!_scl_emac.powered_up) {
_scl_emac.power_up();
}
if (!_interface) {
nsapi_error_t err = _stack.add_ethernet_interface(_emac, true, &_interface);
if (err != NSAPI_ERROR_OK) {
_interface = NULL;
return err;
}
_interface->attach(_connection_status_cb);
}
if (!scl_wifi_is_ready_to_transceive()) {
scl_emac_wifi_link_state_changed(true);
}
interface_status = _interface->bringup(false,
network_parameter.ip_address,
network_parameter.netmask,
network_parameter.gateway,
DEFAULT_STACK);
scl_send_data(SCL_TX_CONNECTION_STATUS, (char *)&connection_status, TIMER_DEFAULT_VALUE);
return interface_status;
}
void SclSTAInterface::wifi_on()
{
if (!_scl_emac.powered_up) {
_scl_emac.power_up();
}
}
nsapi_error_t SclSTAInterface::disconnect()
{
scl_result_t ret_val;
nsapi_error_t disconnect_status;
ret_val = scl_send_data(SCL_TX_DISCONNECT, (char *)&disconnect_status, TIMER_DEFAULT_VALUE);
if (ret_val == SCL_ERROR) {
return NSAPI_ERROR_TIMEOUT;
}
if (!_interface) {
return NSAPI_STATUS_DISCONNECTED;
}
// bring down
int err = _interface->bringdown();
if (err) {
return err;
}
scl_emac_wifi_link_state_changed(false);
return NSAPI_ERROR_OK;
}
int SclSTAInterface::scan(WiFiAccessPoint *res, unsigned count)
{
/* To Do */
return NSAPI_ERROR_UNSUPPORTED;
}
int8_t SclSTAInterface::get_rssi()
{
int32_t rssi;
scl_result_t res;
if (!_scl_emac.powered_up) {
_scl_emac.power_up();
}
res = (scl_result_t) scl_wifi_get_rssi(&rssi);
if (res == SCL_ERROR) {
return SCL_ERROR;
}
return (int8_t)rssi;
}
int SclSTAInterface::is_interface_connected(void)
{
if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) {
return SCL_SUCCESS;
} else {
return SCL_CONNECTION_LOST;
}
}
int SclSTAInterface::get_bssid(uint8_t *bssid)
{
scl_mac_t ap_mac;
scl_result_t res = SCL_SUCCESS;
if (bssid == NULL) {
return SCL_BADARG;
}
memset(&ap_mac, 0, sizeof(ap_mac));
if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) {
res = (scl_result_t) scl_wifi_get_bssid(&ap_mac);
if (res == SCL_SUCCESS) {
memcpy(bssid, ap_mac.octet, sizeof(ap_mac.octet));
}
} else {
return SCL_CONNECTION_LOST;
}
return res;
}
int SclSTAInterface::wifi_set_up(void)
{
int res = SCL_SUCCESS;
res = scl_wifi_set_up();
return res;
}

165
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h
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@ -1,165 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SCL_STA_INTERFACE_H
#define SCL_STA_INTERFACE_H
/** @file
* Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects
*/
#include "netsocket/WiFiInterface.h"
#include "netsocket/EMACInterface.h"
#include "netsocket/OnboardNetworkStack.h"
#include "scl_emac.h"
#include "scl_wifi_api.h"
#include "scl_types.h"
#define MAX_SSID_LENGTH (33) /**< Maximum ssid length */
#define MAX_PASSWORD_LENGTH (64) /**< Maximum password length */
/** SclSTAInterface class
* Implementation of the Network Stack for the SCL
*/
class SclSTAInterface : public WiFiInterface, public EMACInterface {
public:
SclSTAInterface(
SCL_EMAC &emac = SCL_EMAC::get_instance(),
OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance());
/** Gets the current instance of the SclSTAInterface
*
* @return Pointer to the object of class SclSTAInterface.
*/
static SclSTAInterface *get_default_instance();
/** Turns on the Wi-Fi device
*
* @return void
*/
void wifi_on();
/** Starts the interface
*
* Attempts to connect to a Wi-Fi network. Requires ssid and passphrase to be set.
* If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned.
*
* @return 0 on success, negative error code on failure.
*/
nsapi_error_t connect();
/** Starts the interface
*
* Attempts to connect to a Wi-Fi network.
*
* @param ssid Name of the network to connect to.
* @param pass Security passphrase to connect to the network.
* @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE).
* @param channel This parameter is not supported, setting it to a value other than 0 will result in NSAPI_ERROR_UNSUPPORTED.
* @return 0 on success, negative error code on failure.
*/
nsapi_error_t connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0);
/** Disconnects the interface
*
* @return 0 on success, negative error code on failure.
*/
nsapi_error_t disconnect();
/** Set the Wi-Fi network credentials
*
* @param ssid Name of the network to connect to.
* @param pass Security passphrase to connect to the network.
* @param security Type of encryption for connection.
* (defaults to NSAPI_SECURITY_NONE)
* @return 0 on success, negative error code on failure.
*/
nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE);
/** Sets the Wi-Fi network channel - NOT SUPPORTED
*
* This function is not supported and will return NSAPI_ERROR_UNSUPPORTED.
*
* @param channel Channel on which the connection is to be made (Default: 0).
* @return Not supported, returns NSAPI_ERROR_UNSUPPORTED.
*/
nsapi_error_t set_channel(uint8_t channel)
{
if (channel != 0) {
return NSAPI_ERROR_UNSUPPORTED;
}
return 0;
}
/** Set blocking status of interface.
* Nonblocking mode is not supported.
*
* @param blocking True if connect is blocking
* @return 0 on success, negative error code on failure
*/
nsapi_error_t set_blocking(bool blocking)
{
if (blocking) {
_blocking = blocking;
return NSAPI_ERROR_OK;
} else {
return NSAPI_ERROR_UNSUPPORTED;
}
}
/** Gets the current radio signal strength for active connection
*
* @return Connection strength in dBm (negative value).
*/
int8_t get_rssi();
/** Scans for available networks - NOT SUPPORTED
*
* @return NSAPI_ERROR_UNSUPPORTED
*/
int scan(WiFiAccessPoint *res, unsigned count);
/** This function is used to indicate if the device is connected to the network.
*
* @return SCL_SUCCESS if device is connected.
*/
int is_interface_connected();
/** Gets the BSSID (MAC address of device connected to).
*
* @param bssid Pointer to the BSSID value.
* @return SCL_SUCCESS if BSSID is obtained successfully.
* @return SCL_BADARG if input parameter is NULL.
* @return SCL_ERROR if unable to fetch BSSID.
*/
int get_bssid(uint8_t *bssid);
/** This function is used to set up the Wi-Fi interface.
* This function should be used after the wifi_on.
*
* @return SCL_SUCCESS if the Wi-Fi interface is set up successfully.
*/
int wifi_set_up(void);
private:
char _ssid[MAX_SSID_LENGTH]; /**< The longest possible name (defined in 802.11) +1 for the \0 */
char _pass[MAX_PASSWORD_LENGTH]; /**< The longest allowed passphrase + 1 */
nsapi_security_t _security; /**< Security type */
SCL_EMAC &_scl_emac; /**< SCL_EMAC object */
};
#endif /* ifndef SCL_STA_INTERFACE_H */

35
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp
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@ -1,35 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "SclSTAInterface.h"
/** @file
* Provides function definition to override get_target_default_intance of WiFiInterface and NetworkInterface classes
*/
/**
* Returns the WiFiInterface Object
* This function can be called using WiFiInterface or NetworkInterface objects
*
* @return pointer to WiFiInterface object.
*/
WiFiInterface *WiFiInterface::get_target_default_instance()
{
static SclSTAInterface wifi;
return &wifi;
}

203
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp
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@ -1,203 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <ctype.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "cmsis_os.h"
#include "scl_emac.h"
#include "lwip/etharp.h"
#include "lwip/ethip6.h"
#include "mbed_shared_queues.h"
#include "scl_buffer_api.h"
#include "cy_result.h"
#include "cy_pdl.h"
#include "scl_ipc.h"
/** @file
* Provides EMAC interface functions to be used with the SCL_EMAC object
*/
SCL_EMAC::SCL_EMAC(scl_interface_role_t role)
: interface_type(role)
{
}
SCL_EMAC::SCL_EMAC()
: interface_type(SCL_STA_ROLE)
{
}
SCL_EMAC &SCL_EMAC::get_instance()
{
return get_instance(SCL_STA_ROLE);
}
SCL_EMAC &SCL_EMAC::get_instance(scl_interface_role_t role)
{
static SCL_EMAC emac_sta(SCL_STA_ROLE);
static SCL_EMAC emac_ap(SCL_AP_ROLE);
return role == SCL_AP_ROLE ? emac_ap : emac_sta;
}
uint32_t SCL_EMAC::get_mtu_size() const
{
return SCL_PAYLOAD_MTU;
}
uint32_t SCL_EMAC::get_align_preference() const
{
return 0;
}
void SCL_EMAC::add_multicast_group(const uint8_t *addr)
{
memcpy(multicast_addr.octet, addr, sizeof(multicast_addr.octet));
scl_wifi_register_multicast_address(&multicast_addr);
}
void SCL_EMAC::remove_multicast_group(const uint8_t *address)
{
/* To Do */
}
void SCL_EMAC::set_all_multicast(bool all)
{
/* No-op at this stage */
}
void SCL_EMAC::power_down()
{
/* No-op at this stage */
}
bool SCL_EMAC::power_up()
{
if (!powered_up) {
if (scl_wifi_on() != true) {
SCL_LOG(("returning False in scl_wifi_on()\n"));
return false;
}
powered_up = true;
if (link_state && emac_link_state_cb) {
emac_link_state_cb(link_state);
}
}
return true;
}
bool SCL_EMAC::get_hwaddr(uint8_t *addr) const
{
scl_mac_t mac;
scl_result_t res = scl_wifi_get_mac_address(&mac);
if (res == SCL_SUCCESS) {
memcpy(addr, mac.octet, sizeof(mac.octet));
return true;
} else {
SCL_LOG(("return False in SCL_EMAC::gethwaddr\n"));
return false;
}
}
void SCL_EMAC::set_hwaddr(const uint8_t *addr)
{
/* No-op at this stage */
}
uint8_t SCL_EMAC::get_hwaddr_size() const
{
scl_mac_t mac;
return sizeof(mac.octet);
}
void SCL_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb)
{
emac_link_input_cb = input_cb;
}
void SCL_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb)
{
emac_link_state_cb = state_cb;
}
void SCL_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr)
{
memory_manager = &mem_mngr;
}
bool SCL_EMAC::link_out(emac_mem_buf_t *buf)
{
scl_result_t retval;
scl_tx_buf_t scl_tx_data;
scl_tx_data.size = memory_manager->get_total_len(buf);
scl_tx_data.buffer = buf;
if (buf == NULL) {
return false;
}
retval = scl_network_send_ethernet_data(scl_tx_data);
if (retval != SCL_SUCCESS) {
return false;
}
memory_manager->free(buf);
return true;
}
void SCL_EMAC::get_ifname(char *name, uint8_t size) const
{
if (name != NULL) {
memcpy(name, "scl", size);
}
}
void SCL_EMAC::set_activity_cb(mbed::Callback<void(bool)> cb)
{
activity_cb = cb;
}
extern "C"
{
void scl_network_process_ethernet_data(scl_buffer_t buffer)
{
emac_mem_buf_t *mem_buf = NULL;
SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE);
if (!emac.powered_up && !emac.emac_link_input_cb) {
scl_buffer_release(buffer, SCL_NETWORK_RX);
return;
}
mem_buf = buffer;
if (emac.activity_cb) {
emac.activity_cb(false);
}
emac.emac_link_input_cb(mem_buf);
}
void scl_emac_wifi_link_state_changed(bool state_up)
{
SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE);
emac.link_state = state_up;
if (emac.emac_link_state_cb) {
emac.emac_link_state_cb(state_up);
}
}
} // extern "C"

189
features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h
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@ -1,189 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SCL_EMAC_H_
#define SCL_EMAC_H_
/** @file
* Provides EMAC interface functions to be used with the SCL_EMAC object
*
*/
#include "EMAC.h"
#include "EMACInterface.h"
#include "WiFiInterface.h"
#include "scl_common.h"
#include "rtos/Semaphore.h"
#include "rtos/Mutex.h"
#include "scl_wifi_api.h"
class SCL_EMAC : public EMAC {
public:
SCL_EMAC();
SCL_EMAC(scl_interface_role_t itype);
/**
* Get the EMAC instance
*
* @return Reference to SCL_EMAC object.
*/
static SCL_EMAC &get_instance();
/**
* Get the EMAC instance
*
* @param role Interface type.
*
* @return Reference to SCL_EMAC object.
*/
static SCL_EMAC &get_instance(scl_interface_role_t role);
/**
* Returns the maximum transmission unit
*
* @return MTU in bytes.
*/
virtual uint32_t get_mtu_size() const;
/**
* Gets the memory buffer alignment preference
*
* Gets the preferred memory buffer alignment of the EMAC device. IP stack may or may not
* align with the link out memory buffer chains using the alignment.
*
* @return Memory alignment requirement in bytes.
*/
virtual uint32_t get_align_preference() const;
/**
* Returns the interface name
*
* @param name Pointer to the location where the name should be written.
* @param size Maximum number of characters to copy.
*/
virtual void get_ifname(char *name, uint8_t size) const;
/**
* Returns the size of the underlying interface HW address size.
*
* @return HW address size in bytes.
*/
virtual uint8_t get_hwaddr_size() const;
/**
* Returns the interface supplied HW address
* Copies the HW address to the provided memory
* @param addr HW address of the underlying interface. It must be of correct size. See @a get_hwaddr_size.
* @return True if HW address is available.
*/
virtual bool get_hwaddr(uint8_t *addr) const;
/**
* Set HW address for the interface
*
* Provided address must be of correct size. See @a get_hwaddr_size.
*
* Called to set the MAC address to be used - if @a get_hwaddr is provided
* the stack would normally use that, but it could be overridden for test
* purposes.
*
* @param addr Address to be set
*/
virtual void set_hwaddr(const uint8_t *addr);
/**
* Sends the packet over the link
*
* This cannot be called from an interrupt context.
*
* @param buf Packet to be sent.
* @return True if the packet was sent successfully. False otherwise.
*/
virtual bool link_out(emac_mem_buf_t *buf);
/**
* Initializes the HW
*
* @return True on success. False in case of an error.
*/
virtual bool power_up();
/**
* De-initializes the HW
*/
virtual void power_down();
/**
* Sets a callback that is called for packets received for a given interface
*
* @param input_cb Function to be registered as a callback.
*/
virtual void set_link_input_cb(emac_link_input_cb_t input_cb);
/**
* Sets a callback that is called on changes in the link status for a given interface
*
* @param state_cb Function to be registered as a callback.
*/
virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb);
/** Adds a device to a multicast group
*
* @param address A multicast group hardware address.
*/
virtual void add_multicast_group(const uint8_t *address);
/** Removes a device from a multicast group
*
* @param address A multicast group hardware address.
*/
virtual void remove_multicast_group(const uint8_t *address);
/** Requests reception of all multicast packets
*
* @param all True to receive all multicasts.
* False to receive only multicasts addressed to specified groups.
*/
virtual void set_all_multicast(bool all);
/** Sets memory manager used to handle memory buffers
*
* @param mem_mngr Pointer to memory manager.
*/
virtual void set_memory_manager(EMACMemoryManager &mem_mngr);
/** Sets callback to receive EMAC activity events
*
* @param activity_cb The callback for activity events.
*/
virtual void set_activity_cb(mbed::Callback<void(bool is_tx_activity)> activity_cb);
emac_link_input_cb_t emac_link_input_cb = NULL; /**< Callback for incoming data */
emac_link_state_change_cb_t emac_link_state_cb = NULL; /**< Callback for network connection status */
EMACMemoryManager *memory_manager; /**< Pointer to hold memory manager object */
bool powered_up = false; /**< Flag for Wi-Fi power on status */
bool link_state = false; /**< Flag for network connection status */
scl_interface_role_t interface_type; /**< Type of the interface */
scl_mac_t multicast_addr; /**< Multicast address */
mbed::Callback<void(bool)> activity_cb; /**< Callback for activity on network */
};
/** Sends the change in network connection state to network stack
*
* @param state_up Connection status.
*/
extern "C" void scl_emac_wifi_link_state_changed(bool state_up);
#endif /* SCL_EMAC_H_ */

3
features/netsocket/ppp/mbed_lib.json
View File

@ -47,9 +47,6 @@
},
"CY8CKIT_062S2_43012": {
"thread-stacksize": 896
},
"CYSBSYSKIT_01": {
"thread-stacksize": 896
}
}
}

9
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt
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@ -1,9 +0,0 @@
/*
* This file is used to set the MAC address in NVRAM.
* The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM.
* If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used.
* PSOC boards are usually programmed with OTP MAC address.
* MAC address is printed during SCL power up
*/
#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:45:2e:c8"

211
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h
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@ -1,211 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** @file scl_common.h
* Defines common data types used in SCL
*/
#include <stdint.h>
#include "cy_result.h"
#ifndef INCLUDED_SCL_COMMON_H_
#define INCLUDED_SCL_COMMON_H_
#ifdef __cplusplus
extern "C"
{
#endif
/******************************************************
* Constants
******************************************************/
#define SCL_LOG_ENABLE false /**< Flag to enable SCL debug logs */
#define SCL_LOG(x) if (SCL_LOG_ENABLE) \
{ printf x; } /**< SCL log interface */
#define CHECK_BUFFER_NULL(buf) if (buf == NULL)\
{ SCL_LOG(("Buffer pointer is null\n")); \
return SCL_BADARG; } /**< Helper macro to check if the input buffer pointer is null */
#define MODULE_BASE_CODE (0x0080U) /**< Base code for the SCL error status */
#define SCL_RESULT_TYPE (0) /**< SCL Result type */
/*
* scl_result_t Error code format
* |31-18 (14 bit) for module id|17-16 (2 bit) for result type|15-0 for SCL Error code|
* for example, for Error code 1026, the result of SCL_RESULT_CREATE is 33555458.
*/
#define SCL_RESULT_CREATE(x) CY_RSLT_CREATE(SCL_RESULT_TYPE, MODULE_BASE_CODE, (x) ) /**< Create a result value from the specified type, module, and result code */
#define SCL_SUCCESS (0) /**< IPC success */
#define SCL_ERROR (100) /**< IPC error */
#define SCL_PENDING SCL_RESULT_CREATE(1) /**< IPC Pending */
#define SCL_TIMEOUT SCL_RESULT_CREATE(2) /**< Timeout */
#define SCL_BADARG SCL_RESULT_CREATE(5) /**< Bad Arguments */
#define SCL_UNFINISHED SCL_RESULT_CREATE(10) /**< Operation not finished yet (maybe aborted) */
#define SCL_PARTIAL_RESULTS SCL_RESULT_CREATE(1003) /**< Partial results */
#define SCL_INVALID_KEY SCL_RESULT_CREATE(1004) /**< Invalid key */
#define SCL_DOES_NOT_EXIST SCL_RESULT_CREATE(1005) /**< Does not exist */
#define SCL_NOT_AUTHENTICATED SCL_RESULT_CREATE(1006) /**< Not authenticated */
#define SCL_NOT_KEYED SCL_RESULT_CREATE(1007) /**< Not keyed */
#define SCL_IOCTL_FAIL SCL_RESULT_CREATE(1008) /**< IOCTL fail */
#define SCL_BUFFER_UNAVAILABLE_TEMPORARY SCL_RESULT_CREATE(1009) /**< Buffer unavailable temporarily */
#define SCL_BUFFER_UNAVAILABLE_PERMANENT SCL_RESULT_CREATE(1010) /**< Buffer unavailable permanently */
#define SCL_CONNECTION_LOST SCL_RESULT_CREATE(1012) /**< Connection lost */
#define SCL_OUT_OF_EVENT_HANDLER_SPACE SCL_RESULT_CREATE(1013) /**< Cannot add extra event handler */
#define SCL_SEMAPHORE_ERROR SCL_RESULT_CREATE(1014) /**< Error manipulating a semaphore */
#define SCL_FLOW_CONTROLLED SCL_RESULT_CREATE(1015) /**< Packet retrieval cancelled due to flow control */
#define SCL_NO_CREDITS SCL_RESULT_CREATE(1016) /**< Packet retrieval cancelled due to lack of bus credits */
#define SCL_NO_PACKET_TO_SEND SCL_RESULT_CREATE(1017) /**< Packet retrieval cancelled due to no pending packets */
#define SCL_CORE_CLOCK_NOT_ENABLED SCL_RESULT_CREATE(1018) /**< Core disabled due to no clock */
#define SCL_CORE_IN_RESET SCL_RESULT_CREATE(1019) /**< Core disabled - in reset */
#define SCL_UNSUPPORTED SCL_RESULT_CREATE(1020) /**< Unsupported function */
#define SCL_BUS_WRITE_REGISTER_ERROR SCL_RESULT_CREATE(1021) /**< Error writing to WLAN register */
#define SCL_SDIO_BUS_UP_FAIL SCL_RESULT_CREATE(1022) /**< SDIO bus failed to come up */
#define SCL_JOIN_IN_PROGRESS SCL_RESULT_CREATE(1023) /**< Join not finished yet */
#define SCL_NETWORK_NOT_FOUND SCL_RESULT_CREATE(1024) /**< Specified network was not found */
#define SCL_INVALID_JOIN_STATUS SCL_RESULT_CREATE(1025) /**< Join status error */
#define SCL_UNKNOWN_INTERFACE SCL_RESULT_CREATE(1026) /**< Unknown interface specified */
#define SCL_SDIO_RX_FAIL SCL_RESULT_CREATE(1027) /**< Error during SDIO receive */
#define SCL_HWTAG_MISMATCH SCL_RESULT_CREATE(1028) /**< Hardware tag header corrupt */
#define SCL_RX_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1029) /**< Failed to allocate a buffer to receive into */
#define SCL_BUS_READ_REGISTER_ERROR SCL_RESULT_CREATE(1030) /**< Error reading a bus hardware register */
#define SCL_THREAD_CREATE_FAILED SCL_RESULT_CREATE(1031) /**< Failed to create a new thread */
#define SCL_QUEUE_ERROR SCL_RESULT_CREATE(1032) /**< Error manipulating a queue */
#define SCL_BUFFER_POINTER_MOVE_ERROR SCL_RESULT_CREATE(1033) /**< Error moving the current pointer of a packet buffer */
#define SCL_BUFFER_SIZE_SET_ERROR SCL_RESULT_CREATE(1034) /**< Error setting size of packet buffer */
#define SCL_THREAD_STACK_NULL SCL_RESULT_CREATE(1035) /**< Null stack pointer passed when non null was required */
#define SCL_THREAD_DELETE_FAIL SCL_RESULT_CREATE(1036) /**< Error deleting a thread */
#define SCL_SLEEP_ERROR SCL_RESULT_CREATE(1037) /**< Error sleeping a thread */
#define SCL_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1038) /**< Failed to allocate a packet buffer */
#define SCL_NO_PACKET_TO_RECEIVE SCL_RESULT_CREATE(1039) /**< No Packets waiting to be received */
#define SCL_INTERFACE_NOT_UP SCL_RESULT_CREATE(1040) /**< Requested interface is not active */
#define SCL_DELAY_TOO_LONG SCL_RESULT_CREATE(1041) /**< Requested delay is too long */
#define SCL_INVALID_DUTY_CYCLE SCL_RESULT_CREATE(1042) /**< Duty cycle is outside limit 0 to 100 */
#define SCL_PMK_WRONG_LENGTH SCL_RESULT_CREATE(1043) /**< Returned pmk was the wrong length */
#define SCL_UNKNOWN_SECURITY_TYPE SCL_RESULT_CREATE(1044) /**< AP security type was unknown */
#define SCL_WEP_NOT_ALLOWED SCL_RESULT_CREATE(1045) /**< AP not allowed to use WEP - it is not secure - use Open instead */
#define SCL_WPA_KEYLEN_BAD SCL_RESULT_CREATE(1046) /**< WPA / WPA2 key length must be between 8 & 64 bytes */
#define SCL_FILTER_NOT_FOUND SCL_RESULT_CREATE(1047) /**< Specified filter id not found */
#define SCL_SPI_ID_READ_FAIL SCL_RESULT_CREATE(1048) /**< Failed to read 0xfeedbead SPI id from chip */
#define SCL_SPI_SIZE_MISMATCH SCL_RESULT_CREATE(1049) /**< Mismatch in sizes between SPI header and SDPCM header */
#define SCL_ADDRESS_ALREADY_REGISTERED SCL_RESULT_CREATE(1050) /**< Attempt to register a multicast address twice */
#define SCL_SDIO_RETRIES_EXCEEDED SCL_RESULT_CREATE(1051) /**< SDIO transfer failed too many times. */
#define SCL_NULL_PTR_ARG SCL_RESULT_CREATE(1052) /**< Null Pointer argument passed to function. */
#define SCL_THREAD_FINISH_FAIL SCL_RESULT_CREATE(1053) /**< Error deleting a thread */
#define SCL_WAIT_ABORTED SCL_RESULT_CREATE(1054) /**< Semaphore/mutex wait has been aborted */
#define SCL_SET_BLOCK_ACK_WINDOW_FAIL SCL_RESULT_CREATE(1055) /**< Failed to set block ack window */
#define SCL_DELAY_TOO_SHORT SCL_RESULT_CREATE(1056) /**< Requested delay is too short */
#define SCL_INVALID_INTERFACE SCL_RESULT_CREATE(1057) /**< Invalid interface provided */
#define SCL_WEP_KEYLEN_BAD SCL_RESULT_CREATE(1058) /**< WEP / WEP_SHARED key length must be 5 or 13 bytes */
#define SCL_HANDLER_ALREADY_REGISTERED SCL_RESULT_CREATE(1059) /**< EAPOL handler already registered */
#define SCL_AP_ALREADY_UP SCL_RESULT_CREATE(1060) /**< Soft AP or P2P group owner already up */
#define SCL_EAPOL_KEY_PACKET_M1_TIMEOUT SCL_RESULT_CREATE(1061) /**< Timeout occurred while waiting for EAPOL packet M1 from AP */
#define SCL_EAPOL_KEY_PACKET_M3_TIMEOUT SCL_RESULT_CREATE(1062) /**< Timeout occurred while waiting for EAPOL packet M3 from AP which may indicate incorrect WPA2/WPA passphrase */
#define SCL_EAPOL_KEY_PACKET_G1_TIMEOUT SCL_RESULT_CREATE(1063) /**< Timeout occurred while waiting for EAPOL packet G1 from AP */
#define SCL_EAPOL_KEY_FAILURE SCL_RESULT_CREATE(1064) /**< Unknown failure occurred during the EAPOL key handshake */
#define SCL_MALLOC_FAILURE SCL_RESULT_CREATE(1065) /**< Memory allocation failure */
#define SCL_ACCESS_POINT_NOT_FOUND SCL_RESULT_CREATE(1066) /**< Access point not found */
#define SCL_RTOS_ERROR SCL_RESULT_CREATE(1067) /**< RTOS operation failed */
#define SCL_CLM_BLOB_DLOAD_ERROR SCL_RESULT_CREATE(1068) /**< CLM blob download failed */
#define SCL_HAL_ERROR SCL_RESULT_CREATE(1069) /**< SCL HAL Error */
#define SCL_RTOS_STATIC_MEM_LIMIT SCL_RESULT_CREATE(1070) /**< Exceeding the RTOS static objects memory */
/* Application uses the following constants to allocate the buffer pool: */
#define BDC_HEADER_WITH_PAD 6 /**< BDC Header with padding 4 + 2 */
#define SCL_PAYLOAD_MTU (1500) /**< The maximum size, in bytes, of the data part of an Ethernet frame */
/******************************************************
* Type Definitions
******************************************************/
/**
* Typedef for SCL buffer pointer
*/
typedef void *scl_buffer_t;
/**
* Typedef for SCL result
*/
typedef uint32_t scl_result_t;
/******************************************************
* Structures and Enumerations
******************************************************/
/**
* Typedef for SCL boolean flags
*/
typedef enum {
SCL_FALSE = 0, /**< Boolean False */
SCL_TRUE = 1 /**< Boolean True */
} scl_bool_t;
/**
* Typedef for SCL interface roles
*/
typedef enum {
SCL_INVALID_ROLE = 0, /**< Invalid role */
SCL_STA_ROLE = 1, /**< STA or Client Interface */
SCL_AP_ROLE = 2, /**< softAP Interface */
SCL_P2P_ROLE = 3 /**< P2P Interface */
} scl_interface_role_t;
/**
* Typedef for SCL IPC receive index
*/
typedef enum {
SCL_RX_DATA = 0, /**< Received buffer */
SCL_RX_TEST_MSG = 1, /**< Test message */
SCL_RX_GET_BUFFER = 2, /**< Get the buffer */
SCL_RX_GET_CONNECTION_STATUS = 3 /**< Get the connection status */
} scl_ipc_rx_t;
/**
* Typedef for SCL IPC transmit index
*/
typedef enum {
SCL_TX_TEST_MSG = 1, /**< Test Message */
SCL_TX_WIFI_INIT = 2, /**< Initialize Wi-Fi */
SCL_TX_CONFIG_PARAMETERS = 3, /**< Configuration parameters */
SCL_TX_GET_MAC = 4, /**< Get MAC address */
SCL_TX_REGISTER_MULTICAST_ADDRESS = 5, /**< Register multicast address */
SCL_TX_SEND_OUT = 6, /**< Transmit buffer */
SCL_TX_TRANSCEIVE_READY = 7, /**< Wi-Fi transmit/receive ready */
SCL_TX_WIFI_ON = 8, /**< Wi-Fi on */
SCL_TX_WIFI_SET_UP = 9, /**< Wi-Fi setup */
SCL_TX_WIFI_NW_PARAM = 10, /**< Get network parameters */
SCL_TX_WIFI_GET_RSSI = 11, /**< Get RSSI */
SCL_TX_WIFI_GET_BSSID = 12, /**< Get BSSID */
SCL_TX_CONNECT = 13, /**< Wi-Fi connect */
SCL_TX_DISCONNECT = 14, /**< Wi-Fi disconnect */
SCL_TX_CONNECTION_STATUS = 15 /**< Transmit connection status */
} scl_ipc_tx_t;
/**
* Structure for storing a MAC address (Wi-Fi Media Access Control address).
*/
typedef struct {
uint8_t octet[6]; /**< Unique 6-byte MAC address */
} scl_mac_t;
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_SCL_COMMON_H_ */

120
targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h
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@ -1,120 +0,0 @@
/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** @file
* Provides SCL functionality to communicate with Network Processor
*/
#include "scl_common.h"
#include "cy_device.h"
#include "cy_sysint.h"
#include "cy_ipc_drv.h"
#include "scl_wifi_api.h"
#include "ip4_addr.h"
#ifndef INCLUDED_SCL_IPC_H
#define INCLUDED_SCL_IPC_H
#ifdef __cplusplus
extern "C"
{
#endif
/******************************************************
* Macros
******************************************************/
/**
* Hardware address of IPC_DATA0 register
*/
#define REG_IPC_STRUCT_DATA0(base) (((IPC_STRUCT_V2_Type*)(base))->DATA0)
/**
* Default timeout value (in ms) for SCL operations
*/
#define TIMER_DEFAULT_VALUE (100)
/**
* Default timeout value (in ms) for Wi-Fi on
*/
#define WIFI_ON_TIMEOUT (5000)
/**
* Default timeout value (in seconds) for Wi-Fi connection
*/
#define NW_CONNECT_TIMEOUT (30)
/**
* Default interval (in micro seconds) for polling the Network Processor
*/
#define NW_DELAY_TIME_US (3000000)
/**
* Default parameter length
*/
#define PARAM_LEN (20)
/******************************************************
* Variables
******************************************************/
/**
* Network parameters structure.
*/
typedef struct network_params {
char ip_address[PARAM_LEN]; /**< IP address */
char netmask[PARAM_LEN]; /**< Netmask */
char gateway[PARAM_LEN]; /**< Gateway */
int connection_status; /**< Connection status */
} network_params_t;
/******************************************************
* Function Declarations
******************************************************/
/** @addtogroup communication SCL communication API
* APIs for communicating with Network Processor
* @{
*/
/** Initializes the SCL thread and necessary artifacts
*
* @return SCL_SUCCESS on successful initialization or SCL_ERROR otherwise
*/
extern scl_result_t scl_init(void);
/** Sends the SCL data and respective command to Network Processor
*
* @param index Index of the command.
* @param buffer Data to be sent.
* @param timeout The maximum time (in ms) to wait for the Network Processor to release IPC channel.
*
* @return SCL_SUCCESS on successful communication within SCL timeout duration or SCL_ERROR
*/
extern scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout);
/** Terminates the SCL thread and disables the interrupts
*
* @return SCL_SUCCESS on successful termination of SCL thread and disabling of interrupts or SCL_ERROR on timeout
*/
extern scl_result_t scl_end(void);
/** Gets the network parameters like IP Address, Netmask, and Gateway from Network Processor
*
* @param nw_param structure pointer of type @a network_params_t
*
* @return SCL_SUCCESS on successful communication or SCL_ERROR
*/
extern scl_result_t scl_get_nw_parameters(network_params_t *nw_param);
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_SCL_IPC_H */

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targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h
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/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** @file scl_types.h
* Defines common data types used in SCL
*
*/
#include <stdint.h>
#include "cy_result.h"
#ifndef INCLUDED_SCL_TYPES_H_
#define INCLUDED_SCL_TYPES_H_
#ifdef __cplusplus
extern "C"
{
#endif
/******************************************************
* Macros
******************************************************/
#define SSID_NAME_SIZE (32) /**< SSID Length */
#define WEP_ENABLED 0x0001 /**< Flag to enable WEP Security */
#define TKIP_ENABLED 0x0002 /**< Flag to enable TKIP Encryption */
#define AES_ENABLED 0x0004 /**< Flag to enable AES Encryption */
#define SHARED_ENABLED 0x00008000 /**< Flag to enable Shared key Security */
#define WPA_SECURITY 0x00200000 /**< Flag to enable WPA Security */
#define WPA2_SECURITY 0x00400000 /**< Flag to enable WPA2 Security */
#define WPA3_SECURITY 0x01000000 /**< Flag to enable WPA3 PSK Security */
#define ENTERPRISE_ENABLED 0x02000000 /**< Flag to enable Enterprise Security */
#define WPS_ENABLED 0x10000000 /**< Flag to enable WPS Security */
#define IBSS_ENABLED 0x20000000 /**< Flag to enable IBSS mode */
#define FBT_ENABLED 0x40000000 /**< Flag to enable FBT */
#define NO_POWERSAVE_MODE (0) /**< No Power save mode */
#define PM1_POWERSAVE_MODE (1) /**< Power save mode on specified interface without regard for throughput reduction */
#define PM2_POWERSAVE_MODE (2) /**< Power save mode on specified interface with High throughput */
/**
* Suppresses unused parameter warning
*/
#define UNUSED_PARAMETER(x) ( (void)(x) )
/**
* Suppresses unused variable warning
*/
#define UNUSED_VARIABLE(x) ( (void)(x) )
/**
* Suppresses unused variable warning that occurs due to an assert being disabled in release mode
*/
#define REFERENCE_DEBUG_ONLY_VARIABLE(x) ( (void)(x) )
/******************************************************
* Constants
******************************************************/
/******************************************************
* Structures and Enumerations
******************************************************/
/**
* Enumeration of Wi-Fi security modes
*/
typedef enum {
SCL_SECURITY_OPEN = 0, /**< Open security */
SCL_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP PSK Security with open authentication */
SCL_SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /**< WEP PSK Security with shared authentication */
SCL_SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /**< WPA PSK Security with TKIP */
SCL_SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /**< WPA PSK Security with AES */
SCL_SECURITY_WPA_MIXED_PSK = (WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA PSK Security with AES & TKIP */
SCL_SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /**< WPA2 PSK Security with AES */
SCL_SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 PSK Security with TKIP */
SCL_SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 PSK Security with AES & TKIP */
SCL_SECURITY_WPA2_FBT_PSK = (WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 FBT PSK Security with AES & TKIP */
SCL_SECURITY_WPA3_SAE = (WPA3_SECURITY | AES_ENABLED), /**< WPA3 Security with AES */
SCL_SECURITY_WPA3_WPA2_PSK = (WPA3_SECURITY | WPA2_SECURITY | AES_ENABLED), /**< WPA3 WPA2 PSK Security with AES */
SCL_SECURITY_WPA_TKIP_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | TKIP_ENABLED), /**< WPA Enterprise Security with TKIP */
SCL_SECURITY_WPA_AES_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED), /**< WPA Enterprise Security with AES */
SCL_SECURITY_WPA_MIXED_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA Enterprise Security with AES & TKIP */
SCL_SECURITY_WPA2_TKIP_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 Enterprise Security with TKIP */
SCL_SECURITY_WPA2_AES_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED), /**< WPA2 Enterprise Security with AES */
SCL_SECURITY_WPA2_MIXED_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 Enterprise Security with AES & TKIP */
SCL_SECURITY_WPA2_FBT_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 Enterprise Security with AES & FBT */
SCL_SECURITY_IBSS_OPEN = (IBSS_ENABLED), /**< Open security on IBSS ad-hoc network */
SCL_SECURITY_WPS_OPEN = (WPS_ENABLED), /**< WPS with open security */
SCL_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */
SCL_SECURITY_UNKNOWN = -1, /**< Returned by scan function if security is unknown. Do not pass this to the join function! */
SCL_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force scl_security_t type to 32 bits */
} scl_security_t;
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_SCL_TYPES_H_ */

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/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** @file
* Prototypes of functions for controlling the Wi-Fi system
*
* This file provides prototypes for end-user functions, which allow
* actions such as scanning for Wi-Fi networks, joining Wi-Fi
* networks, getting the MAC address, and so on.
*
*/
#include <stdbool.h>
#include "scl_common.h"
#ifndef INCLUDED_SCL_WIFI_API_H
#define INCLUDED_SCL_WIFI_API_H
#ifdef __cplusplus
extern "C"
{
#endif
/**
* SCL transmit buffer structure
*/
typedef struct scl_tx_buf {
scl_buffer_t buffer; /**< pointer to the buffer */
uint32_t size; /**< size of the buffer */
} scl_tx_buf_t;
/******************************************************
* Function Declarations
******************************************************/
/** @addtogroup wifi SCL Wi-Fi API
* APIs for controlling the Wi-Fi system
* @{
*/
/** Turn on the Wi-Fi device
*
* @note This API should be called before using any SCL Wi-Fi API.
*
* @return True if initialization is successful, False otherwise.
*/
extern bool scl_wifi_on(void);
/** Brings up the Wi-Fi core
*
* @return SCL_SUCCESS or Error code.
*/
extern scl_result_t scl_wifi_set_up(void);
/** Retrieves the current Media Access Control (MAC) address
* (or Ethernet hardware address) of the 802.11 device
*
* @param mac Pointer to a variable to which the current MAC address will be written.
*
* @return SCL_SUCCESS or Error code.
*/
extern scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac);
/** Gets the BSSID of the interface
*
* @note This API should be used after the device is connected to a network.
*
* @param bssid Returns the BSSID address (mac address), if associated.
*
* @return SCL_SUCCESS or Error code.
*/
extern scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid);
/** Registers interest in a multicast address
*
* Once a multicast address has been registered, all packets detected on the
* medium destined for that address are forwarded to the host.
* Otherwise, the packets are ignored.
*
* @param mac Ethernet MAC address.
*
* @return SCL_SUCCESS If the address was registered successfully or Error code.
*/
extern scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac);
/** Determines if an interface is ready to transmit/receive ethernet packets.
*
* @note This function must be called after the connection is established; otherwise, it returns Error code.
*
* @return SCL_SUCCESS If the interface is ready to transmit/receive ethernet packets.
* SCL_NOTFOUND If no AP with a matching SSID was found.
* SCL_NOT_AUTHENTICATED If matching AP was found, but it does not let you authenticate.
* @note This can occur if the device is in the blocklist of the AP.
* SCL_NOT_KEYED If the device has authenticated and associated but has not completed the key exchange.
* @note This can occur if the passphrase is incorrect.
* Error code If the interface is not ready to transmit/receive ethernet packets.
*/
extern scl_result_t scl_wifi_is_ready_to_transceive(void);
/** Sends an ethernet frame to SCL (called by the Network Stack)
*
* This function takes ethernet data from the network stack and transmits over the wireless network.
* This function returns immediately after the packet has been queued for transmission,
* NOT after it has been transmitted. Packet buffers passed to the SCL
* are released inside the SCL once they have been transmitted.
*
* @param buffer Handle of the packet buffer to be sent.
*
* @return SCL_SUCCESS or Error code.
*/
extern scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t buffer);
/** Retrieves the latest RSSI value
*
* @note This API must be called after the device is connected to a network.
*
* @param rssi Location where the RSSI value will be stored.
*
* @return SCL_SUCCESS If the RSSI was successfully retrieved or Error code.
*/
extern scl_result_t scl_wifi_get_rssi(int32_t *rssi);
/** Retrieves the RX data packet
*
* @param buffer Pointer to RX buffer.
*/
extern void scl_network_process_ethernet_data(scl_buffer_t buffer);
/** Notifies network stack about the change in network connection state
*
* @param state_up Connection state.
*/
extern void scl_emac_wifi_link_state_changed(bool state_up);
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_SCL_WIFI_API_H */

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/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** @file
* Provides SCL functionality to communicate with Network Processor
*/
#include "scl_ipc.h"
#include "scl_buffer_api.h"
#include "cyabs_rtos.h"
#include "mbed_wait_api.h"
#include "string.h"
#include "nsapi_types.h"
/******************************************************
** Macros
*******************************************************/
#define SCL_THREAD_STACK_SIZE (1000)
#define SCL_THREAD_PRIORITY (CY_RTOS_PRIORITY_HIGH)
#define SCL_INTR_SRC (cpuss_interrupts_ipc_4_IRQn)
#define SCL_INTR_PRI (1)
#define SCL_RX_CHANNEL (4)
#define SCL_CHANNEL_NOTIFY_INTR ((1 << SCL_RX_CHANNEL) << 16)
#define SCL_NOTIFY (1 << SCL_TX_CHANNEL)
#define SCL_LOCK_ACQUIRE_STATUS (0x80000000)
#define SCL_TX_CHANNEL (3)
#define SCL_RELEASE (0)
#define DELAY_TIME (1000)
#define SEMAPHORE_MAXCOUNT (1)
#define SEMAPHORE_INITCOUNT (0)
/******************************************************
** Function Declarations
*******************************************************/
static void scl_isr(void);
static void scl_config(void);
static void scl_rx_handler(void);
static scl_result_t scl_thread_init(void);
scl_result_t scl_get_nw_parameters(network_params_t *nw_param);
scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout);
scl_result_t scl_end(void);
scl_result_t scl_init(void);
/******************************************************
* Variables Definitions
*****************************************************/
/* Structure of SCL thread info
* scl_thread_quit_flag: flag used to determine if thread is to be quit
* scl_inited: flag used to determine if thread is started
* scl_thread: variable for thread handle
* scl_thread_stack_start: pointer to start of thread stack
* scl_thread_stack_size: size of thread stack
* scl_thread_priority: priority of thread
* scl_rx_ready: semaphore for blocking the thread
*/
struct scl_thread_info_t {
volatile scl_bool_t scl_inited;
volatile scl_bool_t scl_thread_quit_flag;
void *scl_thread_stack_start;
cy_thread_t scl_thread;
cy_semaphore_t scl_rx_ready;
uint32_t scl_thread_stack_size;
cy_thread_priority_t scl_thread_priority;
};
struct scl_thread_info_t g_scl_thread_info;
/******************************************************
* Function Definitions
******************************************************/
/** ISR for the IPC receiver channel interrupt
*/
static void scl_isr(void)
{
IPC_INTR_STRUCT_Type *scl_rx_intr = NULL;
scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL);
if (REG_IPC_INTR_STRUCT_INTR_MASKED(scl_rx_intr) & SCL_CHANNEL_NOTIFY_INTR) {
REG_IPC_INTR_STRUCT_INTR(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR;
if (g_scl_thread_info.scl_inited == SCL_TRUE) {
cy_rtos_set_semaphore(&g_scl_thread_info.scl_rx_ready, true);
}
}
}
/** Configures the IPC interrupt channel
*/
static void scl_config(void)
{
IPC_INTR_STRUCT_Type *scl_rx_intr = NULL;
cy_stc_sysint_t intrCfg = {
.intrSrc = SCL_INTR_SRC,
.intrPriority = SCL_INTR_PRI
};
scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL);
REG_IPC_INTR_STRUCT_INTR_MASK(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR;
Cy_SysInt_Init(&intrCfg, &scl_isr);
NVIC_EnableIRQ(intrCfg.intrSrc);
}
/** Create the SCL thread and initialize the semaphore for handling the events from Network Processor
*
* @return SCL_SUCCESS on successful initialization of thread or SCL_ERROR on failure
*/
static scl_result_t scl_thread_init(void)
{
cy_rslt_t retval, tmp = 0;
memset(&g_scl_thread_info, 0, sizeof(g_scl_thread_info));
g_scl_thread_info.scl_thread_stack_start = (uint8_t *) malloc(SCL_THREAD_STACK_SIZE);;
g_scl_thread_info.scl_thread_stack_size = (uint32_t) SCL_THREAD_STACK_SIZE;
g_scl_thread_info.scl_thread_priority = (cy_thread_priority_t) SCL_THREAD_PRIORITY;
if (g_scl_thread_info.scl_inited != SCL_TRUE) {
retval = cy_rtos_init_semaphore(&g_scl_thread_info.scl_rx_ready, SEMAPHORE_MAXCOUNT, SEMAPHORE_INITCOUNT);
if (retval != SCL_SUCCESS) {
return SCL_ERROR;
}
retval = cy_rtos_create_thread(&g_scl_thread_info.scl_thread, (cy_thread_entry_fn_t) scl_rx_handler,
"SCL_thread", g_scl_thread_info.scl_thread_stack_start,
g_scl_thread_info.scl_thread_stack_size,
g_scl_thread_info.scl_thread_priority, (uint32_t) tmp);
if (retval != SCL_SUCCESS) {
return SCL_ERROR;
}
g_scl_thread_info.scl_inited = SCL_TRUE;
} else {
return SCL_ERROR;
}
return SCL_SUCCESS;
}
scl_result_t scl_init(void)
{
scl_result_t retval = SCL_SUCCESS;
uint32_t configuration_parameters = 0;
#ifdef MBED_CONF_TARGET_NP_CLOUD_DISABLE
configuration_parameters = (MBED_CONF_TARGET_NP_CLOUD_DISABLE << 1);
#else
configuration_parameters = (false << 1);
#endif
#ifdef MBED_CONF_TARGET_NP_WIFI_ENABLE
configuration_parameters |= MBED_CONF_TARGET_NP_WIFI_ENABLE;
#else
configuration_parameters |= false;
#endif
//SCL_LOG("configuration_parameters = %lu\n", configuration_parameters);
scl_config();
if (g_scl_thread_info.scl_inited != SCL_TRUE) {
retval = scl_thread_init();
if (retval != SCL_SUCCESS) {
SCL_LOG(("Thread init failed\n"));
return SCL_ERROR;
} else {
retval = scl_send_data(SCL_TX_CONFIG_PARAMETERS, (char *) &configuration_parameters, TIMER_DEFAULT_VALUE);
return retval;
}
}
return SCL_SUCCESS;
}
scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout)
{
uint32_t acquire_state;
IPC_STRUCT_Type *scl_send = NULL;
uint32_t delay_timeout;
SCL_LOG(("scl_send_data index = %d\n", index));
scl_send = Cy_IPC_Drv_GetIpcBaseAddress(SCL_TX_CHANNEL);
CHECK_BUFFER_NULL(buffer);
if (!(REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS)) {
acquire_state = REG_IPC_STRUCT_ACQUIRE(scl_send);
if (!(acquire_state & SCL_LOCK_ACQUIRE_STATUS)) {
SCL_LOG(("IPC Channel 3 Acquired Failed\r\n"));
return SCL_ERROR;
}
REG_IPC_STRUCT_DATA0(scl_send) = index;
REG_IPC_STRUCT_DATA1(scl_send) = (uint32_t) buffer;
REG_IPC_STRUCT_NOTIFY(scl_send) = SCL_NOTIFY;
delay_timeout = 0;
while ((REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS) && delay_timeout <= timeout) {
wait_us(DELAY_TIME);
delay_timeout++;
}
if (delay_timeout > timeout) {
REG_IPC_STRUCT_RELEASE(scl_send) = SCL_RELEASE;
delay_timeout = 0;
return SCL_ERROR;
} else {
return SCL_SUCCESS;
}
} else {
SCL_LOG(("unable to acquire lock\n"));
return SCL_ERROR;
}
}
scl_result_t scl_end(void)
{
scl_result_t retval = SCL_SUCCESS;
if (g_scl_thread_info.scl_inited == SCL_TRUE) {
retval = (scl_result_t) cy_rtos_terminate_thread(&g_scl_thread_info.scl_thread);
if (retval == SCL_SUCCESS) {
retval = (scl_result_t) cy_rtos_join_thread(&g_scl_thread_info.scl_thread);
if (retval == SCL_SUCCESS) {
retval = (scl_result_t) cy_rtos_deinit_semaphore(&g_scl_thread_info.scl_rx_ready);
if (retval == SCL_SUCCESS) {
g_scl_thread_info.scl_inited = SCL_FALSE;
}
}
}
}
return retval;
}
/** Thread to handle the received buffer
*/
static void scl_rx_handler(void)
{
char *buffer = NULL;
nsapi_connection_status_t connection_status;
uint32_t index;
IPC_STRUCT_Type *scl_receive = NULL;
scl_buffer_t cp_buffer;
scl_buffer_t scl_buffer;
uint32_t rx_ipc_size;
struct rx_ipc_info {
uint32_t size;
int *buf_alloc;
}*rx_cp = NULL;
SCL_LOG(("Starting CP Rx thread\r\n"));
scl_receive = Cy_IPC_Drv_GetIpcBaseAddress(SCL_RX_CHANNEL);
while (SCL_TRUE) {
cy_rtos_get_semaphore(&g_scl_thread_info.scl_rx_ready, CY_RTOS_NEVER_TIMEOUT, SCL_FALSE);
index = (uint32_t)REG_IPC_STRUCT_DATA0(scl_receive);
SCL_LOG(("scl_rx_handler index = %lu\n", index));
switch (index) {
case SCL_RX_DATA: {
rx_cp = (struct rx_ipc_info *) REG_IPC_STRUCT_DATA1(scl_receive);
scl_buffer = rx_cp->buf_alloc;
REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE;
SCL_LOG(("scl_buffer = %p\n", scl_buffer));
scl_network_process_ethernet_data(scl_buffer);
break;
}
case SCL_RX_TEST_MSG: {
buffer = (char *) REG_IPC_STRUCT_DATA1(scl_receive);
SCL_LOG(("%s\r\n", (char *) buffer));
REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE;
break;
}
case SCL_RX_GET_BUFFER: {
rx_ipc_size = (uint32_t) REG_IPC_STRUCT_DATA1(scl_receive);
scl_host_buffer_get(&cp_buffer, SCL_NETWORK_RX, rx_ipc_size, SCL_FALSE);
REG_IPC_STRUCT_DATA1(scl_receive) = (uint32_t)cp_buffer;
REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE;
break;
}
case SCL_RX_GET_CONNECTION_STATUS: {
connection_status = (nsapi_connection_status_t) REG_IPC_STRUCT_DATA1(scl_receive);
if (connection_status == NSAPI_STATUS_GLOBAL_UP) {
scl_emac_wifi_link_state_changed(true);
} else {
scl_emac_wifi_link_state_changed(false);
}
SCL_LOG(("connection status = %d\n", connection_status));
break;
}
default: {
SCL_LOG(("incorrect IPC from Network Processor\n"));
REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE;
break;
}
}
}
}
scl_result_t scl_get_nw_parameters(network_params_t *nw_param)
{
scl_result_t status = SCL_ERROR;
status = scl_send_data(SCL_TX_WIFI_NW_PARAM, (char *)nw_param, TIMER_DEFAULT_VALUE);
return status;
}

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/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/** @file
* Provides declarations for buffer management functionality
*/
#ifndef _SCL_INTERNAL_BUFFER_API_H_
#define _SCL_INTERNAL_BUFFER_API_H_
#include "scl_types.h"
#include "scl_common.h"
#include <stdlib.h>
#include "cy_utils.h"
#include "memp.h"
#include "pbuf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/******************************************************
* Constants
******************************************************/
/**
* Size of the SDIO block
*/
#define SDIO_BLOCK_SIZE (64U)
/******************************************************
* Macros
******************************************************/
/******************************************************
* Structures and Enumerations
******************************************************/
/**
* Indicates the transmit/receive direction that the buffer has
* been used for. This is needed if transmit/receive pools are separate.
*/
typedef enum {
SCL_NETWORK_TX = 0, /**< Transmit direction */
SCL_NETWORK_RX = 1 /**< Receive direction */
} scl_buffer_dir_t;
/******************************************************
* Function Prototypes
******************************************************/
/** Allocates the SCL buffer.
*
* Attempts to allocate a buffer of the requested size. A buffer
* is either allocated from a static pool of memory or allocated dynamically.
*
* @param buffer A pointer which receives the allocated buffer.
* @param direction Indicates transmit/receive direction that the buffer is
* used for. This may be needed if transmit/receive pools are separate.
* @param size The number of bytes to allocate.
* @param wait Time to wait for a buffer to be available in milli-seconds.
*
* @return SCL_SUCCESS or Error code
*
*/
scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction,
uint16_t size, uint32_t wait);
/** Releases the SCL buffer.
*
* This function is used by SCL to indicate that it no longer requires
* the buffer. The buffer can then be released back into a pool for
* reuse or the dynamically allocated memory can be freed.
*
* @param buffer The buffer to be released.
* @param direction Indicates the transmit/receive direction that the buffer has
* been used for. This might be needed if transmit/receive pools are separate.
*
*/
void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction);
/** Retrieves the pointer to the payload of the buffer.
*
* @param buffer The buffer whose payload pointer is to be retrieved.
*
* @return Pointer to the payload.
*/
uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer);
/** Retrieves the size of the buffer.
*
* @param buffer The buffer whose size is to be retrieved.
*
* @return The size of the buffer.
*/
uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer);
#ifdef __cplusplus
} /*extern "C" */
#endif
#endif /* ifndef _SCL_INTERNAL_BUFFER_API_H_ */

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/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "scl_buffer_api.h"
/******************************************************
** @cond Constants
*******************************************************/
/******************************************************
** Enumerations
*******************************************************/
/******************************************************
** Function Declarations
*******************************************************/
/******************************************************
* Variables Definitions
*****************************************************/
/******************************************************
* Function Definitions
******************************************************/
scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction,
uint16_t size, uint32_t wait)
{
UNUSED_PARAMETER(direction);
struct pbuf *p = NULL;
if ((direction == SCL_NETWORK_TX) && (size <= PBUF_POOL_BUFSIZE)) {
p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL);
} else {
p = pbuf_alloc(PBUF_RAW, size + SDIO_BLOCK_SIZE, PBUF_RAM);
if (p != NULL) {
p->len = size;
p->tot_len -= SDIO_BLOCK_SIZE;
}
}
if (p != NULL) {
*buffer = p;
return SCL_SUCCESS;
} else {
return SCL_BUFFER_ALLOC_FAIL;
}
}
void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction)
{
UNUSED_PARAMETER(direction);
(void) pbuf_free((struct pbuf *)buffer);
}
uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer)
{
CY_ASSERT(buffer != NULL);
struct pbuf *pbuffer = (struct pbuf *) buffer;
return (uint8_t *) pbuffer->payload;
}
uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer)
{
CY_ASSERT(buffer != NULL);
struct pbuf *pbuffer = (struct pbuf *) buffer;
return (uint16_t) pbuffer->len;
}

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/*
* Copyright 2018-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "scl_wifi_api.h"
#include "scl_ipc.h"
/******************************************************
* Variables Definitions
*****************************************************/
typedef struct {
scl_mac_t *mac;
uint32_t retval;
} scl_mac;
/******************************************************
* Function Definitions
******************************************************/
scl_result_t scl_wifi_is_ready_to_transceive(void)
{
scl_result_t result = SCL_SUCCESS;
scl_result_t retval = SCL_SUCCESS;
result = scl_send_data(SCL_TX_TRANSCEIVE_READY, (char *)&retval, TIMER_DEFAULT_VALUE);
if (result == SCL_ERROR) {
SCL_LOG(("Ready to tranceive error\n"));
return SCL_ERROR;
} else {
return retval;
}
}
bool scl_wifi_on(void)
{
bool retval = false;
scl_result_t result = SCL_SUCCESS;
result = scl_send_data(SCL_TX_WIFI_ON, (char *)&retval, WIFI_ON_TIMEOUT);
if (result == SCL_ERROR) {
SCL_LOG(("wifi_on Error\n"));
return false;
} else {
return retval;
}
}
scl_result_t scl_wifi_set_up(void)
{
scl_result_t retval = SCL_SUCCESS;
scl_result_t result = SCL_SUCCESS;
result = scl_send_data(SCL_TX_WIFI_SET_UP, (char *)&retval, TIMER_DEFAULT_VALUE);
if (result == SCL_SUCCESS) {
return retval;
} else {
SCL_LOG(("Wifi set up error\n"));
return SCL_ERROR;
}
}
scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac)
{
scl_mac scl_mac_data;
scl_result_t scl_retval = SCL_SUCCESS;
scl_mac_data.mac = mac;
scl_mac_data.retval = SCL_SUCCESS;
if (mac == NULL) {
return SCL_BADARG;
}
scl_retval = scl_send_data(SCL_TX_GET_MAC, (char *)&scl_mac_data, TIMER_DEFAULT_VALUE);
if (scl_retval == SCL_SUCCESS) {
return scl_mac_data.retval;
} else {
SCL_LOG(("Get MAC address error\n"));
return SCL_ERROR;
}
}
scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid)
{
struct scl_bssid {
scl_mac_t *bssid;
uint32_t retval;
} scl_bssid_t;
scl_result_t scl_retval = SCL_SUCCESS;
scl_bssid_t.bssid = bssid;
scl_bssid_t.retval = 0;
if (bssid == NULL) {
return SCL_BADARG;
}
scl_retval = scl_send_data(SCL_TX_WIFI_GET_BSSID, (char *)&scl_bssid_t, TIMER_DEFAULT_VALUE);
if (scl_retval == SCL_SUCCESS) {
return scl_bssid_t.retval;
} else {
SCL_LOG(("get bssid error\n"));
return SCL_ERROR;
}
}
scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac)
{
scl_mac scl_mac_t;
scl_mac_t.mac = mac;
scl_mac_t.retval = 0;
scl_result_t scl_retval = SCL_SUCCESS;
if (mac == NULL) {
return SCL_BADARG;
}
scl_retval = scl_send_data(SCL_TX_REGISTER_MULTICAST_ADDRESS, (char *)&scl_mac_t, TIMER_DEFAULT_VALUE);
if (scl_retval != SCL_SUCCESS) {
SCL_LOG(("Register Multicast Address IPC Error"));
return SCL_ERROR;
}
return (scl_mac_t.retval);
}
scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t scl_buffer)
{
scl_result_t retval = SCL_SUCCESS;
if (scl_buffer.buffer == NULL) {
return SCL_BADARG;
}
retval = scl_send_data(SCL_TX_SEND_OUT, (char *)&scl_buffer, TIMER_DEFAULT_VALUE);
return retval;
}
scl_result_t scl_wifi_get_rssi(int32_t *rssi)
{
struct tx_param {
uint32_t retval;
int32_t *get_rssi;
} tx_param_t;
scl_result_t scl_retval = SCL_SUCCESS;
if (rssi == NULL) {
return SCL_BADARG;
}
tx_param_t.get_rssi = rssi;
scl_retval = scl_send_data(SCL_TX_WIFI_GET_RSSI, (char *) &tx_param_t, TIMER_DEFAULT_VALUE);
if (scl_retval == SCL_SUCCESS) {
return tx_param_t.retval;
} else {
SCL_LOG(("get rssi error\n"));
return SCL_ERROR;
}
}

33
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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@ -1,33 +0,0 @@
/*******************************************************************************
* File Name: cycfg.c
*
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg.h"
void init_cycfg_all(void)
{
init_cycfg_routing();
init_cycfg_pins();
}

47
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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@ -1,47 +0,0 @@
/*******************************************************************************
* File Name: cycfg.h
*
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_H)
#define CYCFG_H
#if defined(__cplusplus)
extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_routing.h"
#include "cycfg_pins.h"
void init_cycfg_all(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_H */

26
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
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@ -1,26 +0,0 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

32
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
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@ -1,32 +0,0 @@
/*******************************************************************************
* File Name: cycfg_notices.h
*
* Description:
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_NOTICES_H)
#define CYCFG_NOTICES_H
#endif /* CYCFG_NOTICES_H */

177
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
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@ -1,177 +0,0 @@
/*******************************************************************************
* File Name: cycfg_pins.c
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_SW1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_SW1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SW1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SW1_PORT_NUM,
.channel_num = CYBSP_SW1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_LED1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_LED1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_LED1_PORT_NUM,
.channel_num = CYBSP_LED1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
.hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SW1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_LED1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
#endif //defined (CY_USING_HAL)
}

190
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
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@ -1,190 +0,0 @@
/*******************************************************************************
* File Name: cycfg_pins.h
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PINS_H)
#define CYCFG_PINS_H
#include "cycfg_notices.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_SW1_ENABLED 1U
#define CYBSP_SW1_PORT GPIO_PRT0
#define CYBSP_SW1_PORT_NUM 0U
#define CYBSP_SW1_PIN 4U
#define CYBSP_SW1_NUM 4U
#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_SW1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SW1_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_SW1_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_PORT_PIN P0_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_LED1_ENABLED 1U
#define CYBSP_LED1_PORT GPIO_PRT11
#define CYBSP_LED1_PORT_NUM 11U
#define CYBSP_LED1_PIN 1U
#define CYBSP_LED1_NUM 1U
#define CYBSP_LED1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED1_HSIOM ioss_0_port_11_pin_1_HSIOM
#define CYBSP_LED1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_PORT_PIN P11_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PORT_NUM 6U
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PORT_NUM 6U
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SW1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_LED1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PINS_H */

266
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
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@ -1,266 +0,0 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 4U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

51
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
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@ -1,51 +0,0 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
* QSPI Configurator: 2.0.0.1483
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

31
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
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@ -1,31 +0,0 @@
/*******************************************************************************
* File Name: cycfg_routing.c
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_routing.h"
void init_cycfg_routing(void)
{
}

46
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
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@ -1,46 +0,0 @@
/*******************************************************************************
* File Name: cycfg_routing.h
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_ROUTING_H)
#define CYCFG_ROUTING_H
#if defined(__cplusplus)
extern "C" {
#endif
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_ROUTING_H */

28
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
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@ -1,28 +0,0 @@
/*******************************************************************************
* File Name: cycfg_system.c
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_system.h"

43
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
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@ -1,43 +0,0 @@
/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
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@ -1,2 +0,0 @@
set SMIF_BANKS {
}

99
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
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@ -1,99 +0,0 @@
[Device=CY8C624AFNI-D43]
[Blocks]
# WIFI
# CYBSP_WIFI_SDIO
sdhc[0]
# CYBSP_WIFI_SDIO_D0
ioss[0].port[2].pin[0]
# CYBSP_WIFI_SDIO_D1
ioss[0].port[2].pin[1]
# CYBSP_WIFI_SDIO_D2
ioss[0].port[2].pin[2]
# CYBSP_WIFI_SDIO_D3
ioss[0].port[2].pin[3]
# CYBSP_WIFI_SDIO_CMD
ioss[0].port[2].pin[4]
# CYBSP_WIFI_SDIO_CLK
ioss[0].port[2].pin[5]
# CYBSP_WIFI_WL_REG_ON
ioss[0].port[2].pin[6]
# CYBSP_WIFI_DEVICE_WAKE
ioss[0].port[2].pin[7]
# CYBSP_WIFI_HOST_WAKE
ioss[0].port[1].pin[4]
# BT UART
# CYBSP_BT_UART
scb[12]
# CYBSP_BT_POWER
ioss[0].port[12].pin[0]
# CYBSP_BT_DEVICE_WAKE
ioss[0].port[12].pin[2]
# CYBSP_BT_HOST_WAKE
ioss[0].port[12].pin[3]
# CYBSP_BT_UART_RX
ioss[0].port[13].pin[4]
# CYBSP_BT_UART_TX
ioss[0].port[13].pin[5]
# CYBSP_BT_UART_RTS
ioss[0].port[13].pin[6]
# CYBSP_BT_UART_CTS
ioss[0].port[13].pin[7]
# CYBSP_BT_UART_CLK_DIV
peri[0].div_16[1]
# UART
# CYBSP_DEBUG_UART
scb[10]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[4]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[5]
# CYBSP_DEBUG_UART_CLK_DIV
peri[0].div_16[0]
# POWER
srss[0].power[0]
# SYSTEM CLOCK
srss[0].clock[0]
# CLK_ALT_SYS_TICK
srss[0].clock[0].altsystickclk[0]
# CLK_BAK
srss[0].clock[0].bakclk[0]
# CLK_FAST
srss[0].clock[0].fastclk[0]
# CLK_HF0
srss[0].clock[0].hfclk[0]
# CLK_HF2
srss[0].clock[0].hfclk[2]
# CLK_HF4
srss[0].clock[0].hfclk[4]
# CLK_ILO
srss[0].clock[0].ilo[0]
# CLK_IMO
srss[0].clock[0].imo[0]
# CLK_LF
srss[0].clock[0].lfclk[0]
# PATH_MUX0
srss[0].clock[0].pathmux[0]
# PATH_MUX1
srss[0].clock[0].pathmux[1]
# CLK_PERI
srss[0].clock[0].periclk[0]
# CLK_PLL0
srss[0].clock[0].pll[0]
# CLK_SLOW
srss[0].clock[0].slowclk[0]
# CLK_TIMER
srss[0].clock[0].timerclk[0]
# RTC
srss[0].rtc[0]
# CM0(NP) I2C
# CYBSP_I2C_SCL
ioss[0].port[8].pin[0]
# CYBSP_I2C_SDA
ioss[0].port[8].pin[1]

71
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
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@ -1,71 +0,0 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0.1483-->
<Configuration app="Capsense" major="2" minor="0">
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets/>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi
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@ -1,63 +0,0 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1800FFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

106
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
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@ -1,106 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C624AFNI-D43">
<BlockConfig>
<Block location="cpuss[0].dap[0]">
<Personality template="mxs40dap" version="1.0">
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Personality>
</Block>
<Block location="ioss[0].port[0].pin[4]">
<Alias value="CYBSP_SW1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[1]">
<Alias value="CYBSP_LED1"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[6]">
<Alias value="CYBSP_SWDIO"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[6].pin[7]">
<Alias value="CYBSP_SWDCK"/>
<Personality template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[8].pin[5]">
<Alias value="CYBSP_CSD_SLD2"/>
</Block>
<Block location="ioss[0].port[8].pin[6]">
<Alias value="CYBSP_CSD_SLD3"/>
</Block>
<Block location="ioss[0].port[8].pin[7]">
<Alias value="CYBSP_CSD_SLD4"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
<Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
</Net>
</Netlist>
</Device>
</Devices>
<Libraries/>
<ConfiguratorData/>
</Design>

427
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c
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@ -1,427 +0,0 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
* Copyright (c) 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralNames.h"
#include "PeripheralPins.h"
#include "pinmap.h"
#if DEVICE_SERIAL
//*** SERIAL ***
const PinMap PinMap_UART_RX[] = {
{P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)},
{P2_4, UART_9, CYHAL_PIN_IN_FUNCTION(P2_4_SCB9_UART_RX)},
{P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P5_4, UART_10, CYHAL_PIN_IN_FUNCTION(P5_4_SCB10_UART_RX)},
{P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P8_4, UART_11, CYHAL_PIN_IN_FUNCTION(P8_4_SCB11_UART_RX)},
{P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
{P13_4, UART_12, CYHAL_PIN_IN_FUNCTION(P13_4_SCB12_UART_RX)},
{NC, NC, 0}
};
const PinMap PinMap_UART_TX[] = {
{P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)},
{P2_5, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB9_UART_TX)},
{P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P5_5, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB10_UART_TX)},
{P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
{P13_5, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB12_UART_TX)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)},
{P2_6, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB9_UART_RTS)},
{P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P5_6, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB10_UART_RTS)},
{P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
{P13_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)},
{P13_6, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB12_UART_RTS)},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)},
{P2_7, UART_9, CYHAL_PIN_IN_FUNCTION(P2_7_SCB9_UART_CTS)},
{P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P5_7, UART_10, CYHAL_PIN_IN_FUNCTION(P5_7_SCB10_UART_CTS)},
{P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
{P13_3, UART_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)},
{P13_7, UART_12, CYHAL_PIN_IN_FUNCTION(P13_7_SCB12_UART_CTS)},
{NC, NC, 0}
};
#endif // DEVICE_SERIAL
#if DEVICE_I2C
//*** I2C ***
const PinMap PinMap_I2C_SCL[] = {
{P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)},
{P2_4, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_4_SCB9_I2C_SCL)},
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)},
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
{P13_4, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_4_SCB12_I2C_SCL)},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SDA[] = {
{P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)},
{P2_5, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_5_SCB9_I2C_SDA)},
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
{P13_5, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_5_SCB12_I2C_SDA)},
{NC, NC, 0}
};
#endif // DEVICE_I2C
#if DEVICE_SPI
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
{P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
{NC, NC, 0}
};
#endif // DEVICE_SPI
#if DEVICE_PWMOUT
//*** PWM ***
const PinMap PinMap_PWM_OUT[] = {
// 16-bit PWM outputs
{P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)},
{P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)},
{P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)},
{P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)},
{P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)},
{P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)},
{P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
// 16-bit PWM inverted outputs
{P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)},
{P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)},
{P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)},
{P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)},
{P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)},
{P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)},
{P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
// 32-bit PWM outputs
{P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)},
{P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)},
{P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)},
{P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)},
{P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)},
{P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)},
{P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
// 32-bit PWM inverted outputs
{P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)},
{P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)},
{P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)},
{P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)},
{P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)},
{P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)},
{P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{NC, NC, 0}
};
#endif // DEVICE_PWMOUT
#if DEVICE_ANALOGIN
const PinMap PinMap_ADC[] = {
{P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus
{P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus
{P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus
{P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN
#if DEVICE_QSPI
const PinMap PinMap_QSPI_SCLK[] = {
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_SSEL[] = {
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA0[] = {
{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA1[] = {
{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA2[] = {
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA3[] = {
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
#endif // DEVICE_QSPI

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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c
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/***************************************************************************//**
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdlib.h>
#include "cy_syspm.h"
#include "cy_sysclk.h"
#include "cybsp.h"
#if defined(CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif
#if !defined (CY_CFG_PWR_SYS_IDLE_MODE)
#include "mbed_power_mgmt.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
#else
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
init_cycfg_all();
#endif
if (CY_RSLT_SUCCESS == result)
{
result = cybsp_register_sysclk_pm_callback();
}
#if !defined(CY_CFG_PWR_SYS_IDLE_MODE)
/* Disable deep-sleep. */
sleep_manager_lock_deep_sleep();
#endif
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}
#if defined(__cplusplus)
}
#endif

76
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h
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/***************************************************************************//**
* \file cybsp.h
*
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#include "cyhal_sdio.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */

194
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h
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/***************************************************************************//**
* \file CYSBSYSKIT_01/cybsp_types.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CYSBSYSKIT_01 kit.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
#ifndef CY_CFG_SYSCLK_CLKLF_FREQ_HZ
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ (32000U)
#endif
/**
* \addtogroup group_bsp_settings BSP Settings
* \{
*
* <div class="category">Peripheral Default HAL Settings:</div>
* | Resource | Parameter | Value | Remarks |
* | :------: | :-------: | :---: | :------ |
* | ADC | VREF | 1.2 V | |
* | ^ | Measurement type | Single Ended | |
* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | |
* | ^ | Output range | 0x000 to 0x7FF | |
* | DAC | Reference source | VDDA | |
* | ^ | Input range | 0x000 to 0xFFF | |
* | ^ | Output range | 0 to VDDA | |
* | ^ | Output type | Unbuffered output | |
* | I2C | Role | Master | Configurable to slave mode through HAL function |
* | ^ | Data rate | 100 kbps | Configurable through HAL function |
* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required |
* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. |||
* | SPI | Data rate | 100 kpbs | Configurable through HAL function |
* | ^ | Slave select polarity | Active low | |
* | UART | Flow control | No flow control | Configurable through HAL function |
* | ^ | Data format | 8N1 | Configurable through HAL function |
* | ^ | Baud rate | 115200 | Configurable through HAL function |
*/
/** \} group_bsp_settings */
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
#if defined(CY_USING_HAL)
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
/**
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** BSP user LED1 reference designator to pin mapping */
#define CYBSP_USER_LED1 (P11_1)
/** \} group_bsp_pins_led */
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** BSP user button reference designator to pin mapping */
#define CYBSP_USER_BTN (P0_4)
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P1_4)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P13_4)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P13_5)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P13_6)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P13_7)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P12_0)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P12_3)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P12_2)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_4)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_5)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** \} group_bsp_pins_comm */
/** \} group_bsp_pins */
#endif /* defined(CY_USING_HAL) */
#if defined(__cplusplus)
}
#endif

298
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10180000
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image.
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START)
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system.
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE (MBED_ROM_SIZE)
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08080000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x7F800
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE
; Flash
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
{
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
{
}
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00200000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */

703
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S
View File

@ -1,703 +0,0 @@
;/**************************************************************************//**
; * @file startup_psoc6_02_cm4.S
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Description
DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9
DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10
DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11
DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16
DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17
DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18
DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19
DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20
DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21
DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22
DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23
DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24
DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25
DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26
DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27
DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16
DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17
DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18
DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19
DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20
DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21
DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22
DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23
DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24
DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25
DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26
DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27
DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used
DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Weak function for startup customization
;
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
; because this function is executed as the first instruction in the ResetHandler.
; The PDL is also not initialized to use the proper register offsets.
; The user of this function is responsible for initializing the PDL and resources before using them.
;
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT Cy_SystemInitFpuEnable
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Wrapper\
PROC
EXPORT HardFault_Wrapper [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B HardFault_Wrapper
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
EXPORT lpcomp_interrupt_IRQHandler [WEAK]
EXPORT scb_8_interrupt_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
EXPORT srss_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
EXPORT scb_0_interrupt_IRQHandler [WEAK]
EXPORT scb_1_interrupt_IRQHandler [WEAK]
EXPORT scb_2_interrupt_IRQHandler [WEAK]
EXPORT scb_3_interrupt_IRQHandler [WEAK]
EXPORT scb_4_interrupt_IRQHandler [WEAK]
EXPORT scb_5_interrupt_IRQHandler [WEAK]
EXPORT scb_6_interrupt_IRQHandler [WEAK]
EXPORT scb_7_interrupt_IRQHandler [WEAK]
EXPORT scb_9_interrupt_IRQHandler [WEAK]
EXPORT scb_10_interrupt_IRQHandler [WEAK]
EXPORT scb_11_interrupt_IRQHandler [WEAK]
EXPORT scb_12_interrupt_IRQHandler [WEAK]
EXPORT csd_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK]
EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK]
EXPORT profile_interrupt_IRQHandler [WEAK]
EXPORT smif_interrupt_IRQHandler [WEAK]
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
EXPORT usb_interrupt_med_IRQHandler [WEAK]
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK]
EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK]
EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK]
EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK]
ioss_interrupts_gpio_0_IRQHandler
ioss_interrupts_gpio_1_IRQHandler
ioss_interrupts_gpio_2_IRQHandler
ioss_interrupts_gpio_3_IRQHandler
ioss_interrupts_gpio_4_IRQHandler
ioss_interrupts_gpio_5_IRQHandler
ioss_interrupts_gpio_6_IRQHandler
ioss_interrupts_gpio_7_IRQHandler
ioss_interrupts_gpio_8_IRQHandler
ioss_interrupts_gpio_9_IRQHandler
ioss_interrupts_gpio_10_IRQHandler
ioss_interrupts_gpio_11_IRQHandler
ioss_interrupts_gpio_12_IRQHandler
ioss_interrupts_gpio_13_IRQHandler
ioss_interrupts_gpio_14_IRQHandler
ioss_interrupt_gpio_IRQHandler
ioss_interrupt_vdd_IRQHandler
lpcomp_interrupt_IRQHandler
scb_8_interrupt_IRQHandler
srss_interrupt_mcwdt_0_IRQHandler
srss_interrupt_mcwdt_1_IRQHandler
srss_interrupt_backup_IRQHandler
srss_interrupt_IRQHandler
cpuss_interrupts_ipc_0_IRQHandler
cpuss_interrupts_ipc_1_IRQHandler
cpuss_interrupts_ipc_2_IRQHandler
cpuss_interrupts_ipc_3_IRQHandler
cpuss_interrupts_ipc_4_IRQHandler
cpuss_interrupts_ipc_5_IRQHandler
cpuss_interrupts_ipc_6_IRQHandler
cpuss_interrupts_ipc_7_IRQHandler
cpuss_interrupts_ipc_8_IRQHandler
cpuss_interrupts_ipc_9_IRQHandler
cpuss_interrupts_ipc_10_IRQHandler
cpuss_interrupts_ipc_11_IRQHandler
cpuss_interrupts_ipc_12_IRQHandler
cpuss_interrupts_ipc_13_IRQHandler
cpuss_interrupts_ipc_14_IRQHandler
cpuss_interrupts_ipc_15_IRQHandler
scb_0_interrupt_IRQHandler
scb_1_interrupt_IRQHandler
scb_2_interrupt_IRQHandler
scb_3_interrupt_IRQHandler
scb_4_interrupt_IRQHandler
scb_5_interrupt_IRQHandler
scb_6_interrupt_IRQHandler
scb_7_interrupt_IRQHandler
scb_9_interrupt_IRQHandler
scb_10_interrupt_IRQHandler
scb_11_interrupt_IRQHandler
scb_12_interrupt_IRQHandler
csd_interrupt_IRQHandler
cpuss_interrupts_dmac_0_IRQHandler
cpuss_interrupts_dmac_1_IRQHandler
cpuss_interrupts_dmac_2_IRQHandler
cpuss_interrupts_dmac_3_IRQHandler
cpuss_interrupts_dw0_0_IRQHandler
cpuss_interrupts_dw0_1_IRQHandler
cpuss_interrupts_dw0_2_IRQHandler
cpuss_interrupts_dw0_3_IRQHandler
cpuss_interrupts_dw0_4_IRQHandler
cpuss_interrupts_dw0_5_IRQHandler
cpuss_interrupts_dw0_6_IRQHandler
cpuss_interrupts_dw0_7_IRQHandler
cpuss_interrupts_dw0_8_IRQHandler
cpuss_interrupts_dw0_9_IRQHandler
cpuss_interrupts_dw0_10_IRQHandler
cpuss_interrupts_dw0_11_IRQHandler
cpuss_interrupts_dw0_12_IRQHandler
cpuss_interrupts_dw0_13_IRQHandler
cpuss_interrupts_dw0_14_IRQHandler
cpuss_interrupts_dw0_15_IRQHandler
cpuss_interrupts_dw0_16_IRQHandler
cpuss_interrupts_dw0_17_IRQHandler
cpuss_interrupts_dw0_18_IRQHandler
cpuss_interrupts_dw0_19_IRQHandler
cpuss_interrupts_dw0_20_IRQHandler
cpuss_interrupts_dw0_21_IRQHandler
cpuss_interrupts_dw0_22_IRQHandler
cpuss_interrupts_dw0_23_IRQHandler
cpuss_interrupts_dw0_24_IRQHandler
cpuss_interrupts_dw0_25_IRQHandler
cpuss_interrupts_dw0_26_IRQHandler
cpuss_interrupts_dw0_27_IRQHandler
cpuss_interrupts_dw0_28_IRQHandler
cpuss_interrupts_dw1_0_IRQHandler
cpuss_interrupts_dw1_1_IRQHandler
cpuss_interrupts_dw1_2_IRQHandler
cpuss_interrupts_dw1_3_IRQHandler
cpuss_interrupts_dw1_4_IRQHandler
cpuss_interrupts_dw1_5_IRQHandler
cpuss_interrupts_dw1_6_IRQHandler
cpuss_interrupts_dw1_7_IRQHandler
cpuss_interrupts_dw1_8_IRQHandler
cpuss_interrupts_dw1_9_IRQHandler
cpuss_interrupts_dw1_10_IRQHandler
cpuss_interrupts_dw1_11_IRQHandler
cpuss_interrupts_dw1_12_IRQHandler
cpuss_interrupts_dw1_13_IRQHandler
cpuss_interrupts_dw1_14_IRQHandler
cpuss_interrupts_dw1_15_IRQHandler
cpuss_interrupts_dw1_16_IRQHandler
cpuss_interrupts_dw1_17_IRQHandler
cpuss_interrupts_dw1_18_IRQHandler
cpuss_interrupts_dw1_19_IRQHandler
cpuss_interrupts_dw1_20_IRQHandler
cpuss_interrupts_dw1_21_IRQHandler
cpuss_interrupts_dw1_22_IRQHandler
cpuss_interrupts_dw1_23_IRQHandler
cpuss_interrupts_dw1_24_IRQHandler
cpuss_interrupts_dw1_25_IRQHandler
cpuss_interrupts_dw1_26_IRQHandler
cpuss_interrupts_dw1_27_IRQHandler
cpuss_interrupts_dw1_28_IRQHandler
cpuss_interrupts_fault_0_IRQHandler
cpuss_interrupts_fault_1_IRQHandler
cpuss_interrupt_crypto_IRQHandler
cpuss_interrupt_fm_IRQHandler
cpuss_interrupts_cm4_fp_IRQHandler
cpuss_interrupts_cm0_cti_0_IRQHandler
cpuss_interrupts_cm0_cti_1_IRQHandler
cpuss_interrupts_cm4_cti_0_IRQHandler
cpuss_interrupts_cm4_cti_1_IRQHandler
tcpwm_0_interrupts_0_IRQHandler
tcpwm_0_interrupts_1_IRQHandler
tcpwm_0_interrupts_2_IRQHandler
tcpwm_0_interrupts_3_IRQHandler
tcpwm_0_interrupts_4_IRQHandler
tcpwm_0_interrupts_5_IRQHandler
tcpwm_0_interrupts_6_IRQHandler
tcpwm_0_interrupts_7_IRQHandler
tcpwm_1_interrupts_0_IRQHandler
tcpwm_1_interrupts_1_IRQHandler
tcpwm_1_interrupts_2_IRQHandler
tcpwm_1_interrupts_3_IRQHandler
tcpwm_1_interrupts_4_IRQHandler
tcpwm_1_interrupts_5_IRQHandler
tcpwm_1_interrupts_6_IRQHandler
tcpwm_1_interrupts_7_IRQHandler
tcpwm_1_interrupts_8_IRQHandler
tcpwm_1_interrupts_9_IRQHandler
tcpwm_1_interrupts_10_IRQHandler
tcpwm_1_interrupts_11_IRQHandler
tcpwm_1_interrupts_12_IRQHandler
tcpwm_1_interrupts_13_IRQHandler
tcpwm_1_interrupts_14_IRQHandler
tcpwm_1_interrupts_15_IRQHandler
tcpwm_1_interrupts_16_IRQHandler
tcpwm_1_interrupts_17_IRQHandler
tcpwm_1_interrupts_18_IRQHandler
tcpwm_1_interrupts_19_IRQHandler
tcpwm_1_interrupts_20_IRQHandler
tcpwm_1_interrupts_21_IRQHandler
tcpwm_1_interrupts_22_IRQHandler
tcpwm_1_interrupts_23_IRQHandler
pass_interrupt_sar_IRQHandler
audioss_0_interrupt_i2s_IRQHandler
audioss_0_interrupt_pdm_IRQHandler
audioss_1_interrupt_i2s_IRQHandler
profile_interrupt_IRQHandler
smif_interrupt_IRQHandler
usb_interrupt_hi_IRQHandler
usb_interrupt_med_IRQHandler
usb_interrupt_lo_IRQHandler
sdhc_0_interrupt_wakeup_IRQHandler
sdhc_0_interrupt_general_IRQHandler
sdhc_1_interrupt_wakeup_IRQHandler
sdhc_1_interrupt_general_IRQHandler
B .
ENDP
ALIGN
END
; [] END OF FILE

448
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
View File

@ -1,448 +0,0 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.60
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10180000
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START (MBED_ROM_START)
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x80000
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system.
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08080000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x7F800
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

673
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S
View File

@ -1,673 +0,0 @@
/**************************************************************************//**
* @file startup_psoc6_02_cm4.S
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
.long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
.long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
.long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
.long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
.long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
.long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
.long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
.long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
.long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
.long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
.long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
.long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
.long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
.long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
.long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
.long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
.long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
.long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
.long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
.long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
.long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
.long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
.long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
.long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
.long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
.long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
.long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
.long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
.long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
.long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
.long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
.long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
.long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
.long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
.long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
.long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
.long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
.long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
.long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
.long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
.long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
/* Enable the FPU if used */
bl Cy_SystemInitFpuEnable
bl _start
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_fault_Handler MemManage_Handler
def_fault_Handler BusFault_Handler
def_fault_Handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.end
/* [] END OF FILE */

274
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
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@ -1,274 +0,0 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.icf
* \version 2.60
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10180000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = (MBED_ROM_START);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x80000;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x08080000;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x7F800;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { block RAM};
place in IRAM1_region { block HEAP};
place at end of IRAM1_region { block CSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00200000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

1263
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S
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552
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c
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/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdbool.h>
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
#include "cy_ipc_drv.h"
#if defined(CY_DEVICE_PSOC6ABLE2)
#include "cy_flash.h"
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
/*******************************************************************************
* SystemCoreClockUpdate()
*******************************************************************************/
/** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
* processor core clock.
* This variable implements CMSIS Core global variable.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* This variable can be used by debuggers to query the frequency
* of the debug timer or to configure the trace clock speed.
*
* \attention Compilers must be configured to avoid removing this variable in case
* the application program is not using it. Debugging systems require the variable
* to be physically present in memory so that it can be examined to configure the debugger. */
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
/*******************************************************************************
* SystemInit()
*******************************************************************************/
/* CLK_FLL_CONFIG default values */
#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/*******************************************************************************
* SystemCoreClockUpdate (void)
*******************************************************************************/
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**
* \cond
* Initializes the system:
* - Restores FLL registers to the default state for single core devices.
* - Unlocks and disables WDT.
* - Calls Cy_PDL_Init() function to define the driver library.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
* \endcond
*******************************************************************************/
void SystemInit(void)
{
Cy_PDL_Init(CY_DEVICE_CFG);
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Restore FLL registers to the default state as they are not restored by the ROM code */
uint32_t copy = SRSS->CLK_FLL_CONFIG;
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
SRSS->CLK_FLL_CONFIG = copy;
copy = SRSS->CLK_ROOT_SELECT[0u];
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
SRSS->CLK_ROOT_SELECT[0u] = copy;
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
/* Unlock and disable WDT */
Cy_WDT_Unlock();
Cy_WDT_Disable();
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
Cy_SystemInit();
SystemCoreClockUpdate();
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Allocate and initialize semaphores for the system operations. */
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
#else
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
#endif /* (__CM0P_PRESENT) */
#else
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
#endif /* __CM0P_PRESENT */
/********************************************************************************
*
* Initializes the system pipes. The system pipes are used by BLE and Flash.
*
* If the default startup file is not used, or SystemInit() is not called in your
* project, call the following three functions prior to executing any flash or
* EmEEPROM write or erase operation:
* -# Cy_IPC_Sema_Init()
* -# Cy_IPC_Pipe_Config()
* -# Cy_IPC_Pipe_Init()
* -# Cy_Flash_Init()
*
*******************************************************************************/
/* Create an array of endpoint structures */
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
{
/* .ep0ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
},
/* .ep1ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
/* .ipcNotifierMuxNumber */ 0u,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
},
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**
*
* The function is called during device startup. Once project compiled as part of
* the PSoC Creator project, the Cy_SystemInit() function is generated by the
* PSoC Creator.
*
* The function generated by PSoC Creator performs all of the necessary device
* configuration based on the design settings. This includes settings from the
* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
* configuration that is necessary.
*
*******************************************************************************/
__WEAK void Cy_SystemInit(void)
{
/* Empty weak function. The actual implementation to be in the PSoC Creator
* generated strong function.
*/
}
/*******************************************************************************
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
*
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
/*******************************************************************************
* Function Name: Cy_SystemInitFpuEnable
****************************************************************************//**
*
* Enables the FPU if it is used. The function is called from the startup file.
*
*******************************************************************************/
void Cy_SystemInitFpuEnable(void)
{
#if defined (__FPU_USED) && (__FPU_USED == 1U)
uint32_t interruptState;
interruptState = Cy_SysLib_EnterCriticalSection();
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
__DSB();
__ISB();
Cy_SysLib_ExitCriticalSection(interruptState);
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
}
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/*******************************************************************************
* Function Name: Cy_SysIpcPipeIsrCm4
****************************************************************************//**
*
* This is the interrupt service routine for the system pipe.
*
*******************************************************************************/
void Cy_SysIpcPipeIsrCm4(void)
{
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
}
#endif
/*******************************************************************************
* Function Name: Cy_MemorySymbols
****************************************************************************//**
*
* The intention of the function is to declare boundaries of the memories for the
* MDK compilers. For the rest of the supported compilers, this is done using
* linker configuration files. The following symbols used by the cymcuelftool.
*
*******************************************************************************/
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
__asm void Cy_MemorySymbols(void)
{
/* Flash */
EXPORT __cy_memory_0_start
EXPORT __cy_memory_0_length
EXPORT __cy_memory_0_row_size
/* Working Flash */
EXPORT __cy_memory_1_start
EXPORT __cy_memory_1_length
EXPORT __cy_memory_1_row_size
/* Supervisory Flash */
EXPORT __cy_memory_2_start
EXPORT __cy_memory_2_length
EXPORT __cy_memory_2_row_size
/* XIP */
EXPORT __cy_memory_3_start
EXPORT __cy_memory_3_length
EXPORT __cy_memory_3_row_size
/* eFuse */
EXPORT __cy_memory_4_start
EXPORT __cy_memory_4_length
EXPORT __cy_memory_4_row_size
/* Flash */
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
__cy_memory_0_row_size EQU 0x200
/* Flash region for EEPROM emulation */
__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
__cy_memory_1_row_size EQU 0x200
/* Supervisory Flash */
__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
__cy_memory_2_row_size EQU 0x200
/* XIP */
__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
__cy_memory_3_row_size EQU 0x200
/* eFuse */
__cy_memory_4_start EQU __cpp(0x90700000)
__cy_memory_4_length EQU __cpp(0x100000)
__cy_memory_4_row_size EQU __cpp(1)
}
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
/* [] END OF FILE */

680
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h
View File

@ -1,680 +0,0 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _SYSTEM_PSOC6_H_
#define _SYSTEM_PSOC6_H_
/**
* \addtogroup group_system_config
* \{
* Provides device startup, system configuration, and linker script files.
* The system startup provides the followings features:
* - See \ref group_system_config_device_initialization for the:
* * \ref group_system_config_dual_core_device_initialization
* * \ref group_system_config_single_core_device_initialization
* - \ref group_system_config_device_memory_definition
* - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps
* - \ref group_system_config_default_handlers
* - \ref group_system_config_device_vector_table
* - \ref group_system_config_cm4_functions
*
* \section group_system_config_configuration Configuration Considerations
*
* \subsection group_system_config_device_memory_definition Device Memory Definition
* The flash and RAM allocation for each CPU is defined by the linker scripts.
* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
* For Single-Core devices the system reserves additional 80 bytes of RAM.
* Using the reserved memory area for other purposes will lead to unexpected behavior.
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see warnings during the build process. To eliminate build
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* <b>ARM MDK</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see the warnings during the build process:
* L6314W (no section matches pattern) and/or L6329W
* (pattern only matches removed unused sections). In your project, you can
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
* the linker. You can also comment out or remove the relevant code in the linker
* file.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code
* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
* code passes the control to the Cortex-M0+ startup code located in flash.
*
* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
* The Cortex-M0+ startup code performs the device initialization by a call to
* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
* See \ref group_system_config_cm4_functions for more details.
* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
* The function has a separate implementation on each core.
* Both function implementations unlock and disable the WDT.
* Therefore enable the WDT after both cores have been initialized.
*
* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
* The Cortex-M0+ core is not user-accessible on these devices. In this case the
* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
*
* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
* There are two ways to adjust heap and stack configurations:
* -# Editing source code files
* -# Specifying via command line
*
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
*
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* Change the heap and stack sizes by modifying the following lines:\n
* \code .equ Stack_Size, 0x00001000 \endcode
* \code .equ Heap_Size, 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n
* \code -D __STACK_SIZE=0x000000400 \endcode
* \code -D __HEAP_SIZE=0x000000100 \endcode
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the
* linker (including quotation marks):\n
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
*
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default
* values.
*
* The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific.
*
* The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data.
*
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
* user code by defining the handler function using the same name. For example:
* \code
* void scb_0_interrupt_IRQHandler(void)
*{
* ...
*}
* \endcode
*
* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
* This process uses memory sections defined in the linker script. The startup
* code actually defines the contents of the vector table and performs the copy.
* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* It defines sections and locations in memory.\n
* Copy interrupt vectors from flash to RAM: \n
* From: \code LONG (__Vectors) \endcode
* To: \code LONG (__ram_vectors_start__) \endcode
* Size: \code LONG (__Vectors_End - __Vectors) \endcode
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* The code in these files copies the vector table from Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \subsubsection group_system_config_device_vector_table_iar IAR
* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* This file defines the .intvec_ram section and its location.
* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_more_information More Information
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
* more details.
*
* \section group_system_config_MISRA MISRA Compliance
*
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
* <th>Rule Class (Required/Advisory)</th>
* <th>Rule Description</th>
* <th>Description of Deviation(s)</th>
* </tr>
* <tr>
* <td>2.3</td>
* <td>R</td>
* <td>The character sequence // shall not be used within a comment.</td>
* <td>The comments provide a useful WEB link to the documentation.</td>
* </tr>
* </table>
*
* \section group_system_config_changelog Changelog
* <table class="doxtable">
* <tr>
* <th>Version</th>
* <th>Changes</th>
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
* </tr>
* <tr>
* <td>2.40</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Added Arm Compiler 6 support.</td>
* </tr>
* <tr>
* <td rowspan="2">2.30</td>
* <td>Added assembler files, linker scripts for Mbed OS.</td>
* <td>Added Arm Mbed OS embedded operating system support.</td>
* </tr>
* <tr>
* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
* <td>Enhanced PDL usability.</td>
* </tr>
* <tr>
* <td>2.20</td>
* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
* <td>Changed the IPC driver configuration method from compile time to run time.</td>
* </tr>
* <tr>
* <td rowspan="2"> 2.10</td>
* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
* Removed $Sub$$main symbol for ARM MDK compiler.
* </td>
* <td>uVision Debugger support.</td>
* </tr>
* <tr>
* <td>Updated description of the Startup behavior for Single-Core Devices. \n
* Added note about WDT disabling by SystemInit() function.
* </td>
* <td>Documentation improvement.</td>
* </tr>
* <tr>
* <td rowspan="4"> 2.0</td>
* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
* Single core device support.
* </td>
* <td></td>
* </tr>
* <tr>
* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
* Renamed 'wflash' memory region to 'em_eeprom'.
* </td>
* <td>Linker scripts usability improvement.</td>
* </tr>
* <tr>
* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
* <td>Reserved system resources for internal operations.</td>
* </tr>
* <tr>
* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
*
* \defgroup group_system_config_macro Macro
* \{
* \defgroup group_system_config_system_macro System
* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
* \defgroup group_system_config_user_settings_macro User Settings
* \}
* \defgroup group_system_config_functions Functions
* \{
* \defgroup group_system_config_system_functions System
* \defgroup group_system_config_cm4_functions Cortex-M4 Control
* \}
* \defgroup group_system_config_globals Global Variables
*
* \}
*/
/**
* \addtogroup group_system_config_system_functions
* \{
* \details
* The following system functions implement CMSIS Core functions.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* \}
*/
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Include files
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
* Global preprocessor symbols/macros ('define')
*******************************************************************************/
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
#define CY_SYSTEM_CPU_CM0P 1UL
#else
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
* START OF USER SETTINGS HERE
* ===========================
*
* All lines with '<<<' can be set by user.
*
*******************************************************************************/
/**
* \addtogroup group_system_config_user_settings_macro
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
* <i>(USER SETTING)</i>
*******************************************************************************/
#if !defined (CY_CORTEX_M4_APPL_ADDR)
#define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
#endif /* (CY_CORTEX_M4_APPL_ADDR) */
/***************************************************************************//**
* \brief IPC Semaphores allocation ([value]UL).
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
/***************************************************************************//**
* \brief IPC Pipe definitions ([value]UL).
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
/*******************************************************************************
*
* END OF USER SETTINGS HERE
* =========================
*
*******************************************************************************/
/** \} group_system_config_user_settings_macro */
/**
* \addtogroup group_system_config_system_macro
* \{
*/
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M0+ startup driver identifier */
#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M4 startup driver identifier */
#define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
/** \} group_system_config_system_macro */
/**
* \addtogroup group_system_config_system_functions
* \{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/** \} group_system_config_system_functions */
/**
* \addtogroup group_system_config_cm4_functions
* \{
*/
extern uint32_t Cy_SysGetCM4Status(void);
extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
extern void Cy_SysDisableCM4(void);
extern void Cy_SysRetainCM4(void);
extern void Cy_SysResetCM4(void);
/** \} group_system_config_cm4_functions */
/** \cond */
extern void Default_Handler (void);
void Cy_SysIpcPipeIsrCm0(void);
void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
/** \endcond */
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/**
* \addtogroup group_system_config_cm4_status_macro
* \{
*/
#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
/** \} group_system_config_cm4_status_macro */
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
/*******************************************************************************
* IPC Configuration
* =========================
*******************************************************************************/
/* IPC CY_PIPE default configuration */
#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
/*
* The System pipe configuration defines the IPC channel number, interrupt
* number, and the pipe interrupt mask for the endpoint.
*
* The format of the endPoint configuration
* Bits[31:16] Interrupt Mask
* Bits[15:8 ] IPC interrupt
* Bits[ 7:0 ] IPC channel
*/
/* System Pipe addresses */
/* CyPipe defines */
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
/** \addtogroup group_system_config_globals
* \{
*/
extern uint32_t SystemCoreClock;
extern uint32_t cy_BleEcoClockFreqHz;
extern uint32_t cy_Hfclk0FreqHz;
extern uint32_t cy_PeriClkFreqHz;
/** \} group_system_config_globals */
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
/* BWC defines for functions related to enter/exit critical section */
#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
/** \endcond */
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_PSOC6_H_ */
/* [] END OF FILE */

49
targets/targets.json
View File

@ -9377,55 +9377,6 @@
"network-default-interface-type": "WIFI"
}
},
"CYSBSYSKIT_01": {
"inherits": [
"MCU_PSOC6_M4"
],
"components_add": [
"SCL",
"43012",
"CYW43XXX"
],
"device_has_remove": [
"ANALOGOUT"
],
"components_remove": [
"CM0P_SLEEP"
],
"extra_labels_add": [
"PSOC6_02",
"MXCRYPTO_02"
],
"macros_add": [
"CY8C624AFNI_D43",
"CYBSP_WIFI_CAPABLE"
],
"overrides": {
"network-default-interface-type": "WIFI",
"deep-sleep-latency": 0
},
"detect_code": [
"1912"
],
"macros_remove": [
"CYBSP_WIFI_CAPABLE",
"MBED_TICKLESS"
],
"config": {
"np_cloud_disable": {
"help": "Value: Tells the np to connect to cloud or not",
"value": false
},
"np_wifi_enable": {
"help": "Value: Tells the np to connect to wifi with its network credentials or wait till cp provides network credentials to it",
"value": false
}
},
"forced_reset_timeout": 5,
"post_binary_hook": {
"function": "PSOC6Code.complete"
}
},
"FUTURE_SEQUANA_M0": {
"inherits": ["MCU_PSOC6_M0"],
"supported_form_factors": ["ARDUINO"],