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83 Commits (9a1d05551ba785a158b260796b80b78757060321)

Author SHA1 Message Date
Sam Grove d11289b576 Merge pull request #4165 from adustm/can_init 
fix #3863 Add an mbed API that allows the init of the CAN at the bus frequency
 2017-05-26 10:45:19 -05:00
adustm 3d44a3fcc3 add can_init_freq for NUVOTON platforms 2017-05-15 14:27:22 +02:00
ccli8 08c778d18d [NUC472/M453] Change comment for serial_getc/serial_putc 2017-05-09 09:22:41 +08:00
ccli8 e7b737ddad [NUC472/M453] Fix serial error with sync/async calls interlaced 
Serial implementation uses different vector handlers for sync/async calls respectively. The issue can be reproduced with the following flow:
1. Register sync mode callback with Serial.attach().
2. Sync call with Serial.putc()/getc().
3. Change to async call with Serial.write()/read().
4. Change back to sync call with Serial.putc()/getc().
Now, vector handller is still for async mode, not for sync mode.

To fix it:
1. Introduce internal function serial_enable_interrupt() for both sync/async vector handler enable/disable.
   Original HAL function serial_irq_set() is reduced to call it for sync mode vector handler enable/disable.
2. Introduce internal function serial_rollback_interrupt() to roll back sync mode vector handler at end of async transfer.
 2017-05-02 09:31:09 +08:00
ccli8 32a7e6ba5e [NUC472/M453] Fix pwmout power-down condition 2017-04-20 16:13:37 +08:00
ccli8 e55553e749 [NUC472/M453] Fix DMA channel over-allocate 2017-04-20 14:57:09 +08:00
ccli8 40a9852608 [NUC472] Fix flash algorithm 
1. Remove setting of not released register ICPCON
2. Enable FMC_APUEN to update APROM
 2017-04-05 11:10:48 +08:00
cyliangtw b55708ec65 [NUC472] remove stray tabs to avoid formatting slips 2017-03-30 09:17:35 +08:00
cyliangtw c9e9052c5d [NUC472/M453] remove redundant comment of flash_api 2017-03-23 20:43:52 +08:00
cyliangtw ab814661e5 [NUC472/M453] Fixed scatterAssert of ROM limit 2017-03-23 15:25:08 +08:00
cyliangtw c1b8509b23 [NUC472] Enable HW AES 2017-03-23 10:03:58 +08:00
cyliangtw 1e163e8848 [NUC472/M453] Support bootloader 2017-03-23 09:54:03 +08:00
ccli8 d554f6e4e0 [NUC472/M453] Support flash 2017-03-23 09:54:03 +08:00
ccli8 5720725a3d [NUC472/M453] Refine serial PDMA code 2017-03-10 16:18:14 +08:00
ccli8 502e8ce2a5 [NUC472/M453] Refine SPI PDMA code 2017-03-10 16:18:14 +08:00
ccli8 867072fe70 [NUC472/M453] Add dma_modbase() to get PDMA base address 2017-03-10 16:18:14 +08:00
ccli8 49a2a221a4 [NUC472/M453] Fix pwmout power-down condition 2017-03-10 16:18:14 +08:00
ccli8 4e96f8b721 [NUC472/M453] Fix PDMA error on timeout 2017-03-10 16:18:14 +08:00
ccli8 1da33e809f [NUC472/M453] Refine pin/peripheral/pin map definitions 
Change NUC472 analogin_api.c accordingly
 2017-03-10 16:18:14 +08:00
ccli8 4e4c294fa3 [NUC472/M453] Fix incorrect use of peripheral name as peripheral base address 2017-03-10 16:18:14 +08:00
Christopher Haster aff49d8d1e Renamed files in platform to match source names 
critical.h     -> mbed_critical.h
sleep.h        -> mbed_sleep.h
toolchain.h    -> mbed_toolchain.h
rtc_time.h     -> mbed_rtc_time.h
semihost_api.h -> mbed_semihost_api.h
wait_api.h     -> mbed_wait_api.h
 2017-02-22 18:17:54 -06:00
ccli8 0bd8fb22c4 [NUC472] Support no-XRAM configuration 2017-02-14 09:12:02 +08:00
Sam Grove d8151d7991 Merge pull request #3590 from OpenNuvoton/nuvoton 
[NUC472/M453] Export IAR project and other bugfixes
 2017-02-13 10:12:02 -06:00
Bartek Szatkowski 6a045a49a9 Platform: Add sleep/deepsleep user facing functions 
Add sleep/deepsleep functions to platform layer which are replacing HAL
functions with the same name, rename existing symbols in HAL layer
to hal_sleep/hal_deepsleep. This way sleep functions
are always available, even if target doesn't implement them, which makes
the code using sleep clearer. It also enables us to make decision on in
which builds (debug/release) the sleep will be enabled.
 2017-01-19 09:39:29 +00:00
ccli8 0a0b326da6 [NUC472/M453] Change sbrk() allocation to be 32-byte aligned 2017-01-16 09:48:27 +08:00
ccli8 453f60e9c1 [NUC472/M453] Remove power-down support from us_ticker 2017-01-16 09:48:21 +08:00
Martin Kojtal e7361ebc44 Merge pull request #3365 from OpenNuvoton/nuvoton_usb 
[NUC472/M453] Support USB device
 2016-12-30 12:43:53 +01:00
ccli8 fff8357c1e [NUC472] Fix compile error with Travis CI 
Use MBED_CONF_RTOS_PRESENT to filter out mbedtls alternative for mbed OS 2.
 2016-12-15 11:43:43 +08:00
cyliangtw e4a5401b9b [NUC472/M453] Fix GCC warnings 2016-12-13 15:41:41 +08:00
ccli8 64e27b2e3d [NUC472/M453] Fix stuck in lp_ticker_init() 2016-12-13 11:10:51 +08:00
cyliangtw ec945db013 [NUC472] Resolve TRNG GCC warning 2016-12-13 11:10:51 +08:00
ccli8 3ff2df1875 [NUC472] Fix compile error for SHA-256 alternative on some condition 
Also include non-issue refinement for SHA-1/SHA-256 alternatives.
 2016-12-13 11:10:51 +08:00
ccli8 6af60f9b32 [NUC472/M453] Fix PWM clock error in BSP driver 2016-12-13 11:10:51 +08:00
ccli8 f796eb5d2d [NUC472/M453] Change UART RTS/CTS to low level active 2016-12-13 11:10:51 +08:00
ccli8 59e38666ae [NUC472/M453] Fix serial async transfer failed as data with is 16/32 2016-12-13 11:10:51 +08:00
ccli8 8c0948d605 [NUC472/M453] Integrate with Travis CI 
1. Add targets into build_travis.py and tests.py.
2. Add target SPI pins into SPI SD test samples.
3. Rename target TOOLCHAIN_GCC_ARM/retarget.c to avoid name collision of compiled retarget.o with platform/retargets.cpp.
 2016-12-09 13:46:38 +08:00
ccli8 7f4881fbb2 [NUC472/M453] Support USB device 2016-12-05 15:12:15 +08:00
ccli8 e1995dbe79 [NUC472/M453] Fix spi_master_transfer failed as bit width is 32 2016-11-25 15:32:25 +08:00
ccli8 137053343e [M453] Fix button naming error 2016-11-23 14:35:09 +08:00
ccli8 d24c71fad9 [NUC472/M453] Correct return of i2c_byte_write() on NAK 2016-11-22 13:45:01 +08:00
ccli8 57a22cd4ab [NUC472/M453] Fix CI I2C EEPROM failed 2016-11-22 09:56:54 +08:00
ccli8 f4890f68f1 [NUC472] Remove SPI MOSI1 and MISO1 pins from pinmap 
These pins are for SPI 2-bit mode (not dual mode) and cannot be for SPI standard use.
 2016-11-22 09:56:54 +08:00
ccli8 6c1fca60a5 [M453] Remove SPI MOSI1 and MISO1 pins from pinmap 
These pins are for SPI 2-bit mode (not dual mode) and cannot be for SPI standard use.
 2016-11-22 09:56:54 +08:00
ccli8 e1acb06d05 [NUC472] Rename variable name in analog-in 2016-11-22 09:56:53 +08:00
ccli8 bb1617c5f8 [M453] Fix EADC module is initialized multiple times 
Also fix EADC module name EADC is hardcoded.
 2016-11-22 09:56:53 +08:00
ccli8 35b2ad5a2c [NUC472] Fix CI tests-api-analogin failed 
1. Fix UNO pins A5-A7 don't support analog-in by replacing ADC with EADC to implement analog-in HAL.
2. Update CLK driver to fix EADC clock divider setting error. Also fix CLK_Idle() together.
 2016-11-22 09:56:53 +08:00
ccli8 fe883d42ab [M453] Fix CI tests-api-analogin failed 
1. Fix ADC convert finish check error.
2. Set ADC Vref to internal by default.
 2016-11-22 09:56:53 +08:00
ccli8 e0f97e5c80 [NUC472/M453] Support separate enable of GPIO IRQ de-bounce 2016-11-22 09:56:53 +08:00
ccli8 657d90db2c [NUC472/M453] Fix I2C issues 
1. Fix error on return of i2c_byte_write().
2. Fix error in zero-length transfer corner case.
 2016-11-22 09:56:53 +08:00
ccli8 4ae76be2ce [NUC472/M453] Reduce (interrupt) stack size from 4 KB to 2 KB 2016-11-07 12:28:20 +08:00