Commit Graph

30 Commits (926423c109219e759a19b5c150fd9c3f5424d56b)

Author SHA1 Message Date
Przemyslaw Stekiel f6acb51893 Update find_ports() FPGA testing utility function to loop through the form factor pins instead the pin-map
This change is required to fully remove gpio pin-maps which were already added for FPGA testing.
One use case of adding gpio pinmap was that pin-map must have the specific format - must be ended with NC pin. Functions that deal with pin-maps loops through the pin-map until NC pin is encountered.
Also, our FPGA testing utility function to find pins for testing does that. When gpio pinmaps are fully removed we will have one generic gpio pinmap which provides Arduino pins: D0, D1, D2, etc. (only Arduino form factor is supported at the moment).
In some cases may happen that an arduino pin is not connected (e.g. KW24D: D4 == NC). As a result we will have NC not only at the end, but also in the middle of the gpio pin-map.
In this case find_ports() function will finish processing pin-map to early (when first NC is encountered).
The proposition is to change the find_ports() FPGA testing utility function to loop through form factor pins (instead pin-map) and then check if the pin is not NC and is available on the specific pin-map before using it for testing.
2020-02-24 14:44:33 +01:00
Przemyslaw Stekiel 0d9a54f92e Provide pinmap_uart_restricted_peripherals() function under DEVICE_SERIAL 2020-02-10 08:17:55 +01:00
Przemyslaw Stekiel 3c0982d939 Add pinmap_gpio_restricted_pins() to provide list of restricted GPIO pins
This is a special case since targets do not provide by default GPIO pin-maps.
This extension is required for FPGA GPIO tests - if some pins have limitations (e.g. fixed pull-up) we need to skip these pins while testing.
To do that we were adding a dummy pin-map with commented out pins that can't be tested because of the limitations.
This solution is redundant and the proposition is to provide a list of restricted gpio pins if required (by default weak implementation is provided with an empty list).

This mechanism will be backward compatible, so the old method with dummy gpio pinmap will also work. The switch from dummy pin-maps to pinmap_gpio_restricted_pins() will be performed in separate commits/PRs.
2020-02-07 10:45:02 +01:00
Przemyslaw Stekiel 54f4777e64 Add STDIO UART as restricted for FPGA testing for all targets
Substantiation for this is that the STDIO UART peripheral is used by Mbed, so it should never be tested.

Also solve the potential problem with accidenty skipped peripherals in FPGA testing. Currently, we have a one `pinmap_restricted_peripherals()` function for all interfaces (UART, I2C, SPI, etc.).
The problem can be encountered if different interfaces have the same peripheral ids (e.g. `UART_0` = 0, `SPI_0` = 0). In this case, if `UART_0` is on the restricted list, then SPI tests will be also skipped for `SPI_0`.
The good news is that usually, the peripheral ids are the base addresses of the peripheral's register set, but we can't rely on this. It is also good that `pinmap_restricted_peripherals()` at this moment is only required for STDIO UART (Nuvoton and STM).

To solve this issue we will change name of `pinmap_restricted_peripherals()` to `pinmap_uart_restricted_peripherals()`, make STDIO UART restricted by default for all targets and update FPGA test utilily functions to use `pinmap_uart_restricted_peripherals()` to skip only uart peripherals.
In the future if needed we can consider to add support to restrict peripherals of other interfaces(SPI, I2C, etc).
2020-02-07 10:45:02 +01:00
jeromecoutant 0a1875924b FPGA_CI_TEST_SHIELD : force all peripheral to be tested 2020-01-21 17:17:55 +01:00
Hugues Kamba dbaeeaf758 Replace RawSerial instances as it has been deprecated 2020-01-06 15:48:49 +00:00
Filip Jagodzinski 5ee22d0c24 Test: FPGA shield: Fix GPIO-IRQ test_utils.h
Include the gpio_irq_api header to fix build failures.
2019-07-25 11:04:16 +02:00
Filip Jagodzinski 5e17eddf12 Test: FPGA shield: Update the GPIO-IRQ API tests
Use the gpio_irq_pinmap() for GPIO-IRQ testing.
2019-07-25 11:04:10 +02:00
Seppo Takalo c5c745804d
Merge pull request #11038 from fkjagodzinski/fpga_test-gpio
Extend the GPIO HAL API tests
2019-07-24 15:12:32 +03:00
Seppo Takalo 987533859a
Merge pull request #10104 from kjbracey-arm/sleep_api
Sleep rework, RTOS API for bare metal, wait deprecations
2019-07-17 14:37:53 +03:00
Seppo Takalo 5b6034d0a9
Merge pull request #11028 from c1728p9/fpga_warnings
Fix FPGA CI Test Shield warnings
2019-07-17 14:32:43 +03:00
Seppo Takalo 0425ffda9b
Merge pull request #11026 from c1728p9/skip_peripherals
Add a restricted peripheral list
2019-07-17 14:32:08 +03:00
Kevin Bracey a522dcfa0a Replace deprecated wait calls 2019-07-15 10:13:50 +03:00
Filip Jagodzinski 74be850126 Test: FPGA shield: Extend the GPIO HAL API tests 2019-07-12 14:01:57 +02:00
Russ Butler 87c6a74a21 Fix FPGA CI Test Shield warnings
Fix warnings due to unused variables, comparison between signed and
unsigned. This patch also re-enables I2C asserts that were disabled
during early development.
2019-07-11 16:16:34 +01:00
Russ Butler 57d75538da Add a restricted peripheral list
Allow peripherals to be excluded from testing.
2019-07-11 16:08:33 +01:00
Filip Jagodzinski ed41994a3a Test: HAL: serial: Add DEVICE_SERIAL_FC guards
Fix undefined references to serial_set_flow_control.
2019-07-09 13:21:42 +02:00
Maciej Bocianski a6353b0c92 I2CTester: fix dosc 2019-07-03 10:26:41 +02:00
Maciej Bocianski b65d93e5ef I2CTester: add address mismatch statistics 2019-07-03 10:05:53 +02:00
Maciej Bocianski fb589319bf I2CTester: upgrade checksum calculation 2019-07-02 20:00:31 +02:00
Martin Kojtal 48d23722fe
Merge pull request #10672 from c1728p9/fix_typos
Fix typos in the FPGA CI Test Shield component
2019-06-09 18:05:52 +01:00
Martin Kojtal 62698b903c
Merge pull request #10660 from mprse/fpga_ts_add_sckl_stats
Add SCLK and SIN stats to SPIMasterTester
2019-06-03 08:49:39 +01:00
Przemyslaw Stekiel 87902a8e76 Add SCLK and SIN stats to SPIMasterTester.
It has been found that there is a problem with the new K66F SPI driver when clock polarity is high.
After setting clock polarity to high SCLK line is still low. When transmission starts and CS is asserted (in case of manual CS handling) SCLK signal is invalid (low). After first transfer SCLK idle state becomes high.
SPI implementation on FPGA test shield is resistant on this bug and transmission is successful. The problem has been found on two boards communication test where transmission fails.

The idea is to add support to the FPGA test shield to catch such errors and verify this in the test.
2019-05-27 09:48:33 +02:00
Russ Butler 424c4d9feb Fix typos in the FPGA CI Test Shield component
Fix some typos.
2019-05-26 13:29:14 -05:00
Kevin Bracey 7ec1663dd7 FPGA_CI_TEST_SHIELD: C++11 fix 2019-05-24 16:26:15 +03:00
Russ Butler e2312c4ff4 Bring in more changes from FPGA repo
Bring in updates the the FPGA CI Test Shield repo.
2019-05-23 19:17:32 -05:00
Russ Butler 166ff13fe8 Add missing documentation
Add documentation to the MbedTester class and the test_utils.h file.
2019-05-08 13:15:42 -05:00
Russ Butler 45301ea718 Run astyle on all FPGA files
Run astyle to correct formatting.
2019-05-08 11:01:17 -05:00
Russ Butler 11bd96601b Remove inclusion of mbed.h from FPGA
And fix any build errors this caused.
2019-05-07 17:01:44 -05:00
Russ Butler b3332129b2 Check in files for the FPGA CI Test Shield
Bring all the FPGA CI Test Shield C and C++ driver files into mbed-os
as the component FPGA_CI_TEST_SHIELD. When this component is enabled
all the files that are needed to communicate with, update firmware on
and run testing with the FPGA are built.
2019-05-07 15:10:47 -05:00