Fix typos in the FPGA CI Test Shield component

Fix some typos.
pull/10672/head
Russ Butler 2019-05-26 13:29:14 -05:00
parent a4738fa9a8
commit 424c4d9feb
2 changed files with 4 additions and 4 deletions

View File

@ -55,7 +55,7 @@
* // Map D6 to LogicalPinGPIO0
* tester.pin_map_set(D6, MbedTester::LogicalPinGPIO0);
*
* // Toggle the LED
* // Toggle pin D6
* int toggle = 0;
* while (1) {
* tester.gpio_write(MbedTester::LogicalPinGPIO0, toggle, true);

View File

@ -234,7 +234,7 @@ void test_all_peripherals(std::list<PortType> &matched_ports, std::list<PortType
* - FormFactorType - The form factor to test on
* - f - The test function to run.
*
* This function is calls the test function multiple times with
* This function calls the test function multiple times with
* the appropriate combinations of pins.
*/
template<typename PortType, typename FormFactorType, typename PortType::TestFunctionType f>
@ -255,7 +255,7 @@ void all_ports()
* - FormFactorType - The form factor to test on
* - f - The test function to run.
*
* This function is calls the test function once for each peripheral
* This function calls the test function once for each peripheral
* of the given type.
*/
template<typename PortType, typename FormFactorType, typename PortType::TestFunctionType f>
@ -280,7 +280,7 @@ void all_peripherals()
* - FormFactorType - The form factor to test on
* - f - The test function to run.
*
* This function is calls the test function once for one peripheral
* This function calls the test function once for one peripheral
* of the given type.
*/
template<typename PortType, typename FormFactorType, typename PortType::TestFunctionType f>