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4761 Commits (79568dbe6dfac4206b51f72ddb8e82b2785d5ee4)

Author SHA1 Message Date
Laurent Meunier f903920f47 STM32WB: Fix ARM link error in mbed2 
In case of mbed2, BLE feature is not built.

As there is a MAPPING_TABLE in BLE feature which is not compiled in case
of mbed2, the linker reported the below error

[ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/
.link_script.sct", line 65 (column 6): Error: L6236E:
No section matches selector - no section to be FIRST/LAST.

Solution is to check whether BLE is enabled.
 2019-04-05 12:27:04 +01:00
Laurent Meunier 0dcddcea9b STM32WB: Adapt I2C timings 
for now based on L4+ cubeMX inputs
 2019-04-05 12:27:04 +01:00
Laurent Meunier 9e3d52d701 fixup! NUCLEO_WB55RG: add SDK files 2019-04-05 12:27:04 +01:00
Laurent Meunier 9345e5cbcb STM32WB: Add missing analogin_pinmap 
This is required since PR #9449
commit
"Add HAL API for analog in pinmap"
 2019-04-05 12:27:04 +01:00
Laurent Meunier 86c84050be Add WB support and CUBE FW version in readme.md 2019-04-05 12:27:04 +01:00
Laurent Meunier 91c08e3914 STM: fix minor warnings 2019-04-05 12:27:04 +01:00
Laurent Meunier 1a6cdf849f STM32WB: FIX LL RTC warning 2019-04-05 12:27:04 +01:00
Laurent Meunier e57771f375 STM32WB: Move STM32WB utilies from FEATURE_BLE to targets folder 
These files are not BLE specific, but also needed for some clock setting
for instance.

In order to compile an MBED2 application, we need to move the files.
 2019-04-05 12:27:04 +01:00
Laurent Meunier ee64f1543f NUCLEO_WB55RG: Rework Clock and sleep support 
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
 2019-04-05 12:27:04 +01:00
bcostm 2b257fabad NUCLEO_WB55RG: update targets.json 2019-04-05 12:27:03 +01:00
Laurent Meunier b5c30756f1 NUCLEO_WB55RG: IAR, ARM and GCC linker files alignment 
Align all scatter BLE shared memory declarations.
 2019-04-05 12:27:03 +01:00
jeromecoutant f913a31ad2 NUCLEO_WB55RG: HAL API updates to get SLEEP, RTC and LPTICKER OK 
- astyle OK
- file alignment with other families
- HSE, MSI, HSI clock support
- LPTICKER with RTC and LPTIM tested
 2019-04-05 12:27:03 +01:00
bcostm f07d570137 NUCLEO_WB55RG: update STM common files 
- Include RTC ll file from hal as in other families
- STM32WB: update Flash API driver
 2019-04-05 12:27:03 +01:00
bcostm 658c8b6fdb NUCLEO_WB55RG: update mbed_rtx.h 2019-04-05 12:27:03 +01:00
bcostm 0613359b6b NUCLEO_WB55RG: add SDK files 
- Contains files from STM32Cube_FW_WB_V1.0.0
 2019-04-05 12:27:02 +01:00
Ganesh Ramachandran f05b50ec6e Fixed support for DigitalOut(NC) instantiation 2019-04-05 12:27:02 +01:00
junichi.katsu@uhuru.jp 2f45444cfd added SPDX identifier and added the description of uhuru_raven_init function 2019-04-05 12:27:01 +01:00
junichi.katsu@uhuru.jp 6b2a219740 Add definition of RAVEN 2019-04-05 12:27:01 +01:00
Brian Daniels 160055c0fe Revert "Only enable ARMC6 for a few targets" 
These targets appear to run fine with ARMC5.

This reverts commit 2b75dfda0f.
 2019-04-05 12:27:00 +01:00
Vivek Pallantla c5a1ea3b6b PSOC: Modify lp_ticker to 32 bit 
Needed for PSoC to deep-sleep for more than 2 seconds
Max sleep with 16 bit lp_ticker (before this change) : 2sec
Max sleep with 32 bit lp_ticker (after this change)  : 36hours
 2019-04-05 12:27:00 +01:00
Lei Zhang 5f74415544 PSOC6: Rebuild WICED libraries 
- Modify WICED to RTOS priority mapping
 2019-04-05 12:27:00 +01:00
jeromecoutant ec36d2a16e STM32 ADC INTERNAL CHANNEL reset after read 
Internal channels use is enabling ADC "internal path"
which needs to be disabled after measurement
 2019-04-05 12:26:59 +01:00
Mahesh Mahadevan 7efc3eb841 LPC55S69: Update Flash driver to set clock frequency 
This is to ensure the flash access time is set correctly

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
 2019-04-05 12:26:58 +01:00
Vincent Veron 9a481bdca8 TARGET_STM32F7: Refresh cache when erasing or programming flash 
The cache must be refreshed when we erase or program flash memory.
It fix 2 issues :
    Fix #9934
    Fix #6380

This solution was initially proposed in #6380.

Signed-off-by: Vincent Veron <vincent.veron@st.com>
 2019-04-05 12:26:58 +01:00
ecoromka 313794cbc7 Fix tempsensor cal1 constant in stm32f3xx_ll_adc.h 
Fix TEMPSENSOR_CAL1_TEMP according to datasheet.
 2019-04-05 12:26:56 +01:00
d-kato fe1b368415 Refactoring system clock driver 2019-04-05 12:26:27 +01:00
d-kato 306ab7a650 Removed clock mode decision of "SystemCoreClockUpdate()" 
Since GPIO.PPR0 can not check clock mode, I changed it to set a fixed value for each board.
 2019-04-05 12:26:27 +01:00
d-kato 65a4de1c82 Fix the value of SystemCoreClock 
The OS timer of RZ/A1 uses P0 clock, so until now it has been set the value of P0 clock in SystemCoreClock.
Changed the system clock value to set to SystemCoreClock.
Changed to refer to P0 clock macro instead of SystemCoreClock in OS timer processing.
 2019-04-05 12:26:27 +01:00
ccli8 5ef3e077ba Add button names BUTTON1/BUTTON2 2019-04-05 12:26:27 +01:00
Oren Cohen ad79a3bd8e Define program_cycle_s for CY8CKIT_062_WIFI_BT 2019-04-05 12:26:26 +01:00
Oren Cohen be524bbb5d Define program_cycle_s for NXP LPC55S69 2019-04-05 12:26:26 +01:00
Michael Schwarcz 24a3b0cc74 LPC targets: Compile us_ticker.c only if USTICKER defined 2019-04-05 12:26:25 +01:00
Michael Schwarcz b130fae17e Add USTICKER to more targets 
- LPC4088
- LPC4088_DM
- MAX32600MBED
- NCS36510
- WIZWIKI_W7500
- WIZWIKI_W7500ECO
- WIZWIKI_W7500P
 2019-04-05 12:26:25 +01:00
Michael Schwarcz 83f9243362 Add USTICKER to ARCH_PRO target 2019-04-05 12:26:25 +01:00
Ryan Morse 9b9125a7f1 Fixed issue with PWM not being freed when the object is destroyed 2019-04-05 12:26:24 +01:00
Malavika Sajikumar 865a5dcf13 Renaming SDP-K1 to SDP_K1. 2019-04-05 12:26:24 +01:00
Malavika Sajikumar ad163d73e1 Disabling LPTICKER for now. Fixing a few more alignment issues. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar 792d3b09d2 Updating SPDX-License-Identifier. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar bb863b3109 Adding support for SDP connector pins. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar 41ba2da3d6 Fixing for Travis CI test fail. 5e9e140. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar 4b080876e9 Adding SPDX identifier (year 2019) to the license. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar 84fe82e78e Removing commented out lines. Added SDP connector pins. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar cfcefd347f Fixing alignment on the lines for SDP-K1 description. 2019-04-05 12:26:23 +01:00
Malavika Sajikumar 5b4b4386d0 Adding support for SDP-K1. 2019-04-05 12:26:22 +01:00
jeromecoutant 3c17155119 DISCO_L496AG: Add PMOD and STMOD+ connector 2019-04-05 12:26:20 +01:00
ccli8 2ab9540b80 Remove SD component from targets.json 
Nuvoton targets below don't provide SPI-bus SD on-board, identified by 'SD' in
target component list. Instead, these targets provide SD-bus SD on-board, identified
by unofficial 'NUSD', driver of which is provided outside mbed-os tree. So 'SD' must
be removed to reflect the truth.

- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NUMAKER_PFM_M2351
 2019-04-05 12:26:20 +01:00
Juho Eskeli e49d00fd71 MTB_STM_L475: fix UART clock 2019-04-05 12:26:19 +01:00
Ashok Rao 2daa3e6783 Removing redundant code. 
MCO pins are not brought out on MTB / MCB design.
 2019-04-05 12:26:18 +01:00
Ashok Rao 5e39bf8eec Adding STM32_F439 as a new MTB target 2019-04-05 12:26:18 +01:00
jeromecoutant 85d832eb9f STM32H7 ADC internal channels 2019-04-05 12:26:18 +01:00