Commit Graph

23857 Commits (79568dbe6dfac4206b51f72ddb8e82b2785d5ee4)

Author SHA1 Message Date
Laurent Meunier 79568dbe6d STM32WB: Set a random static address during init 2019-04-05 12:27:05 +01:00
Laurent Meunier dbfe97d649 STM32WB: add debug trace group in BLE Transport Layer 2019-04-05 12:27:05 +01:00
Laurent Meunier f903920f47 STM32WB: Fix ARM link error in mbed2
In case of mbed2, BLE feature is not built.

As there is a MAPPING_TABLE in BLE feature which is not compiled in case
of mbed2, the linker reported the below error

[ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/
.link_script.sct", line 65 (column 6): Error: L6236E:
No section matches selector - no section to be FIRST/LAST.

Solution is to check whether BLE is enabled.
2019-04-05 12:27:04 +01:00
Laurent Meunier 0dcddcea9b STM32WB: Adapt I2C timings
for now based on L4+ cubeMX inputs
2019-04-05 12:27:04 +01:00
Laurent Meunier 9e3d52d701 fixup! NUCLEO_WB55RG: add SDK files 2019-04-05 12:27:04 +01:00
Laurent Meunier 9345e5cbcb STM32WB: Add missing analogin_pinmap
This is required since PR #9449
commit
"Add HAL API for analog in pinmap"
2019-04-05 12:27:04 +01:00
Laurent Meunier 86c84050be Add WB support and CUBE FW version in readme.md 2019-04-05 12:27:04 +01:00
Laurent Meunier 91c08e3914 STM: fix minor warnings 2019-04-05 12:27:04 +01:00
Laurent Meunier 1a6cdf849f STM32WB: FIX LL RTC warning 2019-04-05 12:27:04 +01:00
Laurent Meunier e57771f375 STM32WB: Move STM32WB utilies from FEATURE_BLE to targets folder
These files are not BLE specific, but also needed for some clock setting
for instance.

In order to compile an MBED2 application, we need to move the files.
2019-04-05 12:27:04 +01:00
Laurent Meunier ee64f1543f NUCLEO_WB55RG: Rework Clock and sleep support
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
2019-04-05 12:27:04 +01:00
Laurent Meunier 879ca1db24 NUCLEO_WB55RG: add Cordio HCI and Transport Layer driver
The STM32WB Coridio driver includes:
- the Cordio HCI driver handling the reset sequence. During reset sequence
the TX POWER level is set and the BD address is defined if found in OTP
or option bytes. The rest of the sequence is based on the standard CORDIO
HCI driver example.
- The Transport Layer part handles sending and receiving messages to the
WB controller running on cortex-M0 of the STM32WB target. The messages
are shared through shared memory and mailboxes system based on IPCC HW.
2019-04-05 12:27:03 +01:00
Laurent Meunier e26eaa1c9d NUCLEO_WB55RG: WB Transport Layer Cube files modifications
- Need to force ARM packed redefinition
- Configure LL stack in LL mode only
- Remove warning in shci_tl.c (PLACE_IN_SECTION)
2019-04-05 12:27:03 +01:00
bcostm be1e80512e NUCLEO_WB55RG: add WB Cube files reused for BLE transport layer 2019-04-05 12:27:03 +01:00
bcostm 2b257fabad NUCLEO_WB55RG: update targets.json 2019-04-05 12:27:03 +01:00
Laurent Meunier b5c30756f1 NUCLEO_WB55RG: IAR, ARM and GCC linker files alignment
Align all scatter BLE shared memory declarations.
2019-04-05 12:27:03 +01:00
jeromecoutant f913a31ad2 NUCLEO_WB55RG: HAL API updates to get SLEEP, RTC and LPTICKER OK
- astyle OK
- file alignment with other families
- HSE, MSI, HSI clock support
- LPTICKER with RTC and LPTIM tested
2019-04-05 12:27:03 +01:00
bcostm f07d570137 NUCLEO_WB55RG: update STM common files
- Include RTC ll file from hal as in other families
- STM32WB: update Flash API driver
2019-04-05 12:27:03 +01:00
bcostm 658c8b6fdb NUCLEO_WB55RG: update mbed_rtx.h 2019-04-05 12:27:03 +01:00
bcostm 0613359b6b NUCLEO_WB55RG: add SDK files
- Contains files from STM32Cube_FW_WB_V1.0.0
2019-04-05 12:27:02 +01:00
Ganesh Ramachandran f05b50ec6e Fixed support for DigitalOut(NC) instantiation 2019-04-05 12:27:02 +01:00
Andrii Lishchynskyi 4f181324e8 Fix applying all possible setting 2019-04-05 12:27:02 +01:00
Andrii Lishchynskyi 4d33732fc7 Replace 'resolution_order_names' and 'extra_labels' with 'labels' Get rid of 'next' function 2019-04-05 12:27:01 +01:00
Andriy.Lishchynskyi b7676b36fe Enhancement to remove duplicates in Eclipse launch configurations 2019-04-05 12:27:01 +01:00
Kevin Bracey 550923d630 equeue: align passed-in buffer
Make equeue_create_inplace align the passed-in buffer and size to
sizeof(void *).

Really we should be aiming to align more for ARM, as blocks should be
8-byte aligned, but the internal heap mechanisms only work to 4-byte
alignment at the moment. More work would be needed to ensure 8-byte
alignment of allocated blocks.
2019-04-05 12:27:01 +01:00
junichi.katsu@uhuru.jp ce8f5ece3f added sectors information 2019-04-05 12:27:01 +01:00
junichi.katsu@uhuru.jp dee9192515 added STM32F767VI 2019-04-05 12:27:01 +01:00
junichi.katsu@uhuru.jp 2f45444cfd added SPDX identifier and added the description of uhuru_raven_init function 2019-04-05 12:27:01 +01:00
junichi.katsu@uhuru.jp 6b2a219740 Add definition of RAVEN 2019-04-05 12:27:01 +01:00
ccli8 eba8eec352 Support export IAR8 project
1. Override IlinkOverrideProgramEntryLabel and IlinkProgramEntryLabel to specify
   entry point for debuger.
2. Refer to doc at the link below for post-export steps. Usually, 'export' is nearly
   out of the box and just install 'Nu-Link Driver (IAR)' to update Nuvoton device
   database in IAR.
   https://github.com/OpenNuvoton/NuMaker-mbed-docs/blob/master/IAR/DEBUG_IAR.md
2019-04-05 12:27:01 +01:00
Brian Daniels 160055c0fe Revert "Only enable ARMC6 for a few targets"
These targets appear to run fine with ARMC5.

This reverts commit 2b75dfda0f.
2019-04-05 12:27:00 +01:00
paul-szczepanek-arm e607fe923f add default services first 2019-04-05 12:27:00 +01:00
jeromecoutant d627be3423 Build script: add explicit console log in case of linker script error 2019-04-05 12:27:00 +01:00
jeromecoutant 5233c388ea NUCLEO_L4R5ZI_P: enable sw4stm32 export 2019-04-05 12:27:00 +01:00
Teemu Kultala 5e4d6c96d0 cellular: valgrind defect fix
at_cellulardevicetest.cpp: fix potential memory leak
at_cellularsmstest.cpp: fix potential memory leak, uninitialized memory conditional
athandlertest.cpp: fix potential memory leak, uninitialized memory conditional,
uninitialized memory read
ATHandler_stub.cpp, ATHandler_stub.h: fix potential memory leak, uninitialized memory conditional
2019-04-05 12:27:00 +01:00
Vivek Pallantla c5a1ea3b6b PSOC: Modify lp_ticker to 32 bit
Needed for PSoC to deep-sleep for more than 2 seconds
Max sleep with 16 bit lp_ticker (before this change) : 2sec
Max sleep with 32 bit lp_ticker (after this change)  : 36hours
2019-04-05 12:27:00 +01:00
Kimmo Vaisanen a2857bac97 Cellular: Improve ATHandler AT traces
Original AT traces had several issue:
- Can be overwritten by other traces (printf/mbed-trace)
- No way to know which direction message was going (TX or RX)
- <cr> and <ln> characters were not visible in trace
etc.

This commit addresses those issues using mbed-trace and showing separately
each filehandle write and read.
2019-04-05 12:27:00 +01:00
Lei Zhang 5f74415544 PSOC6: Rebuild WICED libraries
- Modify WICED to RTOS priority mapping
2019-04-05 12:27:00 +01:00
Jan Jongboom 5333ab62a2 README link to license guide 404s
This updates the link
2019-04-05 12:26:59 +01:00
jeromecoutant ec36d2a16e STM32 ADC INTERNAL CHANNEL reset after read
Internal channels use is enabling ADC "internal path"
which needs to be disabled after measurement
2019-04-05 12:26:59 +01:00
mudassar-ublox 603808ea42 wait increased for all cases 2019-04-05 12:26:58 +01:00
mudassar-ublox dc1e1b20a3 power on wait increased for C030_U201 2019-04-05 12:26:58 +01:00
Mahesh Mahadevan 7efc3eb841 LPC55S69: Update Flash driver to set clock frequency
This is to ensure the flash access time is set correctly

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2019-04-05 12:26:58 +01:00
Jimmy Brisson 7d6a07e76e Parse errors and warnings with ARMC6 2019-04-05 12:26:58 +01:00
Vincent Veron 9a481bdca8 TARGET_STM32F7: Refresh cache when erasing or programming flash
The cache must be refreshed when we erase or program flash memory.
It fix 2 issues :
    Fix #9934
    Fix #6380

This solution was initially proposed in #6380.

Signed-off-by: Vincent Veron <vincent.veron@st.com>
2019-04-05 12:26:58 +01:00
David Saada ff6c6b9523 Remove CFSTORE VERSION file (colliding with an ARM 6.12 C++ header file) 2019-04-05 12:26:58 +01:00
Cruz Monrreal II‰ 93c9ec8c69 Updated AWS url for astyle. The original one is no longer appropriate 2019-04-05 12:26:58 +01:00
Offir Kochalsky 1a48962a53 Update QSPIFBlockDevice.cpp 2019-04-05 12:26:58 +01:00
offirko 665a80f671 If QER is undefined: do nothing but log warning and continue 2019-04-05 12:26:58 +01:00
offirko 27a306b91b Fixed Bus Mode bit mask to select best mode. When setting Quad Enable, either SR1, SR2 or CR setup is required. Either way register size is up to 2 bytes. 2019-04-05 12:26:57 +01:00