At IAR linking, the default method of 'initialize by copy' is 'auto', which will estimate
different packing algorithms, including complex 'lz77', for smallest memory footprint. But
the algorithm itself can consume some SRAM and cause OOM at linking time for NANO130, which
just has 16KiB SRAM. To avoid this error, always choose 'none' packing algorithm.
On ARMC6 with optimization level "-Os", the two functions NVIC_SetVector/NVIC_GetVector
will be translated to illegal instruction for trapping due to NVIC_FLASH_VECTOR_ADDRESS
defined as direct 0. Fixed by defining NVIC_FLASH_VECTOR_ADDRESS as a symbol instead to
avoid such optimization error.
Set the ISR stack to be 1KB. https://github.com/ARMmbed/mbed-os/pull/7238
Set the heap size to 3KB(2KB + overhead + spare) so that atleast 2KB free ram is
available for testing.
With dynamic heap size, explicit size is not required. IAR 7.8 supports
static heap, hence the change is needed in IAR linker files.
IAR 7.8 does not support dynamic heap, and some test/addition of new
feature fail on this device because of less static RAM memory.
Reducing the heap memory size for the same reason.
1. Support CMSIS_VECTAB_VIRTUAL feature
2. Reduce the register sync waiting time in LP ticker
3. Adjust the stack and heap size in GCC and IAR toolchains
Chun-Chieh Li
Deepika
MS30 CCChang12