Commit Graph

2574 Commits (6684570dea0402cfe5e7d654aedf1cceafd080ac)

Author SHA1 Message Date
Martin Kojtal 0ae6a048e4
Merge pull request #9431 from deepikabhavnani/iar_armv8m_changes
Update IAR Armv8M changes
2019-02-04 14:34:28 +01:00
Brian Daniels 811152da65
Add missing space - coding style nit
Co-Authored-By: deepikabhavnani <deepika.bhavnani@arm.com>
2019-02-01 10:38:37 -06:00
Martin Kojtal 7ba83a517d
Merge pull request #9342 from Cypress-OpenOCD/master
Add support for debug and program launch configurations
2019-02-01 08:10:20 +01:00
deepikabhavnani 6097095de4 Set the DSP option as `E` for Cortex-M33 2019-01-31 16:19:24 -06:00
deepikabhavnani fdbcae3830 Correct the floating+dsp options for Cortex-M processors
As per the IAR Development guide, below options for CPU are valid

1. Cortex-M33
2. Cortex-M33.no_dsp (core without integer DSP extension)
3. Cortex-M33.fp (floating-point unit with support for single precision)
4. Cortex-M33.no_se (core without support for TrustZone)
5. Cortex-M4
6. Cortex-M4F
7. Cortex-M7
8. Cortex-M7.fp.dp (floating-point unit with support for double precision)
9. Cortex-M7.fp.sp (floating-point unit with support for single precision)
2019-01-31 16:19:24 -06:00
deepikabhavnani 0082474ef2 Update `cmse` flag based on core_arch instead of different cores 2019-01-31 16:19:24 -06:00
Deepika 80f6b0e002 M2351: Update code to support IAR 8.x builds 2019-01-31 16:19:24 -06:00
deepikabhavnani f760f72757 Update IAR flags for Armv8M devices.
Cortex-M23 / Cortex-M33 CPU settings for baseline and mainline
profile (with optional floating and dsp options) updated.
2019-01-31 16:19:24 -06:00
Andriy.Lishchynskyi be5a625771 Resolved code review comments 2019-01-31 19:31:28 +02:00
Jimmy Brisson 020c840cf8
Apply suggestions from code review
Co-Authored-By: Cypress-OpenOCD <39907069+Cypress-OpenOCD@users.noreply.github.com>
2019-01-31 19:29:13 +02:00
Cruz Monrreal c9e00cf781
Merge pull request #9480 from deepikabhavnani/core_arch_v8m
Refactor core optional parameters (FPU + DSP + Security extensions)
2019-01-31 10:22:09 -06:00
Andriy.Lishchynskyi 6f584cd35e Added copyright notes 2019-01-31 16:31:02 +02:00
Martin Kojtal dbc3c6250b
Merge pull request #9487 from theamirocohen/add_sd_driver_example
Add sd-driver example
2019-01-31 11:22:59 +01:00
Martin Kojtal 9265c19e2e
Merge pull request #9394 from jeromecoutant/PR_PERIPH
STM32: PeripheralPins files update from lastest CubeMX tool version
2019-01-31 11:21:09 +01:00
Andriy.Lishchynskyi 48dfcd98a9 Changes:
- added new erase launch configuration
- added new kits support
- code cleanup
2019-01-30 19:48:20 +02:00
Martin Kojtal 93f0a09344
Merge pull request #9521 from cmonr/py3-tests-and-fixes
Py3 fixes and Travis CI enablement
2019-01-30 10:02:50 +01:00
Martin Kojtal 2a16bbdf98
Merge pull request #9496 from NXPmicro/Add_MXRT_IAR_Support
MIMXRT1050_EVK: Add IAR support in the exporter
2019-01-30 09:56:29 +01:00
Martin Kojtal 7d036b52cd
Merge pull request #9283 from michalpasztamobica/tlssocket_greentea
Add TLSSocket greentea tests.
2019-01-30 09:55:21 +01:00
Jimmy Brisson b836b340a2
Updated spm test runner wish short import variant
Co-Authored-By: cmonr <Cruz.Monrreal@arm.com>
2019-01-29 14:54:42 -06:00
Cruz Monrreal II de4b7607a0 Simplified max/min condition 2019-01-28 14:01:48 -06:00
Cruz Monrreal II 533dcf36ff Added universal_newlines flag to Popen in pylint.py 2019-01-28 12:59:43 -06:00
Cruz Monrreal II 2a9a45d087 Increased path for spm include.
Py3 tests were not running as a result
2019-01-28 12:59:43 -06:00
Cruz Monrreal II 149d280e7a Added encoding to version check for Py3 compat 2019-01-28 12:59:43 -06:00
Cruz Monrreal II cc3114113d In Py3.7, a reinit of a mock variable was needed.
It seems that initializing mock variables in an object isn't enough
2019-01-28 12:59:43 -06:00
Cruz Monrreal II d9add3447d Added None check for min in config tools 2019-01-28 12:59:43 -06:00
Cruz Monrreal II 72dbc52715 Added flag to run_cmd Popen invocation to do default decoding 2019-01-28 12:59:43 -06:00
Cruz Monrreal e965aa6640
Merge pull request #9509 from vmedcy/psoc6-daplink-hex
PSOC6.py: generate hex files with 16 bytes per row
2019-01-28 10:38:15 -06:00
Cruz Monrreal 7f8ebc75cd
Merge pull request #9466 from vmedcy/psoc6-target-hook
Improve PSoC 6 post-build hooks, whitelist makefile export
2019-01-28 10:33:12 -06:00
Volodymyr Medvid 5c384f10e7 PSOC6.py: generate hex files with 16 bytes per row
DAPLink implementation on Cypress kits cannot handle hex files
with 64 bytes per row: refer to https://github.com/ARMmbed/DAPLink,
source/daplink/drag-n-drop/intelhex.c, hex_line_t struct, data field.
2019-01-25 10:07:00 -08:00
deepikabhavnani febbeffff6 Change if statements to lookup tables 2019-01-25 09:43:03 -06:00
deepikabhavnani f7d49fdc82 Change DSP variant symbol to `E` from `D`(d-double floating point) 2019-01-25 09:31:44 -06:00
deepikabhavnani c472005cfa GCC_ARM: Strip the -NS from core option before setting floating point options 2019-01-25 09:28:36 -06:00
deepikabhavnani c0750de318 Armc6 - Set floating point and CPU options for all core variants explicitly
Below are the options read from the toolchains/arm
armclang --target=arm-arm-none-eabi -mcpu=list
The following arguments to option 'mcpu' can be selected:
  -mcpu=cortex-m0
  -mcpu=cortex-m0plus
  -mcpu=cortex-m1
  -mcpu=cortex-m3
  -mcpu=cortex-m4
  -mcpu=cortex-m7
  -mcpu=cortex-m23
  -mcpu=cortex-m33
  ...

armlink --cpu=list
The following arguments to option 'cpu' can be selected:
 --cpu=Cortex-M0
 --cpu=Cortex-M0plus
 --cpu=Cortex-M1
 --cpu=Cortex-M1.os_extension
 --cpu=Cortex-M1.no_os_extension
 --cpu=Cortex-M4
 --cpu=Cortex-M4.no_fp
 --cpu=Cortex-M7
 --cpu=Cortex-M7.fp.sp
 --cpu=Cortex-M7.no_fp
 --cpu=Cortex-M23
 --cpu=Cortex-M33
 --cpu=Cortex-M33.no_fp
 --cpu=Cortex-M33.no_dsp
 --cpu=Cortex-M33.no_dsp.no_fp
...

armclang --target=arm-arm-none-eabi -mfpu=list
The following arguments to option 'mfpu' can be selected:
  -mfpu=fpv4-sp-d16
  -mfpu=fpv5-sp-d16
  -mfpu=fpv5-d16
...
2019-01-25 09:28:36 -06:00
deepikabhavnani 907c517473 Use core arch for setting secure/non-secure flags 2019-01-25 09:28:36 -06:00
Cruz Monrreal 615ed31f7a
Merge pull request #9488 from 0xc0170/fix_licenses
Fix licenses in travis test and realtek lib
2019-01-24 16:16:38 -06:00
Mahesh Mahadevan aa449b3c5f MIMXRT1050_EVK: Add IAR support in the exporter
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2019-01-24 13:55:20 -06:00
Cruz Monrreal f69b550d5d
Merge pull request #9462 from deepikabhavnani/add_example
Corrected the targets value in json file as CI uses real board names
2019-01-24 13:27:46 -06:00
Kevin Gilbert ecdd1d7cb3 Add empty en_phonet.
Required to run with aspell and comply with license changes
2019-01-24 11:34:14 -06:00
Martin Kojtal 32e247d06f travis: remove phonedat database
Not permissive license
2019-01-24 12:28:22 +00:00
Amir Cohen f7ea4c9e67 Add sd-driver example 2019-01-24 13:34:35 +02:00
jeromecoutant 16028e3796 STM32_gen_PeripheralPins.py v1.5
Use dedicated PinMap for each QSPI data line #9438
2019-01-24 11:00:00 +01:00
jeromecoutant bdc91b0a9a STM32_gen_PeripheralPins.py v1.4
Minor updates:
- remove QSPI BK2
- beautifier edition
- use STM_MODE_ANALOG_ADC_CONTROL for L4 family
2019-01-24 10:25:36 +01:00
Cruz Monrreal 7bdc280ced
Merge pull request #9437 from deepikabhavnani/preprocess_asm
FPU_USED to be set based on HW FPU support + Squash commits
2019-01-23 22:48:21 -06:00
Andriy.Lishchynskyi 55a6ca5b1a Fix python3 compatibility issue 2019-01-23 23:25:20 +02:00
Martin Kojtal 129889bf52
Merge pull request #9404 from deepikabhavnani/dsp_flag
DSP_PRESENT flag is needed for Armv8m devices having DSP enabled
2019-01-23 14:21:23 +01:00
Martin Kojtal af52c30234
Merge pull request #9433 from deepikabhavnani/asm_v8m_flags
Set DSP and floating point flags for ASM files
2019-01-23 09:18:18 +01:00
Volodymyr Medvid a48ee113ea PSOC6: refactor M0 image merging, enable export to makefile
Rename the existing PSoC-specific m0_core_img key in targets.json
as a more generic hex_filename key. Update makefile exporter to select
the subset of resources.hex_files matching the hex_filename value.
Without this fix, multiple prebuilt CM0+ hex files are found in the
target resources and erroneously passed to the srec_cat tool.

The fix is generic so other targets that need post-build hex merging
can use this key to pass the correct image to srecord tool.

The fix also removes sub_target key: instead, rely hex_filename json
key to detect if the hex image merging needs to be done.
The sub_target is not used in mbed-os codebase for anything else.

It is possible to override the hex file name in mbed_app.json:
{
  "target_overrides": {
    "*": {
      "target.hex_filename": "my_custom_m0_image.hex"
    }
}
2019-01-22 15:40:22 -08:00
Volodymyr Medvid 5b0daadd18 PSOC6.py: do not require metadata during HEX merging
Replace hard-coded numeric offsets of PSoC 6 hex file sections
with sensible constants.
Do not attempt to update the checksum and metadata contents
if the sections are not found in the original HEX file.
2019-01-22 15:40:22 -08:00
Volodymyr Medvid 226edc1abd PSOC6.py: remove silicon ID check
PSoC 6 hex files contain 4-byte chip ID at virtual offset 0x90500002
added by PSoC Creator or cymcuelftool from .cymeta ELF section.
merge_images compares chip ID in CM0+ and CM4 hex files and raises
an exception in case of mismatch. Chip ID is different for each MPN
(for example, 0xE2072100 for CY8C6347BZI-BLD53 and 0xE2062100 for
CY8C6247BZI-D54). CM0+ prebuilt images target CY8C6347BZI-BLD53
but should be compatible with other PSoC6 MPNs.
Remove the check to enable merging CM0+ images with CM4 applications
built for different MPNs, with empty or absent cymetadata.
2019-01-22 15:40:22 -08:00
deepikabhavnani 2c062310cb Corrected the targets value in json file as CI uses real board names 2019-01-22 12:37:44 -06:00