In particular and as kindly suggested by Przemec S. :
1. Add setup/teardown handler’s for all cases. This disables sys-tick,
so there should be no unexpected lp ticker interrupt scheduling.
2. Modify setup/teardown handler’s: remove suspension of lp/us tickers,
so they can count as this is required by test_lock_unlock_test_check test
case.
3. Use TEST_ASSERT_TRUE(sleep_manager_can_deep_sleep_test_check()) after
setting interrupt to cope with STM specific handling (CMPOK interrupt with
deep-sleep locked). This performs wait only if needed and will not affect
other targets which do not need extra wait.
4. Move sleep_manager_lock_deep_sleep() after TEST_ASSERT_TRUE(sleep_manager_can_deep_sleep_test_check())
5. Use TEST_ASSERT_TRUE(sleep_manager_can_deep_sleep_test_check()) in
test_lock_unlock_test_check to let lower layers manage deep sleep.
due to partial implementation. Having FUTURE_SEQUANA_M0 and
FUTURE_SEQUANA PSA targets is misleading.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
On platforms using coretx m33 accessing the secure memory will cause SecureFault instead of Hardfault.
SecureFault is implemented in the secure image and cannot be changed in runtime.
Add calls to `mbedtls_platform_setup()` and
`mbedtls_platform_terminate()` to the trng greentea test, to
initialize the hardware acceleration engines, in some platforms.
Test checks stack sizes:
- ISR stack: exactly 1KB (with exception for NORDIC - 2KB and RENESAS - Cortex A targets not supported for this test)
- Main thread stack: exactly 4KB (with some exceptions - 3KB)
- Thread stack: exactly 4KB
Frequency setting just after erase operation was causing some data
inconsistencies during write/read operations on some targets (frdm-k82f).
To fix this, frequency setting was moved before flash memory init.
The DEVICE_FOO macros are always defined (either 0 or 1).
This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
For enhanced security ARMv8-M firmware doesn't allow the hardfault
handler to be hooked by non-secure code. Because of this there is no
way to recover from the MPU fault tests. This PR disables those tests
until hardfault recovery is supported by secure firmware.
Ensure that code written to ram is flushed and that caches are cleared
before attempting to executing from ram. This fixes CI failures on the
MPU test when it is built for Cotex-M7 devices such as the
NUCLEO-F746ZG.
Make the following changes:
-Allow a vector specific ARM MPU driver by defining MBED_MPU_CUSTOM
-Allow ROM address to be configured for ARMv7-M devices by
setting the define MBED_MPU_ROM_END
-Add ROM write protection
-Add new functions and lock
-enable at boot
-disable during flash programming
Create a dedicated MPU directory for standard Arm MPU implementations
in preparation for the Arm v8m MPU. Replace MBED_MPU_ENABLED with
DEVICE_MPU to align with the porting layer of other HAL APIs.
When programming flash using the FlashIAP API allow execution from
ram. Many devices require flashing to be done from RAM.
Also allow execution from ram when running the low level flash tests.
Test that the MPU correctly stops execution of memory in the stack
region, heap region, data region and bss region. Also check that the
MPU can be enabled, disabled and freed.
Laurent Meunier
Martin Kojtal
Devaraj Ranganna
Guillermo Alonso
Kevin Bracey
Ryan Morse
Cruz Monrreal II
Oren Cohen
Ron Eldor
Russ Butler
Przemyslaw Stekiel
jeromecoutant
Maciej Bocianski
Alexander Zilberkant
Alastair D'Silva
Mahesh Mahadevan