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Fix asyle problems 

Run astyle to fix CI failures.
pull/8871/head
Russ Butler 2018-11-16 18:23:30 -06:00 committed by Martin Kojtal
parent 02b50b44ef
commit 7cdfbee28b
3 changed files with 26 additions and 26 deletions
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14
TESTS/mbed_hal/mpu/main.cpp
View File

@ -46,11 +46,11 @@ static volatile uint16_t bss_function;
static void clear_caches()
{
#if defined(__CORTEX_M7)
/* Data cache clean and invalid */
SCB_CleanInvalidateDCache();
/* Data cache clean and invalid */
SCB_CleanInvalidateDCache();
/* Instruction cache invalid */
SCB_InvalidateICache();
/* Instruction cache invalid */
SCB_InvalidateICache();
#endif
__ISB();
@ -61,7 +61,7 @@ static void clear_caches()
static void call_mem(const volatile uint16_t *mem_function)
{
// or the address with 1 to ensure the thumb bit is set
((void (*)()) ((uint32_t)mem_function | 1))();
((void (*)())((uint32_t)mem_function | 1))();
}
static void hard_fault_handler_test()
@ -144,7 +144,7 @@ void mpu_fault_test_stack()
void mpu_fault_test_heap()
{
uint16_t *heap_function = (uint16_t*)malloc(2);
uint16_t *heap_function = (uint16_t *)malloc(2);
TEST_ASSERT_NOT_EQUAL(NULL, heap_function);
*heap_function = ASM_BX_LR;
@ -166,7 +166,7 @@ utest::v1::status_t fault_override_setup(const Case *const source, const size_t
}
utest::v1::status_t fault_override_teardown(const Case *const source, const size_t passed, const size_t failed,
const failure_t reason)
const failure_t reason)
{
// Restore real fault handlers
NVIC_SetVector(HARDFAULT_IRQn, real_hard_fault_handler);

6
hal/mpu/mbed_mpu_v7m.c
View File

@ -88,7 +88,7 @@ void mbed_mpu_init()
0, // IsShareable
1, // IsCacheable
0, // IsBufferable
// SubRegionDisable - based on where ROM ends
// SubRegionDisable - based on where ROM ends
((MBED_MPU_ROM_END >= 0x00000000) ? 0 : (1 << 0)) | // 0 to enable, 1 << n to disable
((MBED_MPU_ROM_END >= 0x04000000) ? 0 : (1 << 1)) |
((MBED_MPU_ROM_END >= 0x08000000) ? 0 : (1 << 2)) |
@ -114,7 +114,7 @@ void mbed_mpu_init()
0, // IsShareable
1, // IsCacheable
0, // IsBufferable
// SubRegionDisable - based on where RAM starts
// SubRegionDisable - based on where RAM starts
((MBED_MPU_RAM_START <= 0x04000000) ? 0 : (1 << 0)) | // 0 to enable, 1 << n to disable
((MBED_MPU_RAM_START <= 0x08000000) ? 0 : (1 << 1)) |
((MBED_MPU_RAM_START <= 0x0C000000) ? 0 : (1 << 2)) |
@ -141,7 +141,7 @@ void mbed_mpu_init()
0, // IsShareable
1, // IsCacheable
1, // IsBufferable
// SubRegionDisable
// SubRegionDisable
(1 << 0) | // Disable Sub-region
(0 << 1) | // Enable Sub-region SRAM 0x20000000 - 0x3FFFFFFF
(1 << 2) | // Disable Sub-region

32
hal/mpu/mbed_mpu_v8m.c
View File

@ -74,11 +74,11 @@ void mbed_mpu_init()
inner = 0xA; // Write-Through, Non-transient, Read-allocate
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
MPU->RBAR = (0x00000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x00000000
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(3 << MPU_RBAR_AP_Pos) | // RO allowed by all privilege levels
(0 << MPU_RBAR_XN_Pos); // Execute Never disabled
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(3 << MPU_RBAR_AP_Pos) | // RO allowed by all privilege levels
(0 << MPU_RBAR_XN_Pos); // Execute Never disabled
MPU->RLAR = (0x1FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x1FFFFFFF
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
region = 1;
MPU->RNR = region;
@ -86,11 +86,11 @@ void mbed_mpu_init()
outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
MPU->RBAR = (0x20000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x20000000
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
MPU->RLAR = (0x3FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x3FFFFFFF
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
region = 2;
MPU->RNR = region;
@ -98,11 +98,11 @@ void mbed_mpu_init()
outer = 0xF; // Write-Back, Non-transient, Read-allocate, Write-allocate
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
MPU->RBAR = (0x60000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x60000000
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
MPU->RLAR = (0x7FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x7FFFFFFF
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
region = 3;
MPU->RNR = region;
@ -110,11 +110,11 @@ void mbed_mpu_init()
inner = 0xA; // Write-Through, Non-transient, Read-allocate
ARM_MPU_SetMemAttrEx(MPU, region, (outer << 4) | (inner << 0));
MPU->RBAR = (0x80000000 & MPU_RBAR_BASE_Msk) | // Start address is 0x80000000
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
(0 << MPU_RBAR_SH_Pos) | // Not shareable
(1 << MPU_RBAR_AP_Pos) | // RW allowed by all privilege levels
(1 << MPU_RBAR_XN_Pos); // Execute Never enabled
MPU->RLAR = (0x9FFFFFFF & MPU_RLAR_LIMIT_Msk) | // Last address is 0x9FFFFFFF
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
(region << MPU_RLAR_AttrIndx_Pos); // Attribute index - configured to be the same as the region number
// Enable the MPU
MPU->CTRL =