ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,321 Commits
52 Branches
336 Tags
624 MiB
Commit Graph

9321 Commits (1d19f37d2562cf2701acad9aa6e981a3bf4c7721)

Author SHA1 Message Date
Jimmy Brisson 1d19f37d25 Remove special case template for F746ZG 2016-12-19 14:39:34 +00:00
Jimmy Brisson 409be21997 Update IAR template and STM M7 part options 2016-12-19 14:39:31 +00:00
Jimmy Brisson 4476d03f96 Fix typo in IAR definitions 2016-12-19 14:39:29 +00:00
jeromecoutant 4a7316e786 STM32L0 : correct ST HAL API call 
- RCC init: unused clock was enabled without any init parameters
- ADC: a parameter setting was missing
- GPIO: mode was not allowed by ST HAL API
- tick: init value was too high for 16b
 2016-12-19 14:39:27 +00:00
jeromecoutant 0eb0121ba3 STM32L0 : refactor stm32l0xx_hal_conf.h and map ST HAL assert into MBED assert 2016-12-19 14:39:26 +00:00
jeromecoutant 9fb2a1820d STM32F7 : correct ST HAL API call 
- RCC init: unused clock was enabled without any init parameters
- RCC init: one PLL parameter was missing
- GPIO: mode was not allowed by ST HAL API
 2016-12-19 14:39:24 +00:00
jeromecoutant ebda4649d8 STM32F7 : refactor stm32f7xx_hal_conf.h and map ST HAL assert into MBED assert 2016-12-19 14:39:23 +00:00
andreas.larsson d40c1837c9 Added tmpisr = regs->ISR; at the end of the while loop to re-evaluate the ISR value 2016-12-19 14:39:21 +00:00
Jimmy Brisson 333aad6191 Remove deprecated flags args 
The tools will no longer accept `--cflags`, `--cppflags`, or
`--ldflags`. Instead, the ability to modify these flags is
provided by the `--profile` argument. Documentation for the
`--profile` argument may be found in
docs/Toolchain_Profiles.md
 2016-12-19 14:39:19 +00:00
jeromecoutant dc3252b61a STM32F0 : correct ST HAL API call 
- CAN: compilation issue with assert enabled
- ADC: init parameter was not allowed by ST HAL API
- GPIO: mode was not allowed by ST HAL API
 2016-12-19 14:39:18 +00:00
jeromecoutant 35ccdab0cc STM32F0 : map ST HAL assert into MBED assert 2016-12-19 14:39:16 +00:00
bcostm 144f9b3f4d Remove NUCLEO_F412ZG from example linking_list 2016-12-19 14:39:14 +00:00
bcostm 5820dba45c Remove usb in build_travis.py for this target (not supported for now) 2016-12-19 14:39:13 +00:00
bcostm 01c120894b Correct A3, A4, A5 pins definitions 2016-12-19 14:39:11 +00:00
bcostm d2bbadfec8 Add platform in other python and json files 2016-12-19 14:39:10 +00:00
bcostm 3541878896 Correct SDIO_UART pins configuration 2016-12-19 14:39:08 +00:00
bcostm 3b838d28ec Add this platform in mbed_rtx.h file 2016-12-19 14:39:07 +00:00
bcostm 035c8d3770 Correct system clock configuration 2016-12-19 14:39:05 +00:00
bcostm 51000a3a1e Update hal_tick files 2016-12-19 14:39:03 +00:00
bcostm 702320acd7 Add startup and linker files for ARM_STD, ARM_MICRO, IAR 2016-12-19 14:39:02 +00:00
bcostm e22bbbaee6 Add GCC_ARM files and fix errors during GCC build 2016-12-19 14:39:00 +00:00
bcostm c279154a6b Add cmsis, hal_tick, system files 2016-12-19 14:38:58 +00:00
bcostm b64f0870a4 Add first pin, port and objects files 2016-12-19 14:38:57 +00:00
tomoyuki yamanaka c01027b2b4 Fix frequency function of CAN driver. 
Until now, when the frequency function of CAN driver was executed, signal no output, and the frequency could not be changed.
Since there was an error in the frequency changing procedure I modified it.
 2016-12-19 14:38:55 +00:00
Simon D Hughes 38b4e1158c Corrections of debug trace statements which prevent compilation when CFSTORE_DEBUG is defined. 2016-12-19 14:38:54 +00:00
Brian Daniels ddf1de5152 Renames i2c_api.c for STM32F1 targets to fix IAR exporter. 
The IAR build system does not allow two files to have the same name.
This renames the i2c_api.c file for the STM32F1 family to
i2c_api_stm32f1.c to avoid this issue. The common i2c_api.c file shared
among all ST targets is not actually used for STM32F1 targets as it
protected with an #ifdef guard.
 2016-12-19 14:38:52 +00:00
jeromecoutant 00d58f0fa3 STM32L1 : correct ST HAL API call 
- RCC init: unused clock was enabled without any init parameters
- RCC init: one PLL parameter was missing
- ADC: a parameter setting was missing to init clock
- GPIO: mode was not allowed by ST HAL API
- ll_utils: compilation issue
 2016-12-19 14:38:50 +00:00
jeromecoutant 888c52429c STM32L1 : refactor stm32l1xx_hal_conf.h and map ST HAL assert into MBED assert 2016-12-19 14:38:49 +00:00
bcostm deecd6e5ac Add SERIAL_FC in targets.json/device_has field for NUCLEO_F103RB 2016-12-19 14:38:47 +00:00
bcostm 09cf02e0ba Add external declaration of PinMap_UART_RTS/CTS[] const tables 2016-12-19 14:38:46 +00:00
Kevin Gillespie 95ccd4d6df Fixing serial readable function. 2016-12-19 14:38:44 +00:00
Mahadevan Mahesh bbdcae3c0a K66F: Enable LWIP feature 
Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
 2016-12-19 14:38:42 +00:00
Laurent MEUNIER 43854b7365 STM32 NUCLEO-L152RE Update system core clock to 32MHz 
Even when HSE is used, it is possible to get a 32MHz system clock
8MHz x PLLMUL=12 % PLLDIV=2 = 32MHz

And we still get 48MHz USB clock:
8MHz x PLLMUL=12 % 2 = 48MHz

This allows to take full benefit of the CPU capability.
 2016-12-19 14:38:41 +00:00
adustm f114ccf94f Add CAN2 missing pins for connector CN12 2016-12-19 14:38:39 +00:00
Russ Butler 0be2f95e83 Increase stack size in malloc test for Cortex-A 
Increase the stack size used in the malloc test to prevent stack
overflows on Cortex-A devices.
 2016-12-19 14:38:38 +00:00
Sarah Marsh c5c1879ddb Catch specific exception for TargetNotSupported 2016-12-19 14:38:36 +00:00
Sarah Marsh 1c6d6059a8 IAR export will not fail in the absence of a CMSIS pack 2016-12-19 14:38:35 +00:00
Michel Jaouen d6cbf84623 USB_4 : test OK with IAR ,GCC_ARM(limitation to ARM not needed) 2016-12-19 14:38:33 +00:00
Jimmy Brisson da3ac529d5 Enabled example exporting Filter ides by toolchains 2016-12-19 14:38:31 +00:00
Laurent MEUNIER 2ac3196496 STM32 I2C - 1MHZ frequency is allowed 
So make the assert to cover all possible values
Also assert applies only for I2C_IP_VERSION_V2.
Also in case of I2C_IP_VERSION_V1, the HAL makes the proper
checks and can dynamically scale the frequency in case of
intermediate value.
 2016-12-19 14:38:30 +00:00
Laurent MEUNIER ca12282118 enable I2C ASYNCH 
the I2C_ASYNCH feature is  added to all STM32 except
F1 family for now. Will be added when HAL update is done.
 2016-12-19 14:38:28 +00:00
Laurent MEUNIER 77576190c6 HAL I2C (V2) sequential transmit / receive 
In case of sequential transmit / receive, there is a need to:
- not use the reload option
- generate a new START on each new transaction

This applies to all HAL supporting the IP version V2.
 2016-12-19 14:38:27 +00:00
Laurent MEUNIER a8454a2766 HAL F2: I2C fix btf / rxne cases 
Applying the same fix as in L1 and F4
 2016-12-19 14:38:25 +00:00
Laurent MEUNIER b28687ffca Add more supported boards to I2C master slave asynch test 2016-12-19 14:38:24 +00:00
Laurent MEUNIER 645d44e2eb HAL L1: I2C fix btf / rxne cases 
This is an alignement to F4 HAL as the same IP is used.
Next official HAL delivery update hall will include the same alignement.
 2016-12-19 14:38:22 +00:00
Laurent MEUNIER 934a8cfb05 HAL L0: I2C / DMA updates 
This is prelim update before official V1.8.0 HAL to the needed HAL API
available as in F0 HAL which is using the same IP.
 2016-12-19 14:38:20 +00:00
Laurent MEUNIER 300c0b266e Make most of the I2C code into a common file 
Since most of the code in i2c_api.c is now relying on STM32 HAL, there
is now a possibility to make a common usage of this code accross families.

The IP version definition is introduced per family, to allow a switch of
functionnalities, especially the frequency management which differs.
BTw, we fix the F0 frequency settings at the same time.

F1 is managed for now as an exception as the HAL API for sequential transmit
/receive is not yet available (coming soon)
 2016-12-19 14:38:19 +00:00
Mahadevan Mahesh c54fd786e6 K64F DSPI Driver: Fix errors where DSPI state is incorrectly kept busy 
Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
 2016-12-19 14:38:17 +00:00
Mahadevan Mahesh 7ad3026e76 K64F SPI Update: Implement Asynch API's for SPI 
Signed-off-by: Mahadevan Mahesh <Mahesh.Mahadevan@nxp.com>
 2016-12-19 14:38:16 +00:00
jeromecoutant 58be2d4b67 NUCLEO_F429ZI has integrated LSE 2016-12-19 14:38:14 +00:00