Make the following changes:
-Allow a vector specific ARM MPU driver by defining MBED_MPU_CUSTOM
-Allow ROM address to be configured for ARMv7-M devices by
setting the define MBED_MPU_ROM_END
-Add ROM write protection
-Add new functions and lock
-enable at boot
-disable during flash programming
When programming flash using the FlashIAP API allow execution from
ram. Many devices require flashing to be done from RAM.
Also allow execution from ram when running the low level flash tests.
The flash clock test is disabled for the NRF52 series. This change
re-enables the test but with a higher tolerance to accommodate the
high jitter on the current ticker implementation.
The current 0.1% clock tolerance is too small for certain platforms
which natural variance is larger than this. This commit increases the
tolerance to 0.5% instead.
Sample output from time_cpu_cycles called repeatedly in init,
before running any flash tests:
[1515706585.63][CONN][RXD] diff: 49316
[1515706585.69][CONN][RXD] diff: 49256
[1515706585.75][CONN][RXD] diff: 49286
[1515706585.81][CONN][RXD] diff: 49256
[1515706585.87][CONN][RXD] diff: 49225
[1515706585.94][CONN][RXD] diff: 49286
[1515706585.99][CONN][RXD] diff: 49317
[1515706586.06][CONN][RXD] diff: 49255
[1515706586.12][CONN][RXD] diff: 49286
[1515706586.18][CONN][RXD] diff: 49285
[1515706586.24][CONN][RXD] diff: 49286
[1515706586.31][CONN][RXD] diff: 49347
[1515706586.36][CONN][RXD] diff: 49347
[1515706586.43][CONN][RXD] diff: 49286
[1515706586.49][CONN][RXD] diff: 49286
[1515706586.55][CONN][RXD] diff: 49256
[1515706586.61][CONN][RXD] diff: 49286
[1515706586.68][CONN][RXD] diff: 49346
[1515706586.74][CONN][RXD] diff: 49347
[1515706586.80][CONN][RXD] diff: 49256
Notice the outliers will cause intermittent CI failures.
The test assumed that data written to flash would be memory mapped
and directly accessible. On some platform this is not the case
and data has to read back through an explicit read command.
The test has been changed to use the flash read command instead
of direct memory access.