We need to remove *can_api.c* file accordingly to new directory structure.
Without that we can't compile any CAN mBed test.
Change-Id: I3d4f798ad75ec1b4c4a1d7ed877e71b7db6bf60f
This was causing errors at my machine (for programs like MBED_10, RTOS_1):
Error[Li005]: no definition for "__semihost" [referenced from
semihost_api.o(mbed.a)]
[ERROR] Error[Li005]: no definition for "__semihost" [referenced from
semihost_api.o(mbed.a)]
Added CAN API support for NUCLEO_F042K6 target.
"stm32f042x6.h" file was changed to avoid compilation errors.
Change-Id: I9622a233775fc6834201a322740bf5026244d50e
Added CAN API support for NUCLEO_F072RB target.
*stm32f072xb.h* file was changed to avoid compilation errors.
Change-Id: I9da75fde29fd19f0326d554acc1dbb5386b08317
Added CAN API suport for NUCLEO_F091RC target.
*stm32f091xc.h* file was changed to avoid compilation errors.
Change-Id: I9207575a0e2ad0f8e3a4bb78eb23d1e7b4a94171
we changed the sequence of ROM section to "<ro code> <ro data>" when compiled with the IAR.
When the ROM area is large, PC could not jump properly in the program area.
The other development environment of this sequence ("ro code, ro data").
https://github.com/mbedmicro/mbed/pull/1702
In this PR, rtx has updated, the macro into the code were changed.
However, by this macro, the process of task generation in Cortex-A9 can no longer be run.
So, we solve the task generation problem by changing the macro into Tread.cpp again.
NUCLEO_L053R8 is using a 16 bit timer as a internal ticker but the mBed ticker
needs a 32 bit timer, so the upper upart of that timer is being calculated in
software. Continous HIGH/LOW voltage levels were observerd for 65ms due to timer
overflow, so to narrow down the issue, it was decided to switch to 16 bit values
and glue them to get a 32 bit timer.
Change-Id: I54a06d5aa0f8ddabd8abc194470845a2509e0c55
* [STM32F4] Get PCLK1 clock and set initial CAN frequency
CAN bus opperates on APB1 peripheral clock due to that we need to get PCLK1 freq
in *can_frequency()* function to properly calculate CAN speed and reconfigure
BS1, BS2, SJW bits.
Also to fully communicate with other ST platform we set the initical CAN
frequency to 100kb/s to be able to work with the slowest platform which supports
CAN, which is NUCLEO_F303K8 (APB1 is 32MHz).
Change-Id: I10af3aa8d715dd61c9d1b216ef813193449fecbd
* [STM32F4] Fix for CAN2 interrupt index
CAN2 interrupt index was wrong leading to not properly registering interrupt.
Having this fix allow us to pass MBED_30 test.
Change-Id: I33f9ca7c81286f7746a8f8352619e213bdf9756a
With PR #1707 all STM32F4 targets with UART4 and UART5 are broken, a several typos in function definition.
Seems to be a bug in STM32Fcube HAL, not only in the (older) mbed versin but also in current version
* [STM32F1 F4] Fix#1705 MBED_37
The transmit data register needs to be flushed at the initialisation of
the uart.
In case previous transmission was interrupted by a uart init, uart may
contain a char that will be transmitted at the next start.
This is the case in MBED_37 test (serial_auto_nc_rx).
The MCU is writting {{start}}\n
At the moment of the \n the main program is handling 'new serial'. The
next time the main program is handling a printf, the previous \n is
still present in the uart->DR register and is transmitted.
This cannot happen anymore with this commit
* [STM32_F1] Fix#1705 MBED_37 by resetting the uart
Martin Kojtal
Bartosz Szczepanski
Russ Butler
Mihail Stoyanov
Mihail Stoyanov
Toyomasa Watarai
Mahadevan Mahesh
bcostm
TomoYamanaka
ohagendorf
adustm
bcostm
Olaf Hagendorf
adustm