Consider the following factors to define WDT reset delay:
1. Cannot be too small. This is to avoid premature WDT reset in pieces of timeout cascading.
2. Cannot be too large. This is to pass Greentea reset_reason/watchdog_reset tests, which have e.g. 50~100 reset delay tolerance.
Original implementation doesn't enable watchdog reset in pieces of cascaded timeout, except the last one. This is to guarantee re-configuration can be in time, but in interrupt disabled scenario e.g. Hard Fault, watchdog reset can cease to be effective.
This change enables watchdog reset all the way of cascaded timeout. With trade-off, guaranteed watchdog reset function is more significant than re-configuration in time.
In no MISO case, skip SPI read so that no more write/read delay contribute to SPI inter-frame delay when data is written successively.
Update targets:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NU_PFM_M2351_*
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST.)
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
On IAR, configure heap to 1KiB at a minimum and expandable, dependent on available SRAM. This requires IAR 8.x.
Support targets:
- NUMAKER_PFM_NUC472 w/ and w/o XRAM
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
M451 series can classify by M45xD/M45xC and M45xG/M45xE. To support this
classification:
1. Create TARGET_M45xD_M45xC and TARGET_M45xG_M45xE targets.
2. Mark NUMAKER_PFM_M453 belongs to TARGET_M45xG_M45xE by 'extra_labels_add'
in targets.json.
3. Fix pin name table according to the classification.
4. Fix pinmap table according to the classification.
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
Fix logic error on replying NACK at the end of transfer.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
With support for checking H/W UART initialized or not, we can simplify stdio management:
1. When serial_init(&stdio_uart) calls in, just set the 'stdio_uart_inited' flag.
2. When serial_free(&stdio_uart) calls in, just clear the 'stdio_uart_inited' flag.
Except above, we needn't make special handling with 'stdio_uart'.
Martin Kojtal
Chun-Chieh Li
Filip Jagodzinski
Przemyslaw Stekiel
Maciej Bocianski
int_szyk
Rajkumar Kanagaraj
deepikabhavnani
Russ Butler
Cruz Monrreal