STORE_SECTORS is a hard requirement. If there are fewer than 2 pages
then the kvstore will not work, because the garbage collection process
relies on having at least two sectors to work with.
STORE_PAGES is a heuristic. It is a reasonable default to use if the
application does not specify the amount of flash to use for TDBStore.
But if an application knows that a smaller number of pages will suffice
for its specific needs, then that is valid and should be permitted.
The minimum size required by tdbstore is either 2 sectors or 10 pages,
whichever is larger. Correspondingly, adjust the error checks in
_calculate_blocksize_match_tdbstore to match this requirement.
Default the size to the larger of two sectors or 10 pages, so that the
computation works better on devices with a low sector to page size ratio.
Reduce code duplication.
Musca-B1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_B1 is the non-secure target running mbed-os.
- ARM_MUSCA_B1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_B1 is submitted by a
pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
Change-Id: I4b36290941b5f0bb7aa7c12dda2f38b5c1e39ae2
Signed-off-by: Tamas Kaman <tamas.kaman@arm.com>
Signed-off-by: Gabor Abonyi <gabor.abonyi@arm.com>
Previously it was 2 pages - 1kB - which isn't sufficient to store
Reserved Area and Master Record. Reserved are requires one page and Master
Record takes two pages. With 512B page size and having two areas, active and
inactive, the minimum size requirement becomes 2 areas * 3 pages = 3kB. That
isn't enough to store any keys though.
* Refactor some headers to use relative path from Mbed OS root.
* Refactor some data types to compile on 64bit machines.
* Refactor some debug traces to use mbed_trace.
- Enable FLASHIAP for all H7 boards
- Use "TDB_INTERNAL" for all H7 boards
- Define specific internal_base_address only for DISCO_H747I_CM7
(default address is the end of FLASH which is correct for other H7 boards)
- Correct GetSectorBase function with Dual Bank information
The default computation assumes that a flash sector is several times
larger than a flash page. On PSoC 6 targets this is not the case
(the two values are the same) so the computed size is too small.
This is a similar change to 1b1f14d36b,
but for devices which implement TDB in internal storage.
The default computation assumes that a flash sector is several times
larger than a flash page. On PSoC 6 targets this is not the case
(the two values are the same) so the computed size is too small.
To compile Mbed Bootloader with bare metal profile certain defines are
not added anymore automatically. Because of this checks for those
defines needed to be introduced.
Thus far the default position has been after the application plus two
spare sectors. For simplicity and to have a predictable location for the
TDBStore with the default configuration the location is now switched to
the end of the flash. Two last sectors to be exact.
Musca-A1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_A1 is the non-secure target running mbed-os.
- ARM_MUSCA_A1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_A1 is submitted by a pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
due to partial implementation. Having FUTURE_SEQUANA_M0 and
FUTURE_SEQUANA PSA targets is misleading.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
To support block device out of mbed-os tree in KVStore, user needs to:
1. Configure blockdevice to "other".
2. Override get_other_blockdevice() to provide block device out of mbed-os tree.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
Chun-Chieh Li
MarceloSalazar
Kyle Kearney
Marcin Tomczyk
Tamas Kaman
Pawel Zarembski
Przemyslaw Stekiel
Veijo Pesonen
Seppo Takalo
jeromecoutant
Janne Kiiskila
midd
Martin Kojtal
Vairamuthu Ramasamy
Matthew Macovsky
Volodymyr Medvid
Qinghao Shi
Oren Cohen
Michael Schwarcz
Devaraj Ranganna
Anna Bridge
Evgeni Bolotin
Mahesh Mahadevan
Oleg Kapshii
Yossi Levy
Alexander Zilberkant