Commit Graph

20 Commits (mbed-os-5.7)

Author SHA1 Message Date
adustm c1d883db19 Change STM32L475/76/86 GCC_ARM linker files to have HEAP in SRAM1 and stack in SRAM2 (after the interrupt vector) 2018-03-14 14:48:09 -05:00
bcostm a5cd64eebb STM32L476/486: change SRAM config for IAR 2018-02-09 14:18:45 +00:00
jeromecoutant ee333a5cd0 SMT32L4 : add missing ST HAL LPUART functions
To enable/disable UART Clock in Stop Mode
2018-02-09 14:18:41 +00:00
bcostm 5bb6edc952 Update stm32l4xxxx.h files 2018-01-27 01:37:26 -06:00
bcostm 4c7f0e6e5b Update stm32l4xx.h files 2018-01-27 01:37:25 -06:00
bcostm 5fa45e827a L4 ST CUBE V1.11.0
Update to STM32CubeL4 V1.11.0

Conflicts solved:
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h
2018-01-27 01:35:20 -06:00
bcostm 9f86a32baf Add freeze timer on debug for all STM32 devices
This is a continuation of the work done on the STM32F401xE devices only.
2017-09-18 13:31:46 +02:00
Jimmy Brisson 15a9a0382b Enable Compiling with ARMC6 across all targets
remove duplicate sys.cpp
2017-09-11 13:20:32 -05:00
jeromecoutant b654af2d80 STM32L4 : json clock source configuration
- default value is the same as before patch
- system_stm32l4xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- nvic_addr.h file is now in TARGET_STM level
2017-07-19 16:39:26 +02:00
Laurent MEUNIER 73eebaad19 NUCLEO_L476RG: FLASH size of 1MB, not 2MB
MBED_APP_SIZE was erroneously defined to 2MB for this target,
while it's only 1MB.
2017-06-14 16:52:08 +02:00
Laurent MEUNIER 1d802028cf NUCLEO_L476RG: GCC_ARM ld file fix
Following
Merge pull request #4063 from LMESTM/17q2_L4_bootloader
the NUCLEO_L476RG binairies could not boot anymore.

The change done in #4063 was derived from work on NUCLEO_L429ZI target
which supports uvisor. The VECTORS defintiion is introduced as part of
uvisor support and requires further changes in ld file which were missing.
As uvisor is not considered yet, we remove VECTORS for now and will
introduce only when needed.
2017-06-14 16:48:29 +02:00
Sam Grove 1607c83d77 Merge pull request #4469 from kegilbert/17q2-l4-bootloader-rebase
17q2 l4 bootloader - Rebase
2017-06-08 11:38:25 -05:00
Sam Grove 72de85c62f Merge pull request #4417 from monkiineko/master
STM32: Fix 32-bit us ticker interrupt scheduling
2017-06-06 19:59:52 -05:00
Laurent MEUNIER 7ec9fe23c1 Update stm32l476rg linker scripts for bootloader
Add MBED_APP_START and MBED_APP_SIZE to the linker scripts
so the start and size of an image can be specified. This allows the
ROM to be split into a bootloader region and an application region.
2017-06-06 15:43:54 -05:00
Laurent MEUNIER 5fbe3299d7 Rebase of: e51c40c061
Fix vector table

The address of the vector table is hardcoded to the start of flash.
This patch updates make it properly handle updating the VTOR with
a bootloader.
2017-06-06 15:43:17 -05:00
Bradley Scott 260378e774 STM32: Fix 32-bit us ticker interrupt scheduling
For STM32 targets using a 32-bit timer for the microsecond ticker, the
driver did not properly handle timestamps that are in the past.  It
would just blindly set the compare register to the requested timestamp,
resulting in the interrupt being serviced up to 4295 seconds late
(i.e. after the 32-bit timer counts all the way around to hit the
timestamp again).

This problem can easily be reproduced by creating a Timeout object
then calling the timeout's attach_us() member function to attach a
callback with a timeout of 0 us.  The callback will not get called for
over 2147 seconds, and possibly up to 4295 seconds late if no other
microsecond ticker events are getting scheduled in the meantime.

Now, after the compare register has been set, the timestamp is checked
against the current time to see if the timestamp is in the past, and
if so, the compare event is manually set.

NOTE: By checking if the timestamp is in the past after configuring the
capture register, we ensure proper handling in the case where the timer
updates past the timestamp while setting the capture register.
2017-06-01 12:52:03 -04:00
Bartek Szatkowski b97ffe8fdc CMSIS5: Replace target defined NVIC_Set/GetVector with CMSIS implementation 2017-05-30 18:55:51 +01:00
jeromecoutant 5dc49b7d6c STM32L4 replace deprecated macro name 2017-05-19 11:59:38 +02:00
jeromecoutant 0178969e90 STM32Cube_FW_L4_V1.8.0
CMSIS v1.1.1 => v1.3.1
    STM32L4 HAL v1.5.1 => v1.7.1
2017-05-18 14:36:32 +02:00
adustm 389d9ba358 STM32L476xG STM32L486xG folder structure modification 2017-01-27 17:35:27 +01:00