Commit Graph

2085 Commits (mbed-os-5.14)

Author SHA1 Message Date
Martin Kojtal 918a0f5509 Revert "DISCO STM32H747I ETHERNET support, but disabled."
This reverts commit 7fcedd20e1.
2019-11-20 09:41:03 +00:00
adbridge 5700890615 Revert "F7 ST CUBE V1.10.0 => V1.15.0"
This reverts commit 8ac918975f.
2019-11-19 14:39:33 +00:00
adbridge 0960359312 Revert "STM32F7 updates for new driver version"
This reverts commit 52bfd0c99a.
2019-11-19 14:39:18 +00:00
adbridge f94ab8a760 Revert "STM32F7 refactor common files"
This reverts commit 4f788adeb9.
2019-11-19 14:39:02 +00:00
adbridge 345b6f0151 Revert "STM32F7 ARM SCT file update to define correct RAM_SIZE"
This reverts commit 356de44aed.
2019-11-19 14:37:56 +00:00
adbridge 424ade30a8 Revert "STM32F7 HAL CRYPT patch to add missing UNLOCK"
This reverts commit 7847ad79fb.
2019-11-19 14:37:20 +00:00
Adam Mitchell e15560fa83 Correct PB_6/PB_7 Serial AF mapping 2019-11-18 15:48:17 +00:00
jeromecoutant b44d708589 DISCO STM32H747I ETHERNET support, but disabled.
Ethernet is disabled by default,
because some hardware modifications are required on the board DISCO_H747I.
see https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet
2019-11-18 15:48:17 +00:00
jeromecoutant 7eb6ed6602 STM32F7 HAL CRYPT patch to add missing UNLOCK 2019-11-18 15:48:17 +00:00
jeromecoutant dafc9d9b92 STM32F7 ARM SCT file update to define correct RAM_SIZE 2019-11-18 15:48:17 +00:00
jeromecoutant db146ff14b STM32F7 refactor common files 2019-11-18 15:48:17 +00:00
jeromecoutant e400e18cfc STM32F7 updates for new driver version 2019-11-18 15:48:17 +00:00
jeromecoutant ab10fef7a4 F7 ST CUBE V1.10.0 => V1.15.0
https://www.st.com/en/embedded-software/stm32cubef7.html
2019-11-18 15:48:17 +00:00
Laurent Meunier bf3dda363e STM32 QSPI: Use defines for setting address size 2019-11-18 15:42:08 +00:00
Janne Kiiskila 132e76913b Fix for the H747 flash driver / cache cleaning
This copies the approach of the STM32F7 flash driver submitted via
PR https://github.com/ARMmbed/mbed-os/pull/10248

With this change the board finally passes all of the device key
tests 10/10 times correctly.
2019-11-18 15:42:08 +00:00
Jammu Kekkonen 14ac203a3a Add option to use CCMRAM on F303xE. 2019-11-18 15:42:08 +00:00
Kevin Bracey f50e7b1da3 Clean up ARM toolchain heap+stack setup in targets
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.

Looking into this, a number of other issues were highlighted

* Almost all targets had `__initial_sp` hardcoded in assembler,
  rather than getting it from the scatter file. This was behind
  issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
  file layout, in some cases meaning they were overlapping heap
  space. They now all use the area reserved in the scatter file.
  If any problems are seen, then there is an error in the
  scatter file.
* A number of targets were reserving unneeded space for heap and
  stack in their startup assembler, on top of the space reserved in
  the scatter file, so wasting a few K. A couple were using that
  space for the stack, rather than the space in the scatter file.

To clarify expected behaviour:

* Each scatter file contains empty regions `ARM_LIB_HEAP` and
  `ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
  by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
  `ARM_LIB_HEAP` is generally the space left over after static
  RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
  vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
  for the ARM library. The ARM library calls this during startup, and
  it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
  modify SP, so we remain on the boot stack, and the heap is set to
  the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
  exist, then the heap is the space from the end of the used data in
  `RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
  Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
  Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
  itself.
2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 2da2322a08 STM32F767ZI - I2C FastModePlus not properly enabled 2/2
Warning: sometimes I2C_FASTMODEPLUS_I2Cx is defined,
even if not supported by some chip within the family
2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 096847bbb1 STM32F767ZI - I2C FastModePlus not properly enabled
Fixes #11659
2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 4d9c888057 TARGET_STM: remove warning and fix typo on SPI 2019-11-18 15:42:08 +00:00
jeromecoutant 4ab3fb2596 STM32 TRNG clock configuration 2019-11-18 15:42:08 +00:00
Kyle Kearney 6b1a21b7f0 Update STM driver changes for clarity
- Use a switch statement rather than shifting and masking to compute
  the AlternateBytes value.
- Rename rounded_size to alt_bytes to clarify its purpose.
2019-11-18 15:42:08 +00:00
toyowata 9ab22274a6 Add bootloader support for Seeed Arch-MAX 2019-11-18 15:42:08 +00:00
Laurent Meunier d92adcd28c Clearing UART TC Flag prevents deep sleep, so do not clear it
The TC flag is used in function serial_is_tx_ongoing to check if there is
an ongoing serial transmission. So this Flag must not be cleared at the
end of the transmission, otherwise, serial_is_tx_ongoing will notify that
TX is ongoing.

The impact is that it may prevent deep sleep to be entered.

Also there is no need to clear this flag at the end of the transaction
because it will be cleared automatically by HW when a new transmission
starts.
2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 1e351720a7 Mbed patch of STM32cube for bootloader: use NVIC_FLASH_VECTOR_ADDRESS 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol bdb0082bc9 Update HAL/LL EXTI to have default API applied on current core and nott CPU1 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 7846c9fe91 SystemCoreClock should correspond to current core clock and not D1 clock. 2019-11-18 15:42:08 +00:00
Alexandre Bourdiol 5418d70813 DISCO_H747I Dualcore support
Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.
2019-11-18 15:42:08 +00:00
Janne Kiiskila 67fbe49819 stm32f4xx_hal_pcd.c@346,22: unused variable 'ep'
Compiler warning fix, trivial. One function has an unused
variable, delete that line.
2019-11-18 15:42:08 +00:00
adbridge 070269295f Add OKDO platform
Manually ported from PR11407
2019-10-16 12:10:38 +01:00
jeromecoutant 19b641bb66 STM32L151: update calibration memory address 2019-10-16 11:58:32 +01:00
jeromecoutant 82f2b72777 DISCO_L4R9I: update default STMOD+ pin 2019-10-16 11:58:32 +01:00
Kyle Kearney 65e726eb9e Fix possible negative QSPI alt count on STM
Remove an extraneous decrement operation in cases where the alt
bits size is a multiple of 8.
2019-10-16 11:58:32 +01:00
Matthew Macovsky 08a2709993 Allow for arbitrary QSPI alt sizes
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
2019-10-16 11:58:32 +01:00
Ben Cooke 9145b72433 Add MTS_DRAGONFLY_F413RH platform to mbed-os 2019-10-16 11:58:32 +01:00
jeromecoutant b2e0a13730 STM32H7 ST CUBE V1.5.0 update 2019-10-16 11:53:52 +01:00
Vincent Veron 85757ce198 STM32H7 : use RAM instead of DTCMRAM (GCC_ARM toolchain) 2019-10-16 11:53:52 +01:00
Vincent Veron 7561e770a3 STM32H7 : use RAM instead of DTCMRAM (ARM toolchain) 2019-10-16 11:53:52 +01:00
Vincent Veron dd9f9e1cb5 STM32H7 : use RAM instead of DTCMRAM (IAR toolchain)
Keep vector table and crash data ram in 0x20000000 for
tests-mbed_platform-crash_reporting test.
Move the rest in RAM (0x24000000). This is needed for ethernet and allows
user to use more RAM (512k).

Signed-off-by: Vincent Veron <vincent.veron@st.com>
2019-10-16 11:53:52 +01:00
jeromecoutant b3a14b5ead STM32WB : LSI clock selection when LSE is not available 2019-10-16 11:53:52 +01:00
jeromecoutant 7272fe0613 STM32H7: LSI clock selection when LSE is not available 2019-10-16 11:53:52 +01:00
int_szyk 7411db1deb Change the LSI_VALUE according to documentation 2019-10-16 11:53:52 +01:00
jeromecoutant c9f7798df5 STM32WB ADC : Consecutive VBAT values reading was not possible
Add Stop after read
2019-10-16 11:53:52 +01:00
jeromecoutant 74a24ea88d STM32H747 license update 2019-10-16 11:53:52 +01:00
jeromecoutant 2008be1c0d DISCO_H747I single core M7 introduction 2019-10-16 11:53:52 +01:00
jeromecoutant 46b310304a STM32H747xI introduction 2019-10-16 11:53:52 +01:00
jeromecoutant 08fe757f14 STM32H743 files move 2019-10-16 11:53:52 +01:00
jeromecoutant 0f12e65b9c STM license file update
Some code have been copied from ST Cube deliveries.
ST copyright is then needed.
2019-10-16 11:53:52 +01:00
dolphin\\gena 6176f066f4 formatting 2019-10-16 11:53:52 +01:00
dolphin\\gena 8d734ee055 bad formatting correction 2019-10-16 11:53:52 +01:00