In most cases, we can control degraded QSPI H/W to standard through BSP SPI driver directly as if it is just SPI H/W.
However, BSP SPI driver distinguishes among SPI H/W instances in below functions:
- SPI_Open
- SPI_Close
- SPI_SetBusClock
- SPI_GetBusClock
In these cases, we must change to QSPI version instead for QSPI H/W.
Change target:
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NU_PFM_M2351*
Relevant modifications:
1. Support degrading QSPI0/1 to SPI4/5 for normal SPI transfer
2. Fix with BSP crypto driver API change
3. Fix with BSP PDMA driver API change
4. Make necessary modifications to pass FPGA CI Test Shield tests
5. Don't distinguish pinmap among parts e.g. M480 LG. Application users must take care.
In no MISO case, skip SPI read so that no more write/read delay contribute to SPI inter-frame delay when data is written successively.
Update targets:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NU_PFM_M2351_*
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
1. Disable unnecessary TX/RX threshold interrupts to avoid potential trap in DMA transfer
2. Start TX/RX DMA transfer simultaneously to fit H/W spec and avoid potential RX FIFO overflow issue
Chun-Chieh Li
Russ Butler