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[HAL LPC11U6x] Fix mask bits for SPI clock rate

pull/4869/head
toyowata 2017-08-08 15:42:56 +09:00
parent 9ad17b21a2
commit fdc071d5e8
1 changed files with 2 additions and 2 deletions
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4
targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c
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@ -110,7 +110,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0]
tmp |= DSS << 0
| FRF << 4
| SPO << 6
@ -146,7 +146,7 @@ void spi_frequency(spi_t *obj, int hz) {
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFFFF << 8);
obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8]
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;