From fdc071d5e81302ddbe1df77e358d403fe521ea99 Mon Sep 17 00:00:00 2001 From: toyowata Date: Tue, 8 Aug 2017 15:42:56 +0900 Subject: [PATCH] [HAL LPC11U6x] Fix mask bits for SPI clock rate --- targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c b/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c index 95c647c74c..6f78a61cd9 100644 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11U6X/spi_api.c @@ -110,7 +110,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) { int FRF = 0; // FRF (frame format) = SPI uint32_t tmp = obj->spi->CR0; - tmp &= ~(0xFFFF); + tmp &= ~(0x00FF); // Clear DSS, FRF, CPOL and CPHA [7:0] tmp |= DSS << 0 | FRF << 4 | SPO << 6 @@ -146,7 +146,7 @@ void spi_frequency(spi_t *obj, int hz) { obj->spi->CPSR = prescaler; // divider - obj->spi->CR0 &= ~(0xFFFF << 8); + obj->spi->CR0 &= ~(0xFF00); // Clear SCR: Serial clock rate [15:8] obj->spi->CR0 |= (divider - 1) << 8; ssp_enable(obj); return;