mirror of https://github.com/ARMmbed/mbed-os.git
TARGET_STM32F2 astyle
jeromecoutant
parent
c8313901fb
commit
f9bd4768a5
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@ -47,27 +47,27 @@ typedef enum {
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typedef enum {
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PA_0 = 0x00,
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PA_0_ALT0 = 0x00|ALT0,
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PA_0_ALT1 = 0x00|ALT1,
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PA_0_ALT0 = 0x00 | ALT0,
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PA_0_ALT1 = 0x00 | ALT1,
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PA_1 = 0x01,
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PA_1_ALT0 = PA_1|ALT0,
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PA_1_ALT1 = PA_1|ALT1,
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PA_1_ALT0 = PA_1 | ALT0,
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PA_1_ALT1 = PA_1 | ALT1,
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PA_2 = 0x02,
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PA_2_ALT0 = PA_2|ALT0,
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PA_2_ALT1 = PA_2|ALT1,
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PA_2_ALT0 = PA_2 | ALT0,
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PA_2_ALT1 = PA_2 | ALT1,
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PA_3 = 0x03,
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PA_3_ALT0 = 0x03|ALT0,
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PA_3_ALT1 = 0x03|ALT1,
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PA_3_ALT0 = 0x03 | ALT0,
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PA_3_ALT1 = 0x03 | ALT1,
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PA_4 = 0x04,
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PA_4_ALT0 = 0x04|ALT0,
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PA_4_ALT0 = 0x04 | ALT0,
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PA_5 = 0x05,
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PA_5_ALT0 = 0x05|ALT0,
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PA_5_ALT0 = 0x05 | ALT0,
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PA_6 = 0x06,
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PA_6_ALT0 = 0x06|ALT0,
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PA_6_ALT0 = 0x06 | ALT0,
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PA_7 = 0x07,
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PA_7_ALT0 = 0x07|ALT0,
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PA_7_ALT1 = 0x07|ALT1,
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PA_7_ALT2 = 0x07|ALT2,
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PA_7_ALT0 = 0x07 | ALT0,
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PA_7_ALT1 = 0x07 | ALT1,
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PA_7_ALT2 = 0x07 | ALT2,
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PA_8 = 0x08,
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PA_9 = 0x09,
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PA_10 = 0x0A,
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@ -76,63 +76,63 @@ typedef enum {
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PA_13 = 0x0D,
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PA_14 = 0x0E,
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PA_15 = 0x0F,
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PA_15_ALT0 = 0x0F|ALT0,
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PA_15_ALT0 = 0x0F | ALT0,
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PB_0 = 0x10,
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PB_0_ALT0 = 0x10|ALT0,
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PB_0_ALT1 = 0x10|ALT1,
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PB_0_ALT2 = 0x10|ALT2,
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PB_0_ALT0 = 0x10 | ALT0,
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PB_0_ALT1 = 0x10 | ALT1,
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PB_0_ALT2 = 0x10 | ALT2,
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PB_1 = 0x11,
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PB_1_ALT0 = 0x11|ALT0,
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PB_1_ALT1 = 0x11|ALT1,
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PB_1_ALT0 = 0x11 | ALT0,
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PB_1_ALT1 = 0x11 | ALT1,
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PB_2 = 0x12,
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PB_3 = 0x13,
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PB_3_ALT0 = 0x13|ALT0,
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PB_3_ALT0 = 0x13 | ALT0,
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PB_4 = 0x14,
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PB_4_ALT0 = 0x14|ALT0,
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PB_4_ALT0 = 0x14 | ALT0,
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PB_5 = 0x15,
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PB_5_ALT0 = 0x15|ALT0,
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PB_5_ALT0 = 0x15 | ALT0,
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PB_6 = 0x16,
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PB_7 = 0x17,
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PB_8 = 0x18,
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PB_8_ALT0 = 0x18|ALT0,
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PB_8_ALT0 = 0x18 | ALT0,
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PB_9 = 0x19,
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PB_9_ALT0 = 0x19|ALT0,
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PB_9_ALT0 = 0x19 | ALT0,
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PB_10 = 0x1A,
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PB_11 = 0x1B,
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PB_12 = 0x1C,
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PB_13 = 0x1D,
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PB_14 = 0x1E,
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PB_14_ALT0 = PB_14|ALT0,
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PB_14_ALT1 = PB_14|ALT1,
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PB_14_ALT0 = PB_14 | ALT0,
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PB_14_ALT1 = PB_14 | ALT1,
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PB_15 = 0x1F,
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PB_15_ALT0 = 0x1F|ALT0,
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PB_15_ALT1 = 0x1F|ALT1,
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PB_15_ALT0 = 0x1F | ALT0,
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PB_15_ALT1 = 0x1F | ALT1,
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PC_0 = 0x20,
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PC_0_ALT0 = 0x20|ALT0,
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PC_0_ALT1 = 0x20|ALT1,
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PC_0_ALT0 = 0x20 | ALT0,
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PC_0_ALT1 = 0x20 | ALT1,
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PC_1 = 0x21,
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PC_1_ALT0 = PC_1|ALT0,
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PC_1_ALT1 = PC_1|ALT1,
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PC_1_ALT0 = PC_1 | ALT0,
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PC_1_ALT1 = PC_1 | ALT1,
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PC_2 = 0x22,
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PC_2_ALT0 = 0x22|ALT0,
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PC_2_ALT1 = 0x22|ALT1,
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PC_2_ALT0 = 0x22 | ALT0,
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PC_2_ALT1 = 0x22 | ALT1,
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PC_3 = 0x23,
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PC_3_ALT0 = 0x23|ALT0,
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PC_3_ALT1 = 0x23|ALT1,
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PC_3_ALT0 = 0x23 | ALT0,
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PC_3_ALT1 = 0x23 | ALT1,
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PC_4 = 0x24,
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PC_4_ALT0 = PC_4|ALT0,
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PC_4_ALT0 = PC_4 | ALT0,
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PC_5 = 0x25,
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PC_5_ALT0 = PC_5|ALT0,
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PC_5_ALT0 = PC_5 | ALT0,
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PC_6 = 0x26,
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PC_6_ALT0 = 0x26|ALT0,
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PC_6_ALT0 = 0x26 | ALT0,
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PC_7 = 0x27,
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PC_7_ALT0 = 0x27|ALT0,
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PC_7_ALT0 = 0x27 | ALT0,
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PC_8 = 0x28,
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PC_8_ALT0 = 0x28|ALT0,
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PC_8_ALT0 = 0x28 | ALT0,
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PC_9 = 0x29,
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PC_9_ALT0 = 0x29|ALT0,
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PC_9_ALT0 = 0x29 | ALT0,
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PC_10 = 0x2A,
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PC_11 = 0x2B,
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PC_12 = 0x2C,
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@ -272,7 +272,7 @@ typedef enum {
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SPI_CS = D10,
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PWM_OUT = D9,
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/**** USB pins ****/
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/**** USB pins ****/
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USB_OTG_FS_DM = PA_11,
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USB_OTG_FS_DP = PA_12,
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USB_OTG_FS_ID = PA_10,
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@ -296,7 +296,7 @@ typedef enum {
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USB_OTG_HS_ULPI_STP = PC_0,
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USB_OTG_HS_VBUS = PB_13,
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/**** ETHERNET pins ****/
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/**** ETHERNET pins ****/
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ETH_COL = PA_3,
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ETH_CRS = PA_0,
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ETH_CRS_DV = PA_7,
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@ -323,13 +323,13 @@ typedef enum {
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ETH_TX_EN = PB_11,
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ETH_TX_EN_ALT0 = PG_11,
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/**** OSCILLATOR pins ****/
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/**** OSCILLATOR pins ****/
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RCC_OSC32_IN = PC_14,
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RCC_OSC32_OUT = PC_15,
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RCC_OSC_IN = PH_0,
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RCC_OSC_OUT = PH_1,
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/**** DEBUG pins ****/
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/**** DEBUG pins ****/
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SYS_JTCK_SWCLK = PA_14,
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SYS_JTDI = PA_15,
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SYS_JTDO_SWO = PB_3,
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@ -74,7 +74,7 @@ void analogout_init(dac_t *obj, PinName pin)
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obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
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obj->handle.State = HAL_DAC_STATE_RESET;
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if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
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if (HAL_DAC_Init(&obj->handle) != HAL_OK) {
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error("HAL_DAC_Init failed");
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}
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@ -14,7 +14,7 @@
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* limitations under the License.
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*/
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#if DEVICE_FLASH
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#if DEVICE_FLASH
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#include "flash_api.h"
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#include "flash_data.h"
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@ -99,10 +99,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
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return -1;
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}
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/* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
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you have to make sure that these data are rewritten before they are accessed during code
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execution. If this cannot be done safely, it is recommended to flush the caches by setting the
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DCRST and ICRST bits in the FLASH_CR register. */
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/* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
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you have to make sure that these data are rewritten before they are accessed during code
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execution. If this cannot be done safely, it is recommended to flush the caches by setting the
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DCRST and ICRST bits in the FLASH_CR register. */
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__HAL_FLASH_DATA_CACHE_DISABLE();
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__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
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@ -171,13 +171,13 @@ static uint32_t GetSector(uint32_t address)
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}
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#endif
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if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
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sector += tmp >>14;
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sector += tmp >> 14;
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}
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#if defined(ADDR_FLASH_SECTOR_5)
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else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
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sector += FLASH_SECTOR_4;
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} else {
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sector += 4 + (tmp >>17);
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sector += 4 + (tmp >> 17);
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}
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#else
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// In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one.
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@ -197,16 +197,16 @@ static uint32_t GetSectorSize(uint32_t Sector)
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{
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uint32_t sectorsize = 0x00;
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#if defined(FLASH_SECTOR_16)
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if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
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(Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) ||\
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(Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
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sectorsize = 16 * 1024;
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} else if((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
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if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \
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(Sector == FLASH_SECTOR_3) || (Sector == FLASH_SECTOR_12) || (Sector == FLASH_SECTOR_13) || \
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(Sector == FLASH_SECTOR_14) || (Sector == FLASH_SECTOR_15)) {
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sectorsize = 16 * 1024;
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} else if ((Sector == FLASH_SECTOR_4) || (Sector == FLASH_SECTOR_16)) {
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#else
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if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) ||\
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(Sector == FLASH_SECTOR_3)) {
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sectorsize = 16 * 1024;
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} else if(Sector == FLASH_SECTOR_4) {
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if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_SECTOR_2) || \
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(Sector == FLASH_SECTOR_3)) {
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sectorsize = 16 * 1024;
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} else if (Sector == FLASH_SECTOR_4) {
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#endif
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sectorsize = 64 * 1024;
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} else {
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@ -39,27 +39,27 @@ extern "C" {
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// until then let's define locally the required functions
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__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
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{
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SET_BIT(EXTI->RTSR, ExtiLine);
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SET_BIT(EXTI->RTSR, ExtiLine);
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}
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__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
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{
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CLEAR_BIT(EXTI->RTSR, ExtiLine);
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CLEAR_BIT(EXTI->RTSR, ExtiLine);
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}
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__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
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{
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SET_BIT(EXTI->FTSR, ExtiLine);
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SET_BIT(EXTI->FTSR, ExtiLine);
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}
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__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
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{
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CLEAR_BIT(EXTI->FTSR, ExtiLine);
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CLEAR_BIT(EXTI->FTSR, ExtiLine);
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}
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__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
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{
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SET_BIT(EXTI->IMR, ExtiLine);
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SET_BIT(EXTI->IMR, ExtiLine);
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}
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__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
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{
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CLEAR_BIT(EXTI->IMR, ExtiLine);
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CLEAR_BIT(EXTI->IMR, ExtiLine);
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}
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// Above lines shall be later defined in LL
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@ -71,35 +71,35 @@
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__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
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{
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MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
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(Alternate << (POSITION_VAL(Pin) * 4U)));
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MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
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(Alternate << (POSITION_VAL(Pin) * 4U)));
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}
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__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
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{
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MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
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(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
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MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
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(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
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}
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__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
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{
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MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
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MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
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}
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__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
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{
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return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
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return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODER0)) / (Pin * Pin));
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}
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__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
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{
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MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
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MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
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}
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__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
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{
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MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
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MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
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}
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__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
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{
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MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
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(Speed << (POSITION_VAL(Pin) * 2U)));
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MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
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(Speed << (POSITION_VAL(Pin) * 2U)));
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}
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// Above lines shall be defined in LL when available
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@ -126,14 +126,15 @@ static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint3
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}
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}
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static inline void stm_pin_SetAFPin( GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
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static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
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{
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uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
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if (STM_PIN(pin) > 7)
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if (STM_PIN(pin) > 7) {
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LL_GPIO_SetAFPin_8_15(gpio, ll_pin, afnum);
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else
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} else {
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LL_GPIO_SetAFPin_0_7(gpio, ll_pin, afnum);
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}
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}
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#endif
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@ -33,8 +33,7 @@
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#ifdef DEVICE_PWMOUT
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const pwm_apb_map_t pwm_apb_map_table[] =
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{
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const pwm_apb_map_t pwm_apb_map_table[] = {
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#if defined(TIM2_BASE)
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{PWM_2, PWMOUT_ON_APB1},
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#endif
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@ -51,7 +51,7 @@ static void uart_irq(UARTName uart_name)
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int8_t id = get_uart_index(uart_name);
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if (id >= 0) {
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UART_HandleTypeDef * huart = &uart_handlers[id];
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UART_HandleTypeDef *huart = &uart_handlers[id];
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if (serial_irq_ids[id] != 0) {
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if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) {
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if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) {
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@ -132,7 +132,7 @@ static void uart8_irq(void)
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void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
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{
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
|
||||
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj_s->index] = id;
|
||||
}
|
||||
|
|
@ -271,7 +271,7 @@ void serial_break_set(serial_t *obj)
|
|||
* LOCAL HELPER FUNCTIONS
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
/**
|
||||
* Configure the TX buffer for an asynchronous write serial transaction
|
||||
*
|
||||
* @param obj The serial object.
|
||||
|
|
@ -291,7 +291,7 @@ static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t
|
|||
obj->tx_buff.length = tx_length;
|
||||
obj->tx_buff.pos = 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Configure the RX buffer for an asynchronous write serial transaction
|
||||
*
|
||||
|
|
@ -313,7 +313,7 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
|
|||
obj->rx_buff.pos = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
* Configure events
|
||||
*
|
||||
* @param obj The serial object
|
||||
|
|
@ -321,9 +321,9 @@ static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t
|
|||
* @param enable Set to non-zero to enable events, or zero to disable them
|
||||
*/
|
||||
static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
|
||||
{
|
||||
{
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
|
||||
|
||||
// Shouldn't have to enable interrupt here, just need to keep track of the requested events.
|
||||
if (enable) {
|
||||
obj_s->events |= event;
|
||||
|
|
@ -396,7 +396,7 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
|
|||
* MBED API FUNCTIONS
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
/**
|
||||
* Begin asynchronous TX transfer. The used buffer is specified in the serial
|
||||
* object, tx_buff
|
||||
*
|
||||
|
|
@ -410,28 +410,28 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name)
|
|||
* @return Returns number of data transfered, or 0 otherwise
|
||||
*/
|
||||
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
||||
{
|
||||
{
|
||||
// TODO: DMA usage is currently ignored
|
||||
(void) hint;
|
||||
|
||||
|
||||
// Check buffer is ok
|
||||
MBED_ASSERT(tx != (void*)0);
|
||||
MBED_ASSERT(tx != (void *)0);
|
||||
MBED_ASSERT(tx_width == 8); // support only 8b width
|
||||
|
||||
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
if (tx_length == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
// Set up buffer
|
||||
serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
|
||||
|
||||
|
||||
// Set up events
|
||||
serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
|
||||
serial_enable_event(obj, event, 1); // Set only the wanted events
|
||||
|
||||
|
||||
// Enable interrupt
|
||||
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
|
||||
NVIC_ClearPendingIRQ(irq_n);
|
||||
|
|
@ -441,14 +441,14 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx
|
|||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
// the following function will enable UART_IT_TXE and error interrupts
|
||||
if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
|
||||
if (HAL_UART_Transmit_IT(huart, (uint8_t *)tx, tx_length) != HAL_OK) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
return tx_length;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
* Begin asynchronous RX transfer (enable interrupt for data collecting)
|
||||
* The used buffer is specified in the serial object, rx_buff
|
||||
*
|
||||
|
|
@ -469,18 +469,18 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
|
|||
|
||||
/* Sanity check arguments */
|
||||
MBED_ASSERT(obj);
|
||||
MBED_ASSERT(rx != (void*)0);
|
||||
MBED_ASSERT(rx != (void *)0);
|
||||
MBED_ASSERT(rx_width == 8); // support only 8b width
|
||||
|
||||
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
|
||||
serial_enable_event(obj, event, 1);
|
||||
|
||||
|
||||
// set CharMatch
|
||||
obj->char_match = char_match;
|
||||
|
||||
|
||||
serial_rx_buffer_set(obj, rx, rx_length, rx_width);
|
||||
|
||||
IRQn_Type irq_n = serial_get_irq_n(obj_s->uart);
|
||||
|
|
@ -490,8 +490,8 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
|
|||
NVIC_SetVector(irq_n, (uint32_t)handler);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
// following HAL function will enable the RXNE interrupt + error interrupts
|
||||
HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
|
||||
// following HAL function will enable the RXNE interrupt + error interrupts
|
||||
HAL_UART_Receive_IT(huart, (uint8_t *)rx, rx_length);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -503,10 +503,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt
|
|||
uint8_t serial_tx_active(serial_t *obj)
|
||||
{
|
||||
MBED_ASSERT(obj);
|
||||
|
||||
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
|
||||
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
|
||||
}
|
||||
|
||||
|
|
@ -519,20 +519,22 @@ uint8_t serial_tx_active(serial_t *obj)
|
|||
uint8_t serial_rx_active(serial_t *obj)
|
||||
{
|
||||
MBED_ASSERT(obj);
|
||||
|
||||
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
|
||||
return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
|
||||
}
|
||||
|
||||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
|
||||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
|
||||
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
|
||||
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
|
||||
} else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
|
||||
|
|
@ -554,49 +556,49 @@ int serial_irq_handler_asynch(serial_t *obj)
|
|||
{
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
|
||||
volatile int return_event = 0;
|
||||
uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
|
||||
uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer);
|
||||
uint8_t i = 0;
|
||||
|
||||
|
||||
// TX PART:
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
|
||||
if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
|
||||
// Return event SERIAL_EVENT_TX_COMPLETE if requested
|
||||
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
|
||||
if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE) != 0) {
|
||||
return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// Handle error events
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
|
||||
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
|
||||
return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
|
||||
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
|
||||
return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
|
||||
if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
|
||||
return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
HAL_UART_IRQHandler(huart);
|
||||
|
||||
|
||||
// Abort if an error occurs
|
||||
if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
|
||||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
|
||||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
|
||||
(return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
|
||||
(return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
|
||||
return return_event;
|
||||
}
|
||||
|
||||
|
||||
//RX PART
|
||||
if (huart->RxXferSize != 0) {
|
||||
obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
|
||||
|
|
@ -604,7 +606,7 @@ int serial_irq_handler_asynch(serial_t *obj)
|
|||
if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
|
||||
return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
|
||||
}
|
||||
|
||||
|
||||
// Check if char_match is present
|
||||
if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
|
||||
if (buf != NULL) {
|
||||
|
|
@ -618,11 +620,11 @@ int serial_irq_handler_asynch(serial_t *obj)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
return return_event;
|
||||
|
||||
return return_event;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
* Abort the ongoing TX transaction. It disables the enabled interupt for TX and
|
||||
* flush TX hardware buffer if TX FIFO is used
|
||||
*
|
||||
|
|
@ -632,17 +634,17 @@ void serial_tx_abort_asynch(serial_t *obj)
|
|||
{
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
|
||||
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
|
||||
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
|
||||
|
||||
|
||||
// clear flags
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
|
||||
|
||||
// reset states
|
||||
huart->TxXferCount = 0;
|
||||
// update handle state
|
||||
if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
|
||||
if (huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
|
||||
huart->gState = HAL_UART_STATE_BUSY_RX;
|
||||
} else {
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
|
|
@ -659,20 +661,20 @@ void serial_rx_abort_asynch(serial_t *obj)
|
|||
{
|
||||
struct serial_s *obj_s = SERIAL_S(obj);
|
||||
UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
|
||||
|
||||
|
||||
// disable interrupts
|
||||
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
|
||||
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
|
||||
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
|
||||
|
||||
|
||||
// clear flags
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
|
||||
volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear error flags
|
||||
|
||||
|
||||
// reset states
|
||||
huart->RxXferCount = 0;
|
||||
// update handle state
|
||||
if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
|
||||
if (huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
|
||||
huart->RxState = HAL_UART_STATE_BUSY_TX;
|
||||
} else {
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
|
@ -702,9 +704,9 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
|
|||
obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
|
||||
MBED_ASSERT(obj_s->uart != (UARTName)NC);
|
||||
|
||||
if(type == FlowControlNone) {
|
||||
if (type == FlowControlNone) {
|
||||
// Disable hardware flow control
|
||||
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
|
||||
obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
|
||||
}
|
||||
if (type == FlowControlRTS) {
|
||||
// Enable RTS
|
||||
|
|
@ -734,7 +736,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
|
|||
// Enable the pin for RTS function
|
||||
pinmap_pinout(rxflow, PinMap_UART_RTS);
|
||||
}
|
||||
|
||||
|
||||
init_uart(obj);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -39,20 +39,21 @@
|
|||
#include "mbed_error.h"
|
||||
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
|
||||
#define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
|
||||
#else
|
||||
#define SPI_S(obj) (( struct spi_s *)(obj))
|
||||
#define SPI_S(obj) (( struct spi_s *)(obj))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Only the frequency is managed in the family specific part
|
||||
* the rest of SPI management is common to all STM32 families
|
||||
*/
|
||||
int spi_get_clock_freq(spi_t *obj) {
|
||||
int spi_get_clock_freq(spi_t *obj)
|
||||
{
|
||||
struct spi_s *spiobj = SPI_S(obj);
|
||||
int spi_hz = 0;
|
||||
int spi_hz = 0;
|
||||
|
||||
/* Get source clock depending on SPI instance */
|
||||
/* Get source clock depending on SPI instance */
|
||||
switch ((int)spiobj->spi) {
|
||||
case SPI_1:
|
||||
#if defined SPI4_BASE
|
||||
|
|
|
|||
Loading…
Reference in New Issue